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Commit 8e816bb4 authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915: Use enum plane_id in SKL plane code 

Replace the intel_plane->plane and hardcoded 0 usage in the SKL plane
code with intel_plane->id.

This should make the SKL "primary" and "sprite" code virtually
identical, so the next logical step would likely be dropping one
of the copies.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1479830524-7882-5-git-send-email-ville.syrjala@linux.intel.com
parent d5cdfdf5
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Showing with 37 additions and 36 deletions
drivers/gpu/drm/i915/intel_display.c
View file @ 8e816bb4
...@@ -3378,7 +3378,8 @@ static void skylake_update_primary_plane(struct drm_plane *plane, ...@@ -3378,7 +3378,8 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_framebuffer *fb = plane_state->base.fb; struct drm_framebuffer *fb = plane_state->base.fb;
int pipe = intel_crtc->pipe; enum plane_id plane_id = to_intel_plane(plane)->id;
enum pipe pipe = to_intel_plane(plane)->pipe;
u32 plane_ctl; u32 plane_ctl;
unsigned int rotation = plane_state->base.rotation; unsigned int rotation = plane_state->base.rotation;
u32 stride = skl_plane_stride(fb, 0, rotation); u32 stride = skl_plane_stride(fb, 0, rotation);
...@@ -3413,30 +3414,30 @@ static void skylake_update_primary_plane(struct drm_plane *plane, ...@@ -3413,30 +3414,30 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
intel_crtc->adjusted_x = src_x; intel_crtc->adjusted_x = src_x;
intel_crtc->adjusted_y = src_y; intel_crtc->adjusted_y = src_y;
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x); I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
I915_WRITE(PLANE_STRIDE(pipe, 0), stride); I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w); I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
if (scaler_id >= 0) { if (scaler_id >= 0) {
uint32_t ps_ctrl = 0; uint32_t ps_ctrl = 0;
WARN_ON(!dst_w || !dst_h); WARN_ON(!dst_w || !dst_h);
ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
crtc_state->scaler_state.scalers[scaler_id].mode; crtc_state->scaler_state.scalers[scaler_id].mode;
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
I915_WRITE(PLANE_POS(pipe, 0), 0); I915_WRITE(PLANE_POS(pipe, plane_id), 0);
} else { } else {
I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
} }
I915_WRITE(PLANE_SURF(pipe, 0), I915_WRITE(PLANE_SURF(pipe, plane_id),
intel_fb_gtt_offset(fb, rotation) + surf_addr); intel_fb_gtt_offset(fb, rotation) + surf_addr);
POSTING_READ(PLANE_SURF(pipe, 0)); POSTING_READ(PLANE_SURF(pipe, plane_id));
} }
static void skylake_disable_primary_plane(struct drm_plane *primary, static void skylake_disable_primary_plane(struct drm_plane *primary,
...@@ -3444,12 +3445,12 @@ static void skylake_disable_primary_plane(struct drm_plane *primary, ...@@ -3444,12 +3445,12 @@ static void skylake_disable_primary_plane(struct drm_plane *primary,
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); enum plane_id plane_id = to_intel_plane(primary)->id;
int pipe = intel_crtc->pipe; enum pipe pipe = to_intel_plane(primary)->pipe;
I915_WRITE(PLANE_CTL(pipe, 0), 0); I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
I915_WRITE(PLANE_SURF(pipe, 0), 0); I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
POSTING_READ(PLANE_SURF(pipe, 0)); POSTING_READ(PLANE_SURF(pipe, plane_id));
} }
/* Assume fb object is pinned & idle & fenced and just update base pointers */ /* Assume fb object is pinned & idle & fenced and just update base pointers */
......
drivers/gpu/drm/i915/intel_sprite.c
View file @ 8e816bb4
...@@ -203,8 +203,8 @@ skl_update_plane(struct drm_plane *drm_plane, ...@@ -203,8 +203,8 @@ skl_update_plane(struct drm_plane *drm_plane,
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *intel_plane = to_intel_plane(drm_plane); struct intel_plane *intel_plane = to_intel_plane(drm_plane);
struct drm_framebuffer *fb = plane_state->base.fb; struct drm_framebuffer *fb = plane_state->base.fb;
const int pipe = intel_plane->pipe; enum plane_id plane_id = intel_plane->id;
const int plane = intel_plane->plane + 1; enum pipe pipe = intel_plane->pipe;
u32 plane_ctl; u32 plane_ctl;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr = plane_state->main.offset; u32 surf_addr = plane_state->main.offset;
...@@ -229,9 +229,9 @@ skl_update_plane(struct drm_plane *drm_plane, ...@@ -229,9 +229,9 @@ skl_update_plane(struct drm_plane *drm_plane,
plane_ctl |= skl_plane_ctl_rotation(rotation); plane_ctl |= skl_plane_ctl_rotation(rotation);
if (key->flags) { if (key->flags) {
I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); I915_WRITE(PLANE_KEYVAL(pipe, plane_id), key->min_value);
I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); I915_WRITE(PLANE_KEYMAX(pipe, plane_id), key->max_value);
I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); I915_WRITE(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
} }
if (key->flags & I915_SET_COLORKEY_DESTINATION) if (key->flags & I915_SET_COLORKEY_DESTINATION)
...@@ -245,36 +245,36 @@ skl_update_plane(struct drm_plane *drm_plane, ...@@ -245,36 +245,36 @@ skl_update_plane(struct drm_plane *drm_plane,
crtc_w--; crtc_w--;
crtc_h--; crtc_h--;
I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x); I915_WRITE(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
I915_WRITE(PLANE_STRIDE(pipe, plane), stride); I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w); I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
/* program plane scaler */ /* program plane scaler */
if (plane_state->scaler_id >= 0) { if (plane_state->scaler_id >= 0) {
int scaler_id = plane_state->scaler_id; int scaler_id = plane_state->scaler_id;
const struct intel_scaler *scaler; const struct intel_scaler *scaler;
DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n",
PS_PLANE_SEL(plane)); plane_id, PS_PLANE_SEL(plane_id));
scaler = &crtc_state->scaler_state.scalers[scaler_id]; scaler = &crtc_state->scaler_state.scalers[scaler_id];
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode); PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
((crtc_w + 1) << 16)|(crtc_h + 1)); ((crtc_w + 1) << 16)|(crtc_h + 1));
I915_WRITE(PLANE_POS(pipe, plane), 0); I915_WRITE(PLANE_POS(pipe, plane_id), 0);
} else { } else {
I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); I915_WRITE(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
} }
I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
I915_WRITE(PLANE_SURF(pipe, plane), I915_WRITE(PLANE_SURF(pipe, plane_id),
intel_fb_gtt_offset(fb, rotation) + surf_addr); intel_fb_gtt_offset(fb, rotation) + surf_addr);
POSTING_READ(PLANE_SURF(pipe, plane)); POSTING_READ(PLANE_SURF(pipe, plane_id));
} }
static void static void
...@@ -283,13 +283,13 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) ...@@ -283,13 +283,13 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
struct drm_device *dev = dplane->dev; struct drm_device *dev = dplane->dev;
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *intel_plane = to_intel_plane(dplane); struct intel_plane *intel_plane = to_intel_plane(dplane);
const int pipe = intel_plane->pipe; enum plane_id plane_id = intel_plane->id;
const int plane = intel_plane->plane + 1; enum pipe pipe = intel_plane->pipe;
I915_WRITE(PLANE_CTL(pipe, plane), 0); I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
I915_WRITE(PLANE_SURF(pipe, plane), 0); I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
POSTING_READ(PLANE_SURF(pipe, plane)); POSTING_READ(PLANE_SURF(pipe, plane_id));
} }
static void static void
......
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