Commit 8e99e770 authored by Abel Vesa's avatar Abel Vesa Committed by Bjorn Andersson

arm64: dts: qcom: x1e80100: Fix PCIe 6a reg offsets and add MHI

The actual size of the DBI region is 0xf20 and the start of the
ELBI region is 0xf40, according to the documentation. So fix them.
While at it, add the MHI region as well.

Fixes: 5eb83fc1 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Acked-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240604-x1e80100-dts-fixes-pcie6a-v2-1-0b4d8c6256e5@linaro.orgSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 41fca593
...@@ -2737,15 +2737,17 @@ pcie6a: pci@1bf8000 { ...@@ -2737,15 +2737,17 @@ pcie6a: pci@1bf8000 {
device_type = "pci"; device_type = "pci";
compatible = "qcom,pcie-x1e80100"; compatible = "qcom,pcie-x1e80100";
reg = <0 0x01bf8000 0 0x3000>, reg = <0 0x01bf8000 0 0x3000>,
<0 0x70000000 0 0xf1d>, <0 0x70000000 0 0xf20>,
<0 0x70000f20 0 0xa8>, <0 0x70000f40 0 0xa8>,
<0 0x70001000 0 0x1000>, <0 0x70001000 0 0x1000>,
<0 0x70100000 0 0x100000>; <0 0x70100000 0 0x100000>,
<0 0x01bfb000 0 0x1000>;
reg-names = "parf", reg-names = "parf",
"dbi", "dbi",
"elbi", "elbi",
"atu", "atu",
"config"; "config",
"mhi";
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>,
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment