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Kirill Smelkov
linux
Commits
8eb8462c
Commit
8eb8462c
authored
Jul 19, 2003
by
David S. Miller
Browse files
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Plain Diff
[SPARC64]: Add Ultra-IIIi/Jalapeno support.
parent
c8c70605
Changes
2
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Inline
Side-by-side
Showing
2 changed files
with
24 additions
and
7 deletions
+24
-7
arch/sparc64/kernel/cpu.c
arch/sparc64/kernel/cpu.c
+4
-2
arch/sparc64/kernel/smp.c
arch/sparc64/kernel/smp.c
+20
-5
No files found.
arch/sparc64/kernel/cpu.c
View file @
8eb8462c
...
...
@@ -34,6 +34,7 @@ struct cpu_fp_info linux_sparc_fpu[] = {
{
0x17
,
0x13
,
0
,
"UltraSparc IIe integrated FPU"
},
{
0x3e
,
0x14
,
0
,
"UltraSparc III integrated FPU"
},
{
0x3e
,
0x15
,
0
,
"UltraSparc III+ integrated FPU"
},
{
0x3e
,
0x16
,
0
,
"UltraSparc IIIi integrated FPU"
},
};
#define NSPARCFPU (sizeof(linux_sparc_fpu)/sizeof(struct cpu_fp_info))
...
...
@@ -42,10 +43,11 @@ struct cpu_iu_info linux_sparc_chips[] = {
{
0x17
,
0x10
,
"TI UltraSparc I (SpitFire)"
},
{
0x22
,
0x10
,
"TI UltraSparc I (SpitFire)"
},
{
0x17
,
0x11
,
"TI UltraSparc II (BlackBird)"
},
{
0x17
,
0x12
,
"TI UltraSparc IIi"
},
{
0x17
,
0x13
,
"TI UltraSparc IIe"
},
{
0x17
,
0x12
,
"TI UltraSparc IIi
(Sabre)
"
},
{
0x17
,
0x13
,
"TI UltraSparc IIe
(Hummingbird)
"
},
{
0x3e
,
0x14
,
"TI UltraSparc III (Cheetah)"
},
{
0x3e
,
0x15
,
"TI UltraSparc III+ (Cheetah+)"
},
{
0x3e
,
0x16
,
"TI UltraSparc IIIi (Jalapeno)"
},
};
#define NSPARCCHIPS (sizeof(linux_sparc_chips)/sizeof(struct cpu_iu_info))
...
...
arch/sparc64/kernel/smp.c
View file @
8eb8462c
...
...
@@ -445,12 +445,19 @@ static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, u
#endif
static
void
cheetah_xcall_deliver
(
u64
data0
,
u64
data1
,
u64
data2
,
unsigned
long
mask
)
{
u64
pstate
;
int
nack_busy_id
;
u64
pstate
,
ver
;
int
nack_busy_id
,
is_jalapeno
;
if
(
!
mask
)
return
;
/* Unfortunately, someone at Sun had the brilliant idea to make the
* busy/nack fields hard-coded by ITID number for this Ultra-III
* derivative processor.
*/
__asm__
(
"rdpr %%ver, %0"
:
"=r"
(
ver
));
is_jalapeno
=
((
ver
>>
32
)
==
0x003e0016
);
__asm__
__volatile__
(
"rdpr %%pstate, %0"
:
"=r"
(
pstate
));
retry:
...
...
@@ -476,12 +483,14 @@ static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, unsigned long
if
(
work_mask
&
(
1UL
<<
i
))
{
u64
target
=
(
i
<<
14
)
|
0x70
;
target
|=
(
nack_busy_id
++
<<
24
);
if
(
!
is_jalapeno
)
target
|=
(
nack_busy_id
<<
24
);
__asm__
__volatile__
(
"stxa %%g0, [%0] %1
\n\t
"
"membar #Sync
\n\t
"
:
/* no outputs */
:
"r"
(
target
),
"i"
(
ASI_INTR_W
));
nack_busy_id
++
;
work_mask
&=
~
(
1UL
<<
i
);
if
(
!
work_mask
)
break
;
...
...
@@ -531,8 +540,14 @@ static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, unsigned long
*/
for
(
i
=
0
;
i
<
NR_CPUS
;
i
++
)
{
if
(
work_mask
&
(
1UL
<<
i
))
{
if
((
dispatch_stat
&
(
0x2
<<
this_busy_nack
))
==
0
)
u64
check_mask
;
if
(
is_jalapeno
)
check_mask
=
(
0x2UL
<<
(
2
*
i
));
else
check_mask
=
(
0x2UL
<<
this_busy_nack
);
if
((
dispatch_stat
&
check_mask
)
==
0
)
mask
&=
~
(
1UL
<<
i
);
this_busy_nack
+=
2
;
work_mask
&=
~
(
1UL
<<
i
);
...
...
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