Commit 8f668fbb authored by Max Filippov's avatar Max Filippov Committed by Greg Kroah-Hartman

USB: c67x00: add proper delays to HPI read/write

According to CY7C67300 specification HPI read and write cycle duration
Tcyc must be at least 6T long, where T is 1/48MHz, which is 125ns.
Without this delay fast host processor cannot write to chip registers.
Add proper ndelay to hpi_{read,write}_reg.
Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
Acked-by: default avatarPeter Korsgaard <peter@korsgaard.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 543d7784
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
*/ */
#include <asm/byteorder.h> #include <asm/byteorder.h>
#include <linux/delay.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/jiffies.h> #include <linux/jiffies.h>
#include <linux/usb/c67x00.h> #include <linux/usb/c67x00.h>
...@@ -73,13 +74,22 @@ struct c67x00_lcp_int_data { ...@@ -73,13 +74,22 @@ struct c67x00_lcp_int_data {
#define HPI_ADDR 2 #define HPI_ADDR 2
#define HPI_STATUS 3 #define HPI_STATUS 3
/*
* According to CY7C67300 specification (tables 140 and 141) HPI read and
* write cycle duration Tcyc must be at least 6T long, where T is 1/48MHz,
* which is 125ns.
*/
#define HPI_T_CYC_NS 125
static inline u16 hpi_read_reg(struct c67x00_device *dev, int reg) static inline u16 hpi_read_reg(struct c67x00_device *dev, int reg)
{ {
ndelay(HPI_T_CYC_NS);
return __raw_readw(dev->hpi.base + reg * dev->hpi.regstep); return __raw_readw(dev->hpi.base + reg * dev->hpi.regstep);
} }
static inline void hpi_write_reg(struct c67x00_device *dev, int reg, u16 value) static inline void hpi_write_reg(struct c67x00_device *dev, int reg, u16 value)
{ {
ndelay(HPI_T_CYC_NS);
__raw_writew(value, dev->hpi.base + reg * dev->hpi.regstep); __raw_writew(value, dev->hpi.base + reg * dev->hpi.regstep);
} }
......
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