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Commit 8fbca791 authored by Ben Hutchings's avatar Ben Hutchings Committed by David S. Miller
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sfc: Remove support for SFN4111T, SFT9001 and Falcon GMAC 

SFN4111T never reached production and is not being used for internal
or customer testing.

Since we have no production Falcon boards using the SFT9001 or the
GMAC, remove support for them as well.
Signed-off-by: default avatarBen Hutchings <bhutchings@solarflare.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a0741ca9
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Showing with 56 additions and 893 deletions
drivers/net/sfc/Makefile
View file @ 8fbca791
sfc-y += efx.o nic.o falcon.o siena.o tx.o rx.o filter.o \
falcon_gmac.o falcon_xmac.o mcdi_mac.o \
falcon_xmac.o mcdi_mac.o \
selftest.o ethtool.o qt202x_phy.o mdio_10g.o \
tenxpress.o falcon_boards.o mcdi.o mcdi_phy.o
sfc-$(CONFIG_SFC_MTD) += mtd.o
......
drivers/net/sfc/falcon.c
View file @ 8fbca791
......@@ -446,16 +446,6 @@ static void falcon_reset_macs(struct efx_nic *efx)
/* It's not safe to use GLB_CTL_REG to reset the
* macs, so instead use the internal MAC resets
*/
if (!EFX_IS10G(efx)) {
EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
efx_writeo(efx, &reg, FR_AB_GM_CFG1);
udelay(1000);
EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
efx_writeo(efx, &reg, FR_AB_GM_CFG1);
udelay(1000);
return;
} else {
EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
......@@ -470,7 +460,6 @@ static void falcon_reset_macs(struct efx_nic *efx)
netif_err(efx, hw, efx->net_dev,
"timed out waiting for XMAC core reset\n");
}
}
/* Mac stats will fail whist the TX fifo is draining */
WARN_ON(nic_data->stats_disable_count == 0);
......@@ -508,7 +497,6 @@ static void falcon_reset_macs(struct efx_nic *efx)
* are re-enabled by the caller */
efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
/* This can run even when the GMAC is selected */
falcon_setup_xaui(efx);
}
......@@ -646,8 +634,6 @@ static void falcon_stats_timer_func(unsigned long context)
spin_unlock(&efx->stats_lock);
}
static void falcon_switch_mac(struct efx_nic *efx);
static bool falcon_loopback_link_poll(struct efx_nic *efx)
{
struct efx_link_state old_state = efx->link_state;
......@@ -658,10 +644,6 @@ static bool falcon_loopback_link_poll(struct efx_nic *efx)
efx->link_state.fd = true;
efx->link_state.fc = efx->wanted_fc;
efx->link_state.up = true;
if (efx->loopback_mode == LOOPBACK_GMAC)
efx->link_state.speed = 1000;
else
efx->link_state.speed = 10000;
return !efx_link_state_equal(&efx->link_state, &old_state);
......@@ -685,7 +667,7 @@ static int falcon_reconfigure_port(struct efx_nic *efx)
falcon_stop_nic_stats(efx);
falcon_deconfigure_mac_wrapper(efx);
falcon_switch_mac(efx);
falcon_reset_macs(efx);
efx->phy_op->reconfigure(efx);
rc = efx->mac_op->reconfigure(efx);
......@@ -835,69 +817,16 @@ static int falcon_mdio_read(struct net_device *net_dev,
return rc;
}
static void falcon_clock_mac(struct efx_nic *efx)
{
unsigned strap_val;
efx_oword_t nic_stat;
/* Configure the NIC generated MAC clock correctly */
efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
strap_val = EFX_IS10G(efx) ? 5 : 3;
if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
} else {
/* Falcon A1 does not support 1G/10G speed switching
* and must not be used with a PHY that does. */
BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
strap_val);
}
}
static void falcon_switch_mac(struct efx_nic *efx)
{
struct efx_mac_operations *old_mac_op = efx->mac_op;
struct falcon_nic_data *nic_data = efx->nic_data;
unsigned int stats_done_offset;
WARN_ON(!mutex_is_locked(&efx->mac_lock));
WARN_ON(nic_data->stats_disable_count == 0);
efx->mac_op = (EFX_IS10G(efx) ?
&falcon_xmac_operations : &falcon_gmac_operations);
if (EFX_IS10G(efx))
stats_done_offset = XgDmaDone_offset;
else
stats_done_offset = GDmaDone_offset;
nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset;
if (old_mac_op == efx->mac_op)
return;
falcon_clock_mac(efx);
netif_dbg(efx, hw, efx->net_dev, "selected %cMAC\n",
EFX_IS10G(efx) ? 'X' : 'G');
/* Not all macs support a mac-level link state */
efx->xmac_poll_required = false;
falcon_reset_macs(efx);
}
/* This call is responsible for hooking in the MAC and PHY operations */
static int falcon_probe_port(struct efx_nic *efx)
{
struct falcon_nic_data *nic_data = efx->nic_data;
int rc;
switch (efx->phy_type) {
case PHY_TYPE_SFX7101:
efx->phy_op = &falcon_sfx7101_phy_ops;
break;
case PHY_TYPE_SFT9001A:
case PHY_TYPE_SFT9001B:
efx->phy_op = &falcon_sft9001_phy_ops;
break;
case PHY_TYPE_QT2022C2:
case PHY_TYPE_QT2025C:
efx->phy_op = &falcon_qt202x_phy_ops;
......@@ -937,6 +866,7 @@ static int falcon_probe_port(struct efx_nic *efx)
(u64)efx->stats_buffer.dma_addr,
efx->stats_buffer.addr,
(u64)virt_to_phys(efx->stats_buffer.addr));
nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset;
return 0;
}
......@@ -1201,7 +1131,7 @@ static void falcon_monitor(struct efx_nic *efx)
falcon_stop_nic_stats(efx);
falcon_deconfigure_mac_wrapper(efx);
falcon_switch_mac(efx);
falcon_reset_macs(efx);
rc = efx->mac_op->reconfigure(efx);
BUG_ON(rc);
......@@ -1210,7 +1140,6 @@ static void falcon_monitor(struct efx_nic *efx)
efx_link_status_changed(efx);
}
if (EFX_IS10G(efx))
falcon_poll_xmac(efx);
}
......@@ -1604,16 +1533,6 @@ static int falcon_init_nic(struct efx_nic *efx)
EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
efx_writeo(efx, &temp, FR_AB_NIC_STAT);
/* Set the source of the GMAC clock */
if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) {
efx_reado(efx, &temp, FR_AB_GPIO_CTL);
EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
}
/* Select the correct MAC */
falcon_clock_mac(efx);
rc = falcon_reset_sram(efx);
if (rc)
return rc;
......
drivers/net/sfc/falcon_boards.c
View file @ 8fbca791
......@@ -26,7 +26,6 @@
/* Board types */
#define FALCON_BOARD_SFE4001 0x01
#define FALCON_BOARD_SFE4002 0x02
#define FALCON_BOARD_SFN4111T 0x51
#define FALCON_BOARD_SFN4112F 0x52
/* Board temperature is about 15°C above ambient when air flow is
......@@ -142,17 +141,17 @@ static inline int efx_check_lm87(struct efx_nic *efx, unsigned mask)
#endif /* CONFIG_SENSORS_LM87 */
/*****************************************************************************
* Support for the SFE4001 and SFN4111T NICs.
* Support for the SFE4001 NIC.
*
* The SFE4001 does not power-up fully at reset due to its high power
* consumption. We control its power via a PCA9539 I/O expander.
* Both boards have a MAX6647 temperature monitor which we expose to
* It also has a MAX6647 temperature monitor which we expose to
* the lm90 driver.
*
* This also provides minimal support for reflashing the PHY, which is
* initiated by resetting it with the FLASH_CFG_1 pin pulled down.
* On SFE4001 rev A2 and later this is connected to the 3V3X output of
* the IO-expander; on the SFN4111T it is connected to Falcon's GPIO3.
* the IO-expander.
* We represent reflash mode as PHY_MODE_SPECIAL and make it mutually
* exclusive with the network device being open.
*/
......@@ -304,34 +303,6 @@ static int sfe4001_poweron(struct efx_nic *efx)
return rc;
}
static int sfn4111t_reset(struct efx_nic *efx)
{
struct falcon_board *board = falcon_board(efx);
efx_oword_t reg;
/* GPIO 3 and the GPIO register are shared with I2C, so block that */
i2c_lock_adapter(&board->i2c_adap);
/* Pull RST_N (GPIO 2) low then let it up again, setting the
* FLASH_CFG_1 strap (GPIO 3) appropriately. Only change the
* output enables; the output levels should always be 0 (low)
* and we rely on external pull-ups. */
efx_reado(efx, &reg, FR_AB_GPIO_CTL);
EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, true);
efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
msleep(1000);
EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, false);
EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN,
!!(efx->phy_mode & PHY_MODE_SPECIAL));
efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
msleep(1);
i2c_unlock_adapter(&board->i2c_adap);
ssleep(1);
return 0;
}
static ssize_t show_phy_flash_cfg(struct device *dev,
struct device_attribute *attr, char *buf)
{
......@@ -363,10 +334,7 @@ static ssize_t set_phy_flash_cfg(struct device *dev,
efx->phy_mode = new_mode;
if (new_mode & PHY_MODE_SPECIAL)
falcon_stop_nic_stats(efx);
if (falcon_board(efx)->type->id == FALCON_BOARD_SFE4001)
err = sfe4001_poweron(efx);
else
err = sfn4111t_reset(efx);
if (!err)
err = efx_reconfigure_port(efx);
if (!(new_mode & PHY_MODE_SPECIAL))
......@@ -479,83 +447,6 @@ static int sfe4001_init(struct efx_nic *efx)
return rc;
}
static int sfn4111t_check_hw(struct efx_nic *efx)
{
s32 status;
/* If XAUI link is up then do not monitor */
if (EFX_WORKAROUND_7884(efx) && !efx->xmac_poll_required)
return 0;
/* Test LHIGH, RHIGH, FAULT, EOT and IOT alarms */
status = i2c_smbus_read_byte_data(falcon_board(efx)->hwmon_client,
MAX664X_REG_RSL);
if (status < 0)
return -EIO;
if (status & 0x57)
return -ERANGE;
return 0;
}
static void sfn4111t_fini(struct efx_nic *efx)
{
netif_info(efx, drv, efx->net_dev, "%s\n", __func__);
device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_flash_cfg);
i2c_unregister_device(falcon_board(efx)->hwmon_client);
}
static struct i2c_board_info sfn4111t_a0_hwmon_info = {
I2C_BOARD_INFO("max6647", 0x4e),
};
static struct i2c_board_info sfn4111t_r5_hwmon_info = {
I2C_BOARD_INFO("max6646", 0x4d),
};
static void sfn4111t_init_phy(struct efx_nic *efx)
{
if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
if (sft9001_wait_boot(efx) != -EINVAL)
return;
efx->phy_mode = PHY_MODE_SPECIAL;
falcon_stop_nic_stats(efx);
}
sfn4111t_reset(efx);
sft9001_wait_boot(efx);
}
static int sfn4111t_init(struct efx_nic *efx)
{
struct falcon_board *board = falcon_board(efx);
int rc;
board->hwmon_client =
i2c_new_device(&board->i2c_adap,
(board->minor < 5) ?
&sfn4111t_a0_hwmon_info :
&sfn4111t_r5_hwmon_info);
if (!board->hwmon_client)
return -EIO;
rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_flash_cfg);
if (rc)
goto fail_hwmon;
if (efx->phy_mode & PHY_MODE_SPECIAL)
/* PHY may not generate a 156.25 MHz clock and MAC
* stats fetch will fail. */
falcon_stop_nic_stats(efx);
return 0;
fail_hwmon:
i2c_unregister_device(board->hwmon_client);
return rc;
}
/*****************************************************************************
* Support for the SFE4002
*
......@@ -712,16 +603,6 @@ static const struct falcon_board_type board_types[] = {
.set_id_led = sfe4002_set_id_led,
.monitor = sfe4002_check_hw,
},
{
.id = FALCON_BOARD_SFN4111T,
.ref_model = "SFN4111T",
.gen_type = "100/1000/10GBASE-T adapter",
.init = sfn4111t_init,
.init_phy = sfn4111t_init_phy,
.fini = sfn4111t_fini,
.set_id_led = tenxpress_set_id_led,
.monitor = sfn4111t_check_hw,
},
{
.id = FALCON_BOARD_SFN4112F,
.ref_model = "SFN4112F",
......
drivers/net/sfc/falcon_gmac.c deleted 100644 → 0
View file @ a0741ca9
/****************************************************************************
* Driver for Solarflare Solarstorm network controllers and boards
* Copyright 2005-2006 Fen Systems Ltd.
* Copyright 2006-2009 Solarflare Communications Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation, incorporated herein by reference.
*/
#include <linux/delay.h>
#include "net_driver.h"
#include "efx.h"
#include "nic.h"
#include "mac.h"
#include "regs.h"
#include "io.h"
/**************************************************************************
*
* MAC operations
*
*************************************************************************/
static int falcon_reconfigure_gmac(struct efx_nic *efx)
{
struct efx_link_state *link_state = &efx->link_state;
bool loopback, tx_fc, rx_fc, bytemode;
int if_mode;
unsigned int max_frame_len;
efx_oword_t reg;
/* Configuration register 1 */
tx_fc = (link_state->fc & EFX_FC_TX) || !link_state->fd;
rx_fc = !!(link_state->fc & EFX_FC_RX);
loopback = (efx->loopback_mode == LOOPBACK_GMAC);
bytemode = (link_state->speed == 1000);
EFX_POPULATE_OWORD_5(reg,
FRF_AB_GM_LOOP, loopback,
FRF_AB_GM_TX_EN, 1,
FRF_AB_GM_TX_FC_EN, tx_fc,
FRF_AB_GM_RX_EN, 1,
FRF_AB_GM_RX_FC_EN, rx_fc);
efx_writeo(efx, &reg, FR_AB_GM_CFG1);
udelay(10);
/* Configuration register 2 */
if_mode = (bytemode) ? 2 : 1;
EFX_POPULATE_OWORD_5(reg,
FRF_AB_GM_IF_MODE, if_mode,
FRF_AB_GM_PAD_CRC_EN, 1,
FRF_AB_GM_LEN_CHK, 1,
FRF_AB_GM_FD, link_state->fd,
FRF_AB_GM_PAMBL_LEN, 0x7/*datasheet recommended */);
efx_writeo(efx, &reg, FR_AB_GM_CFG2);
udelay(10);
/* Max frame len register */
max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_MAX_FLEN, max_frame_len);
efx_writeo(efx, &reg, FR_AB_GM_MAX_FLEN);
udelay(10);
/* FIFO configuration register 0 */
EFX_POPULATE_OWORD_5(reg,
FRF_AB_GMF_FTFENREQ, 1,
FRF_AB_GMF_STFENREQ, 1,
FRF_AB_GMF_FRFENREQ, 1,
FRF_AB_GMF_SRFENREQ, 1,
FRF_AB_GMF_WTMENREQ, 1);
efx_writeo(efx, &reg, FR_AB_GMF_CFG0);
udelay(10);
/* FIFO configuration register 1 */
EFX_POPULATE_OWORD_2(reg,
FRF_AB_GMF_CFGFRTH, 0x12,
FRF_AB_GMF_CFGXOFFRTX, 0xffff);
efx_writeo(efx, &reg, FR_AB_GMF_CFG1);
udelay(10);
/* FIFO configuration register 2 */
EFX_POPULATE_OWORD_2(reg,
FRF_AB_GMF_CFGHWM, 0x3f,
FRF_AB_GMF_CFGLWM, 0xa);
efx_writeo(efx, &reg, FR_AB_GMF_CFG2);
udelay(10);
/* FIFO configuration register 3 */
EFX_POPULATE_OWORD_2(reg,
FRF_AB_GMF_CFGHWMFT, 0x1c,
FRF_AB_GMF_CFGFTTH, 0x08);
efx_writeo(efx, &reg, FR_AB_GMF_CFG3);
udelay(10);
/* FIFO configuration register 4 */
EFX_POPULATE_OWORD_1(reg, FRF_AB_GMF_HSTFLTRFRM_PAUSE, 1);
efx_writeo(efx, &reg, FR_AB_GMF_CFG4);
udelay(10);
/* FIFO configuration register 5 */
efx_reado(efx, &reg, FR_AB_GMF_CFG5);
EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGBYTMODE, bytemode);
EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGHDPLX, !link_state->fd);
EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTDRPLT64, !link_state->fd);
EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTFLTRFRMDC_PAUSE, 0);
efx_writeo(efx, &reg, FR_AB_GMF_CFG5);
udelay(10);
/* MAC address */
EFX_POPULATE_OWORD_4(reg,
FRF_AB_GM_ADR_B0, efx->net_dev->dev_addr[5],
FRF_AB_GM_ADR_B1, efx->net_dev->dev_addr[4],
FRF_AB_GM_ADR_B2, efx->net_dev->dev_addr[3],
FRF_AB_GM_ADR_B3, efx->net_dev->dev_addr[2]);
efx_writeo(efx, &reg, FR_AB_GM_ADR1);
udelay(10);
EFX_POPULATE_OWORD_2(reg,
FRF_AB_GM_ADR_B4, efx->net_dev->dev_addr[1],
FRF_AB_GM_ADR_B5, efx->net_dev->dev_addr[0]);
efx_writeo(efx, &reg, FR_AB_GM_ADR2);
udelay(10);
falcon_reconfigure_mac_wrapper(efx);
return 0;
}
static void falcon_update_stats_gmac(struct efx_nic *efx)
{
struct efx_mac_stats *mac_stats = &efx->mac_stats;
unsigned long old_rx_pause, old_tx_pause;
unsigned long new_rx_pause, new_tx_pause;
/* Pause frames are erroneously counted as errors (SFC bug 3269) */
old_rx_pause = mac_stats->rx_pause;
old_tx_pause = mac_stats->tx_pause;
/* Update MAC stats from DMAed values */
FALCON_STAT(efx, GRxGoodOct, rx_good_bytes);
FALCON_STAT(efx, GRxBadOct, rx_bad_bytes);
FALCON_STAT(efx, GRxMissPkt, rx_missed);
FALCON_STAT(efx, GRxFalseCRS, rx_false_carrier);
FALCON_STAT(efx, GRxPausePkt, rx_pause);
FALCON_STAT(efx, GRxBadPkt, rx_bad);
FALCON_STAT(efx, GRxUcastPkt, rx_unicast);
FALCON_STAT(efx, GRxMcastPkt, rx_multicast);
FALCON_STAT(efx, GRxBcastPkt, rx_broadcast);
FALCON_STAT(efx, GRxGoodLt64Pkt, rx_good_lt64);
FALCON_STAT(efx, GRxBadLt64Pkt, rx_bad_lt64);
FALCON_STAT(efx, GRx64Pkt, rx_64);
FALCON_STAT(efx, GRx65to127Pkt, rx_65_to_127);
FALCON_STAT(efx, GRx128to255Pkt, rx_128_to_255);
FALCON_STAT(efx, GRx256to511Pkt, rx_256_to_511);
FALCON_STAT(efx, GRx512to1023Pkt, rx_512_to_1023);
FALCON_STAT(efx, GRx1024to15xxPkt, rx_1024_to_15xx);
FALCON_STAT(efx, GRx15xxtoJumboPkt, rx_15xx_to_jumbo);
FALCON_STAT(efx, GRxGtJumboPkt, rx_gtjumbo);
FALCON_STAT(efx, GRxFcsErr64to15xxPkt, rx_bad_64_to_15xx);
FALCON_STAT(efx, GRxFcsErr15xxtoJumboPkt, rx_bad_15xx_to_jumbo);
FALCON_STAT(efx, GRxFcsErrGtJumboPkt, rx_bad_gtjumbo);
FALCON_STAT(efx, GTxGoodBadOct, tx_bytes);
FALCON_STAT(efx, GTxGoodOct, tx_good_bytes);
FALCON_STAT(efx, GTxSglColPkt, tx_single_collision);
FALCON_STAT(efx, GTxMultColPkt, tx_multiple_collision);
FALCON_STAT(efx, GTxExColPkt, tx_excessive_collision);
FALCON_STAT(efx, GTxDefPkt, tx_deferred);
FALCON_STAT(efx, GTxLateCol, tx_late_collision);
FALCON_STAT(efx, GTxExDefPkt, tx_excessive_deferred);
FALCON_STAT(efx, GTxPausePkt, tx_pause);
FALCON_STAT(efx, GTxBadPkt, tx_bad);
FALCON_STAT(efx, GTxUcastPkt, tx_unicast);
FALCON_STAT(efx, GTxMcastPkt, tx_multicast);
FALCON_STAT(efx, GTxBcastPkt, tx_broadcast);
FALCON_STAT(efx, GTxLt64Pkt, tx_lt64);
FALCON_STAT(efx, GTx64Pkt, tx_64);
FALCON_STAT(efx, GTx65to127Pkt, tx_65_to_127);
FALCON_STAT(efx, GTx128to255Pkt, tx_128_to_255);
FALCON_STAT(efx, GTx256to511Pkt, tx_256_to_511);
FALCON_STAT(efx, GTx512to1023Pkt, tx_512_to_1023);
FALCON_STAT(efx, GTx1024to15xxPkt, tx_1024_to_15xx);
FALCON_STAT(efx, GTx15xxtoJumboPkt, tx_15xx_to_jumbo);
FALCON_STAT(efx, GTxGtJumboPkt, tx_gtjumbo);
FALCON_STAT(efx, GTxNonTcpUdpPkt, tx_non_tcpudp);
FALCON_STAT(efx, GTxMacSrcErrPkt, tx_mac_src_error);
FALCON_STAT(efx, GTxIpSrcErrPkt, tx_ip_src_error);
/* Pause frames are erroneously counted as errors (SFC bug 3269) */
new_rx_pause = mac_stats->rx_pause;
new_tx_pause = mac_stats->tx_pause;
mac_stats->rx_bad -= (new_rx_pause - old_rx_pause);
mac_stats->tx_bad -= (new_tx_pause - old_tx_pause);
/* Derive stats that the MAC doesn't provide directly */
mac_stats->tx_bad_bytes =
mac_stats->tx_bytes - mac_stats->tx_good_bytes;
mac_stats->tx_packets =
mac_stats->tx_lt64 + mac_stats->tx_64 +
mac_stats->tx_65_to_127 + mac_stats->tx_128_to_255 +
mac_stats->tx_256_to_511 + mac_stats->tx_512_to_1023 +
mac_stats->tx_1024_to_15xx + mac_stats->tx_15xx_to_jumbo +
mac_stats->tx_gtjumbo;
mac_stats->tx_collision =
mac_stats->tx_single_collision +
mac_stats->tx_multiple_collision +
mac_stats->tx_excessive_collision +
mac_stats->tx_late_collision;
mac_stats->rx_bytes =
mac_stats->rx_good_bytes + mac_stats->rx_bad_bytes;
mac_stats->rx_packets =
mac_stats->rx_good_lt64 + mac_stats->rx_bad_lt64 +
mac_stats->rx_64 + mac_stats->rx_65_to_127 +
mac_stats->rx_128_to_255 + mac_stats->rx_256_to_511 +
mac_stats->rx_512_to_1023 + mac_stats->rx_1024_to_15xx +
mac_stats->rx_15xx_to_jumbo + mac_stats->rx_gtjumbo;
mac_stats->rx_good = mac_stats->rx_packets - mac_stats->rx_bad;
mac_stats->rx_lt64 = mac_stats->rx_good_lt64 + mac_stats->rx_bad_lt64;
}
static bool falcon_gmac_check_fault(struct efx_nic *efx)
{
return false;
}
struct efx_mac_operations falcon_gmac_operations = {
.reconfigure = falcon_reconfigure_gmac,
.update_stats = falcon_update_stats_gmac,
.check_fault = falcon_gmac_check_fault,
};
drivers/net/sfc/mac.h
View file @ 8fbca791
......@@ -13,7 +13,6 @@
#include "net_driver.h"
extern struct efx_mac_operations falcon_gmac_operations;
extern struct efx_mac_operations falcon_xmac_operations;
extern struct efx_mac_operations efx_mcdi_mac_operations;
extern void falcon_reconfigure_xmac_core(struct efx_nic *efx);
......
drivers/net/sfc/mdio_10g.c
View file @ 8fbca791
......@@ -286,46 +286,24 @@ int efx_mdio_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
*/
void efx_mdio_an_reconfigure(struct efx_nic *efx)
{
bool xnp = (efx->link_advertising & ADVERTISED_10000baseT_Full
|| EFX_WORKAROUND_13204(efx));
int reg;
WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN));
/* Set up the base page */
reg = ADVERTISE_CSMA;
if (efx->link_advertising & ADVERTISED_10baseT_Half)
reg |= ADVERTISE_10HALF;
if (efx->link_advertising & ADVERTISED_10baseT_Full)
reg |= ADVERTISE_10FULL;
if (efx->link_advertising & ADVERTISED_100baseT_Half)
reg |= ADVERTISE_100HALF;
if (efx->link_advertising & ADVERTISED_100baseT_Full)
reg |= ADVERTISE_100FULL;
if (xnp)
reg |= ADVERTISE_RESV;
else if (efx->link_advertising & (ADVERTISED_1000baseT_Half |
ADVERTISED_1000baseT_Full))
reg |= ADVERTISE_NPAGE;
reg = ADVERTISE_CSMA | ADVERTISE_RESV;
if (efx->link_advertising & ADVERTISED_Pause)
reg |= ADVERTISE_PAUSE_CAP;
if (efx->link_advertising & ADVERTISED_Asym_Pause)
reg |= ADVERTISE_PAUSE_ASYM;
efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
/* Set up the (extended) next page if necessary */
if (efx->phy_op->set_npage_adv)
/* Set up the (extended) next page */
efx->phy_op->set_npage_adv(efx, efx->link_advertising);
/* Enable and restart AN */
reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
reg |= MDIO_AN_CTRL1_ENABLE;
if (!(EFX_WORKAROUND_15195(efx) && LOOPBACK_EXTERNAL(efx)))
reg |= MDIO_AN_CTRL1_RESTART;
if (xnp)
reg |= MDIO_AN_CTRL1_XNP;
else
reg &= ~MDIO_AN_CTRL1_XNP;
reg |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART | MDIO_AN_CTRL1_XNP;
efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
}
......
drivers/net/sfc/net_driver.h
View file @ 8fbca791
......@@ -406,8 +406,6 @@ enum efx_int_mode {
};
#define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
#define EFX_IS10G(efx) ((efx)->link_state.speed == 10000)
enum nic_state {
STATE_INIT = 0,
STATE_RUNNING = 1,
......
drivers/net/sfc/phy.h
View file @ 8fbca791
......@@ -11,17 +11,12 @@
#define EFX_PHY_H
/****************************************************************************
* 10Xpress (SFX7101 and SFT9001) PHYs
* 10Xpress (SFX7101) PHY
*/
extern struct efx_phy_operations falcon_sfx7101_phy_ops;
extern struct efx_phy_operations falcon_sft9001_phy_ops;
extern void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode);
/* Wait for the PHY to boot. Return 0 on success, -EINVAL if the PHY failed
* to boot due to corrupt flash, or some other negative error code. */
extern int sft9001_wait_boot(struct efx_nic *efx);
/****************************************************************************
* AMCC/Quake QT202x PHYs
*/
......
drivers/net/sfc/tenxpress.c
View file @ 8fbca791
This diff is collapsed.
drivers/net/sfc/workarounds.h
View file @ 8fbca791
......@@ -19,9 +19,7 @@
#define EFX_WORKAROUND_FALCON_A(efx) (efx_nic_rev(efx) <= EFX_REV_FALCON_A1)
#define EFX_WORKAROUND_FALCON_AB(efx) (efx_nic_rev(efx) <= EFX_REV_FALCON_B0)
#define EFX_WORKAROUND_SIENA(efx) (efx_nic_rev(efx) == EFX_REV_SIENA_A0)
#define EFX_WORKAROUND_10G(efx) EFX_IS10G(efx)
#define EFX_WORKAROUND_SFT9001(efx) ((efx)->phy_type == PHY_TYPE_SFT9001A || \
(efx)->phy_type == PHY_TYPE_SFT9001B)
#define EFX_WORKAROUND_10G(efx) 1
/* XAUI resets if link not detected */
#define EFX_WORKAROUND_5147 EFX_WORKAROUND_ALWAYS
......@@ -58,9 +56,4 @@
/* Leak overlength packets rather than free */
#define EFX_WORKAROUND_8071 EFX_WORKAROUND_FALCON_A
/* Need to send XNP pages for 100BaseT */
#define EFX_WORKAROUND_13204 EFX_WORKAROUND_SFT9001
/* Don't restart AN in near-side loopback */
#define EFX_WORKAROUND_15195 EFX_WORKAROUND_SFT9001
#endif /* EFX_WORKAROUNDS_H */
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