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Commit 9136e1f1 authored by Paul Greenwalt's avatar Paul Greenwalt Committed by Tony Nguyen
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ice: refactor PHY type to ethtool link mode 

Refactor ice_phy_type_to_ethtool to use phy_type_[low|high]_lkup table to
map PHY type to AQ link speed and ethtool link mode. This removes
complexity and simplifies future changes.
Signed-off-by: default avatarPaul Greenwalt <paul.greenwalt@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 578fb092
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Showing with 141 additions and 274 deletions
drivers/net/ethernet/intel/ice/ice.h
View file @ 9136e1f1
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#include <linux/pkt_sched.h> #include <linux/pkt_sched.h>
#include <linux/if_bridge.h> #include <linux/if_bridge.h>
#include <linux/ctype.h> #include <linux/ctype.h>
#include <linux/linkmode.h>
#include <linux/bpf.h> #include <linux/bpf.h>
#include <linux/btf.h> #include <linux/btf.h>
#include <linux/auxiliary_bus.h> #include <linux/auxiliary_bus.h>
......
drivers/net/ethernet/intel/ice/ice_ethtool.c
View file @ 9136e1f1
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
/* ethtool support for ice */ /* ethtool support for ice */
#include "ice.h" #include "ice.h"
#include "ice_ethtool.h"
#include "ice_flow.h" #include "ice_flow.h"
#include "ice_fltr.h" #include "ice_fltr.h"
#include "ice_lib.h" #include "ice_lib.h"
...@@ -1658,15 +1659,26 @@ ice_mask_min_supported_speeds(struct ice_hw *hw, ...@@ -1658,15 +1659,26 @@ ice_mask_min_supported_speeds(struct ice_hw *hw,
*phy_types_low &= ~ICE_PHY_TYPE_LOW_MASK_MIN_1G; *phy_types_low &= ~ICE_PHY_TYPE_LOW_MASK_MIN_1G;
} }
#define ice_ethtool_advertise_link_mode(aq_link_speed, ethtool_link_mode) \ /**
do { \ * ice_linkmode_set_bit - set link mode bit
if (req_speeds & (aq_link_speed) || \ * @phy_to_ethtool: PHY type to ethtool link mode struct to set
(!req_speeds && \ * @ks: ethtool link ksettings struct to fill out
(advert_phy_type_lo & phy_type_mask_lo || \ * @req_speeds: speed requested by user
advert_phy_type_hi & phy_type_mask_hi))) \ * @advert_phy_type: advertised PHY type
ethtool_link_ksettings_add_link_mode(ks, advertising,\ * @phy_type: PHY type
ethtool_link_mode); \ */
} while (0) static void
ice_linkmode_set_bit(const struct ice_phy_type_to_ethtool *phy_to_ethtool,
struct ethtool_link_ksettings *ks, u32 req_speeds,
u64 advert_phy_type, u32 phy_type)
{
linkmode_set_bit(phy_to_ethtool->link_mode, ks->link_modes.supported);
if (req_speeds & phy_to_ethtool->aq_link_speed ||
(!req_speeds && advert_phy_type & BIT(phy_type)))
linkmode_set_bit(phy_to_ethtool->link_mode,
ks->link_modes.advertising);
}
/** /**
* ice_phy_type_to_ethtool - convert the phy_types to ethtool link modes * ice_phy_type_to_ethtool - convert the phy_types to ethtool link modes
...@@ -1682,11 +1694,10 @@ ice_phy_type_to_ethtool(struct net_device *netdev, ...@@ -1682,11 +1694,10 @@ ice_phy_type_to_ethtool(struct net_device *netdev,
struct ice_pf *pf = vsi->back; struct ice_pf *pf = vsi->back;
u64 advert_phy_type_lo = 0; u64 advert_phy_type_lo = 0;
u64 advert_phy_type_hi = 0; u64 advert_phy_type_hi = 0;
u64 phy_type_mask_lo = 0;
u64 phy_type_mask_hi = 0;
u64 phy_types_high = 0; u64 phy_types_high = 0;
u64 phy_types_low = 0; u64 phy_types_low = 0;
u16 req_speeds; u32 req_speeds;
u32 i;
req_speeds = vsi->port_info->phy.link_info.req_speeds; req_speeds = vsi->port_info->phy.link_info.req_speeds;
...@@ -1743,272 +1754,22 @@ ice_phy_type_to_ethtool(struct net_device *netdev, ...@@ -1743,272 +1754,22 @@ ice_phy_type_to_ethtool(struct net_device *netdev,
advert_phy_type_hi = vsi->port_info->phy.phy_type_high; advert_phy_type_hi = vsi->port_info->phy.phy_type_high;
} }
ethtool_link_ksettings_zero_link_mode(ks, supported); linkmode_zero(ks->link_modes.supported);
ethtool_link_ksettings_zero_link_mode(ks, advertising); linkmode_zero(ks->link_modes.advertising);
phy_type_mask_lo = ICE_PHY_TYPE_LOW_100BASE_TX |
ICE_PHY_TYPE_LOW_100M_SGMII;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100baseT_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100MB,
100baseT_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_1000BASE_T |
ICE_PHY_TYPE_LOW_1G_SGMII;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
1000baseT_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_1000MB,
1000baseT_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_1000BASE_KX;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
1000baseKX_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_1000MB,
1000baseKX_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_1000BASE_SX |
ICE_PHY_TYPE_LOW_1000BASE_LX;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
1000baseX_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_1000MB,
1000baseX_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_2500BASE_T;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
2500baseT_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_2500MB,
2500baseT_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_2500BASE_X |
ICE_PHY_TYPE_LOW_2500BASE_KX;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
2500baseX_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_2500MB,
2500baseX_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_5GBASE_T |
ICE_PHY_TYPE_LOW_5GBASE_KR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
5000baseT_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_5GB,
5000baseT_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_T |
ICE_PHY_TYPE_LOW_10G_SFI_DA |
ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC |
ICE_PHY_TYPE_LOW_10G_SFI_C2C;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
10000baseT_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,
10000baseT_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_KR_CR1;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
10000baseKR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,
10000baseKR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_SR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
10000baseSR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,
10000baseSR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_10GBASE_LR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
10000baseLR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_10GB,
10000baseLR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_25GBASE_T |
ICE_PHY_TYPE_LOW_25GBASE_CR |
ICE_PHY_TYPE_LOW_25GBASE_CR_S |
ICE_PHY_TYPE_LOW_25GBASE_CR1 |
ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC |
ICE_PHY_TYPE_LOW_25G_AUI_C2C;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
25000baseCR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_25GB,
25000baseCR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_25GBASE_SR |
ICE_PHY_TYPE_LOW_25GBASE_LR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
25000baseSR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_25GB,
25000baseSR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_25GBASE_KR |
ICE_PHY_TYPE_LOW_25GBASE_KR_S |
ICE_PHY_TYPE_LOW_25GBASE_KR1;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
25000baseKR_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_25GB,
25000baseKR_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_KR4;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
40000baseKR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,
40000baseKR4_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_CR4 |
ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC |
ICE_PHY_TYPE_LOW_40G_XLAUI;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
40000baseCR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,
40000baseCR4_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_SR4;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
40000baseSR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,
40000baseSR4_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_40GBASE_LR4;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
40000baseLR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_40GB,
40000baseLR4_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_50GBASE_CR2 |
ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC |
ICE_PHY_TYPE_LOW_50G_LAUI2 |
ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC |
ICE_PHY_TYPE_LOW_50G_AUI2 |
ICE_PHY_TYPE_LOW_50GBASE_CP |
ICE_PHY_TYPE_LOW_50GBASE_SR |
ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC |
ICE_PHY_TYPE_LOW_50G_AUI1;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
50000baseCR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_50GB,
50000baseCR2_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_50GBASE_KR2 |
ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
50000baseKR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_50GB,
50000baseKR2_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_50GBASE_SR2 |
ICE_PHY_TYPE_LOW_50GBASE_LR2 |
ICE_PHY_TYPE_LOW_50GBASE_FR |
ICE_PHY_TYPE_LOW_50GBASE_LR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
50000baseSR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_50GB,
50000baseSR2_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_100GBASE_CR4 |
ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC |
ICE_PHY_TYPE_LOW_100G_CAUI4 |
ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC |
ICE_PHY_TYPE_LOW_100G_AUI4 |
ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4;
phy_type_mask_hi = ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC |
ICE_PHY_TYPE_HIGH_100G_CAUI2 |
ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC |
ICE_PHY_TYPE_HIGH_100G_AUI2;
if (phy_types_low & phy_type_mask_lo ||
phy_types_high & phy_type_mask_hi) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseCR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseCR4_Full);
}
if (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_CP2) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseCR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseCR2_Full);
}
if (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_SR4) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseSR4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseSR4_Full);
}
if (phy_types_low & ICE_PHY_TYPE_LOW_100GBASE_SR2) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseSR2_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseSR2_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_100GBASE_LR4 |
ICE_PHY_TYPE_LOW_100GBASE_DR;
if (phy_types_low & phy_type_mask_lo) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100000baseLR4_ER4_Full);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseLR4_ER4_Full);
}
phy_type_mask_lo = ICE_PHY_TYPE_LOW_100GBASE_KR4 | for (i = 0; i < BITS_PER_TYPE(u64); i++) {
ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4; if (phy_types_low & BIT_ULL(i))
if (phy_types_low & phy_type_mask_lo) { ice_linkmode_set_bit(&phy_type_low_lkup[i], ks,
ethtool_link_ksettings_add_link_mode(ks, supported, req_speeds, advert_phy_type_lo,
100000baseKR4_Full); i);
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB,
100000baseKR4_Full);
} }
if (phy_types_high & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) { for (i = 0; i < BITS_PER_TYPE(u64); i++) {
ethtool_link_ksettings_add_link_mode(ks, supported, if (phy_types_high & BIT_ULL(i))
100000baseKR2_Full); ice_linkmode_set_bit(&phy_type_high_lkup[i], ks,
ice_ethtool_advertise_link_mode(ICE_AQ_LINK_SPEED_100GB, req_speeds, advert_phy_type_hi,
100000baseKR2_Full); i);
} }
} }
#define TEST_SET_BITS_TIMEOUT 50 #define TEST_SET_BITS_TIMEOUT 50
......
drivers/net/ethernet/intel/ice/ice_ethtool.h 0 → 100644
View file @ 9136e1f1
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (C) 2023 Intel Corporation */
#ifndef _ICE_ETHTOOL_H_
#define _ICE_ETHTOOL_H_
struct ice_phy_type_to_ethtool {
u64 aq_link_speed;
u8 link_mode;
};
/* Macro to make PHY type to Ethtool link mode table entry.
* The index is the PHY type.
*/
#define ICE_PHY_TYPE(LINK_SPEED, ETHTOOL_LINK_MODE) {\
.aq_link_speed = ICE_AQ_LINK_SPEED_##LINK_SPEED, \
.link_mode = ETHTOOL_LINK_MODE_##ETHTOOL_LINK_MODE##_BIT, \
}
/* Lookup table mapping PHY type low to link speed and Ethtool link modes.
* Array index corresponds to HW PHY type bit, see
* ice_adminq_cmd.h:ICE_PHY_TYPE_LOW_*.
*/
static const struct ice_phy_type_to_ethtool
phy_type_low_lkup[] = {
[0] = ICE_PHY_TYPE(100MB, 100baseT_Full),
[1] = ICE_PHY_TYPE(100MB, 100baseT_Full),
[2] = ICE_PHY_TYPE(1000MB, 1000baseT_Full),
[3] = ICE_PHY_TYPE(1000MB, 1000baseX_Full),
[4] = ICE_PHY_TYPE(1000MB, 1000baseX_Full),
[5] = ICE_PHY_TYPE(1000MB, 1000baseKX_Full),
[6] = ICE_PHY_TYPE(1000MB, 1000baseT_Full),
[7] = ICE_PHY_TYPE(2500MB, 2500baseT_Full),
[8] = ICE_PHY_TYPE(2500MB, 2500baseX_Full),
[9] = ICE_PHY_TYPE(2500MB, 2500baseX_Full),
[10] = ICE_PHY_TYPE(5GB, 5000baseT_Full),
[11] = ICE_PHY_TYPE(5GB, 5000baseT_Full),
[12] = ICE_PHY_TYPE(10GB, 10000baseT_Full),
[13] = ICE_PHY_TYPE(10GB, 10000baseT_Full),
[14] = ICE_PHY_TYPE(10GB, 10000baseSR_Full),
[15] = ICE_PHY_TYPE(10GB, 10000baseLR_Full),
[16] = ICE_PHY_TYPE(10GB, 10000baseKR_Full),
[17] = ICE_PHY_TYPE(10GB, 10000baseT_Full),
[18] = ICE_PHY_TYPE(10GB, 10000baseKR_Full),
[19] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
[20] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
[21] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
[22] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
[23] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
[24] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
[25] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
[26] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
[27] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
[28] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
[29] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
[30] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
[31] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
[32] = ICE_PHY_TYPE(40GB, 40000baseLR4_Full),
[33] = ICE_PHY_TYPE(40GB, 40000baseKR4_Full),
[34] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
[35] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
[36] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[37] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
[38] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
[39] = ICE_PHY_TYPE(50GB, 50000baseKR2_Full),
[40] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[41] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[42] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[43] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[44] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[45] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[46] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
[47] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
[48] = ICE_PHY_TYPE(50GB, 50000baseKR2_Full),
[49] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[50] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
[51] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[52] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full),
[53] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full),
[54] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full),
[55] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[56] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[57] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[58] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[59] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[60] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full),
[61] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
[62] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
[63] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full),
};
/* Lookup table mapping PHY type high to link speed and Ethtool link modes.
* Array index corresponds to HW PHY type bit, see
* ice_adminq_cmd.h:ICE_PHY_TYPE_HIGH_*
*/
static const struct ice_phy_type_to_ethtool
phy_type_high_lkup[] = {
[0] = ICE_PHY_TYPE(100GB, 100000baseKR2_Full),
[1] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[2] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[3] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
[4] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
};
#endif /* !_ICE_ETHTOOL_H_ */
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