Commit 919eb475 authored by Mika Westerberg's avatar Mika Westerberg Committed by Linus Walleij

pinctrl: intel: Add support for variable size pad groups

The Intel GPIO hardware has a concept of pad groups, which means 1 to 32
pads occupying their own GPI_IS, GPI_IE, PAD_OWN and so on registers. The
existing hardware has the same amount of pads in each pad group (except the
last one) so it is possible to use community->gpp_size to calculate start
offset of each register.

With the next generation SoCs the pad group size is not always the same
anymore which means we cannot use community->gpp_size for register offset
calculations directly.

To support variable size pad groups we introduce struct intel_padgroup that
can be filled in by the client drivers according the hardware pad group
layout. The core driver will always use these when it performs calculations
for pad register offsets. The core driver will automatically populate pad
groups based on community->gpp_size if the driver does not provide any.
This makes sure the existing drivers still work as expected.
Signed-off-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarChuah, Kim Tatt <kim.tatt.chuah@intel.com>
Signed-off-by: default avatarTan Jui Nee <jui.nee.tan@intel.com>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 41633edf
This diff is collapsed.
...@@ -43,6 +43,23 @@ struct intel_function { ...@@ -43,6 +43,23 @@ struct intel_function {
size_t ngroups; size_t ngroups;
}; };
/**
* struct intel_padgroup - Hardware pad group information
* @reg_num: GPI_IS register number
* @base: Starting pin of this group
* @size: Size of this group (maximum is 32).
* @padown_num: PAD_OWN register number (assigned by the core driver)
*
* If pad groups of a community are not the same size, use this structure
* to specify them.
*/
struct intel_padgroup {
unsigned reg_num;
unsigned base;
unsigned size;
unsigned padown_num;
};
/** /**
* struct intel_community - Intel pin community description * struct intel_community - Intel pin community description
* @barno: MMIO BAR number where registers for this community reside * @barno: MMIO BAR number where registers for this community reside
...@@ -56,13 +73,22 @@ struct intel_function { ...@@ -56,13 +73,22 @@ struct intel_function {
* @ie_offset: Register offset of GPI_IE from @regs. * @ie_offset: Register offset of GPI_IE from @regs.
* @pin_base: Starting pin of pins in this community * @pin_base: Starting pin of pins in this community
* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
* HOSTSW_OWN, GPI_IS, GPI_IE, etc. * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL.
* @gpp_num_padown_regs: Number of pad registers each pad group consumes at
* minimum. Use %0 if the number of registers can be
* determined by the size of the group.
* @npins: Number of pins in this community * @npins: Number of pins in this community
* @features: Additional features supported by the hardware * @features: Additional features supported by the hardware
* @gpps: Pad groups if the controller has variable size pad groups
* @ngpps: Number of pad groups in this community
* @regs: Community specific common registers (reserved for core driver) * @regs: Community specific common registers (reserved for core driver)
* @pad_regs: Community specific pad registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver)
* @ngpps: Number of groups (hw groups) in this community (reserved for *
* core driver) * Most Intel GPIO host controllers this driver supports each pad group is
* of equal size (except the last one). In that case the driver can just
* fill in @gpp_size field and let the core driver to handle the rest. If
* the controller has pad groups of variable size the client driver can
* pass custom @gpps and @ngpps instead.
*/ */
struct intel_community { struct intel_community {
unsigned barno; unsigned barno;
...@@ -72,11 +98,14 @@ struct intel_community { ...@@ -72,11 +98,14 @@ struct intel_community {
unsigned ie_offset; unsigned ie_offset;
unsigned pin_base; unsigned pin_base;
unsigned gpp_size; unsigned gpp_size;
unsigned gpp_num_padown_regs;
size_t npins; size_t npins;
unsigned features; unsigned features;
const struct intel_padgroup *gpps;
size_t ngpps;
/* Reserved for the core driver */
void __iomem *regs; void __iomem *regs;
void __iomem *pad_regs; void __iomem *pad_regs;
size_t ngpps;
}; };
/* Additional features supported by the hardware */ /* Additional features supported by the hardware */
......
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
.hostown_offset = SPT_HOSTSW_OWN, \ .hostown_offset = SPT_HOSTSW_OWN, \
.ie_offset = SPT_GPI_IE, \ .ie_offset = SPT_GPI_IE, \
.gpp_size = 24, \ .gpp_size = 24, \
.gpp_num_padown_regs = 4, \
.pin_base = (s), \ .pin_base = (s), \
.npins = ((e) - (s) + 1), \ .npins = ((e) - (s) + 1), \
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment