Commit 93404fc8 authored by qiuguorui1's avatar qiuguorui1 Committed by Greg Kroah-Hartman

irqchip/stm32-exti: Avoid losing interrupts due to clearing pending bits by mistake

commit e579076a upstream.

In the current code, when the eoi callback of the exti clears the pending
bit of the current interrupt, it will first read the values of fpr and
rpr, then logically OR the corresponding bit of the interrupt number,
and finally write back to fpr and rpr.

We found through experiments that if two exti interrupts,
we call them int1/int2, arrive almost at the same time. in our scenario,
the time difference is 30 microseconds, assuming int1 is triggered first.

there will be an extreme scenario: both int's pending bit are set to 1,
the irq handle of int1 is executed first, and eoi handle is then executed,
at this moment, all pending bits are cleared, but the int 2 has not
finally been reported to the cpu yet, which eventually lost int2.

According to stm32's TRM description about rpr and fpr: Writing a 1 to this
bit will trigger a rising edge event on event x, Writing 0 has no
effect.

Therefore, when clearing the pending bit, we only need to clear the
pending bit of the irq.

Fixes: 927abfc4 ("irqchip/stm32: Add stm32mp1 support with hierarchy domain")
Signed-off-by: default avatarqiuguorui1 <qiuguorui1@huawei.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org # v4.18+
Link: https://lore.kernel.org/r/20200820031629.15582-1-qiuguorui1@huawei.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent d9eeca1e
...@@ -382,6 +382,16 @@ static void stm32_irq_ack(struct irq_data *d) ...@@ -382,6 +382,16 @@ static void stm32_irq_ack(struct irq_data *d)
irq_gc_unlock(gc); irq_gc_unlock(gc);
} }
/* directly set the target bit without reading first. */
static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
{
struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
void __iomem *base = chip_data->host_data->base;
u32 val = BIT(d->hwirq % IRQS_PER_BANK);
writel_relaxed(val, base + reg);
}
static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
{ {
struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
...@@ -415,9 +425,9 @@ static void stm32_exti_h_eoi(struct irq_data *d) ...@@ -415,9 +425,9 @@ static void stm32_exti_h_eoi(struct irq_data *d)
raw_spin_lock(&chip_data->rlock); raw_spin_lock(&chip_data->rlock);
stm32_exti_set_bit(d, stm32_bank->rpr_ofst); stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
if (stm32_bank->fpr_ofst != UNDEF_REG) if (stm32_bank->fpr_ofst != UNDEF_REG)
stm32_exti_set_bit(d, stm32_bank->fpr_ofst); stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
raw_spin_unlock(&chip_data->rlock); raw_spin_unlock(&chip_data->rlock);
......
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