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Commit 938a0447 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Greg Kroah-Hartman
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staging: r8822be: Add code for halmac sub-driver 

The RTL8822BE, an 802.11ac wireless network card, is now appearing in
new computers. Its driver is being placed in staging to reduce the time
that users of this new card will have access to in-kernel drivers.

New Realtek devices implement a common sub-driver to control the MAC
layer. The RTL8822BE is the first of these devices, thus its introduction
involves some extra code. In the wireless tree, this will be a separate
module; however, it is compiled into the 8822be driver here.
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Cc: Yan-Hsuan Chuang <yhchuang@realtek.com>
Cc: Birming Chiu <birming@realtek.com>
Cc: Shaofu <shaofu@realtek.com>
Cc: Steven Ting <steventing@realtek.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b53b764b
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drivers/staging/rtlwifi/halmac/halmac_2_platform.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_2_PLATFORM_H_
#define _HALMAC_2_PLATFORM_H_
#include "../wifi.h"
#include <asm/byteorder.h>
#define HALMAC_PLATFORM_LITTLE_ENDIAN 1
#define HALMAC_PLATFORM_BIG_ENDIAN 0
/* Note : Named HALMAC_PLATFORM_LITTLE_ENDIAN / HALMAC_PLATFORM_BIG_ENDIAN
* is not mandatory. But Little endian must be '1'. Big endian must be '0'
*/
#if defined(__LITTLE_ENDIAN)
#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_LITTLE_ENDIAN
#elif defined(__BIG_ENDIAN)
#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_BIG_ENDIAN
#else
#error
#endif
/* define the Platform SDIO Bus CLK */
#define PLATFORM_SD_CLK 50000000 /*50MHz*/
/* define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */
/* Should be 8 Byte alignment */
#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 16 /*Bytes*/
#endif /* _HALMAC_2_PLATFORM_H_ */
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_8822B_CFG_H_
#define _HALMAC_8822B_CFG_H_
#include "halmac_8822b_pwr_seq.h"
#include "halmac_api_8822b.h"
#include "halmac_api_8822b_usb.h"
#include "halmac_api_8822b_sdio.h"
#include "halmac_api_8822b_pcie.h"
#include "../../halmac_bit2.h"
#include "../../halmac_reg2.h"
#include "../../halmac_api.h"
#define HALMAC_TX_FIFO_SIZE_8822B 262144 /* 256k */
#define HALMAC_TX_FIFO_SIZE_LA_8822B 131072 /* 128k */
#define HALMAC_RX_FIFO_SIZE_8822B 24576 /* 24k */
#define HALMAC_TX_PAGE_SIZE_8822B 128 /* PageSize 128Byte */
#define HALMAC_TX_ALIGN_SIZE_8822B 8
#define HALMAC_TX_PAGE_SIZE_2_POWER_8822B 7 /* 128 = 2^7 */
#define HALMAC_SECURITY_CAM_ENTRY_NUM_8822B 64 /* CAM Entry size */
#define HALMAC_TX_AGG_ALIGNMENT_SIZE_8822B 8
#define HALMAC_TX_DESC_SIZE_8822B 48
#define HALMAC_RX_DESC_SIZE_8822B 24
#define HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B 120
#define HALMAC_C2H_PKT_BUF_8822B 256
#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B 80 /* align 8 Byte*/
#define HALMAC_RX_FIFO_EXPANDING_UNIT_8822B \
(HALMAC_RX_DESC_SIZE_8822B + HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B + \
HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE) /* align 8 Byte*/
#define HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8822B \
(HALMAC_RX_DESC_SIZE_8822B + HALMAC_RX_DESC_DUMMY_SIZE_MAX_8822B + \
HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B) /* align 8 Byte*/
#define HALMAC_TX_FIFO_SIZE_EX_1_BLK_8822B 196608 /* 192k */
#define HALMAC_RX_FIFO_SIZE_EX_1_BLK_8822B \
((((HALMAC_RX_FIFO_EXPANDING_UNIT_8822B << 8) - 1) >> 10) \
<< 10) /* < 56k*/
#define HALMAC_RX_FIFO_SIZE_EX_1_BLK_MAX_8822B \
((((HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8822B << 8) - 1) >> 10) \
<< 10) /* 55k*/
#define HALMAC_TX_FIFO_SIZE_EX_2_BLK_8822B 131072 /* 128k */
#define HALMAC_RX_FIFO_SIZE_EX_2_BLK_8822B 155648 /* 152k */
#define HALMAC_TX_FIFO_SIZE_EX_3_BLK_8822B 65536 /* 64k */
#define HALMAC_RX_FIFO_SIZE_EX_3_BLK_8822B 221184 /* 216k */
/* TXFIFO LAYOUT
* HIGH_QUEUE
* NORMAL_QUEUE
* LOW_QUEUE
* EXTRA_QUEUE
* PUBLIC_QUEUE -- decided after all other queue are defined
* GAP_QUEUE -- Used to separate AC queue and Rsvd page
*
* RSVD_DRIVER -- Driver used rsvd page area
* RSVD_H2C_EXTRAINFO -- Extra Information for h2c
* RSVD_H2C_QUEUE -- h2c queue in rsvd page
* RSVD_CPU_INSTRUCTION -- extend fw code
* RSVD_FW_TXBUFF -- fw used this area to send packet
*
* Symbol: HALMAC_MODE_QUEUE_UNIT_CHIP, ex: HALMAC_LB_2BULKOUT_FWCMD_PGNUM_8822B
*/
#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_8822B \
16384 /*16K, only used in init case*/
#define HALMAC_RSVD_DRV_PGNUM_8822B 16 /*2048*/
#define HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B 32 /*4096*/
#define HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B 8 /*1024*/
#define HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B 0 /*0*/
#define HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B 4 /*512*/
#define HALMAC_EFUSE_SIZE_8822B 1024 /* 0x400 */
#define HALMAC_BT_EFUSE_SIZE_8822B 128 /* 0x80 */
#define HALMAC_EEPROM_SIZE_8822B 0x300
#define HALMAC_CR_TRX_ENABLE_8822B \
(BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | BIT_RXDMA_EN | \
BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | BIT_MACTXEN | BIT_MACRXEN)
#define HALMAC_BLK_DESC_NUM_8822B 0x3 /* Only for USB */
/* AMPDU max time (unit : 32us) */
#define HALMAC_AMPDU_MAX_TIME_8822B 0x70
/* Protect mode control */
#define HALMAC_PROT_RTS_LEN_TH_8822B 0xFF
#define HALMAC_PROT_RTS_TX_TIME_TH_8822B 0x08
#define HALMAC_PROT_MAX_AGG_PKT_LIMIT_8822B 0x20
#define HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8822B 0x20
/* Fast EDCA setting */
#define HALMAC_FAST_EDCA_VO_TH_8822B 0x06
#define HALMAC_FAST_EDCA_VI_TH_8822B 0x06
#define HALMAC_FAST_EDCA_BE_TH_8822B 0x06
#define HALMAC_FAST_EDCA_BK_TH_8822B 0x06
/* BAR setting */
#define HALMAC_BAR_RETRY_LIMIT_8822B 0x01
#define HALMAC_RA_TRY_RATE_AGG_LIMIT_8822B 0x08
enum halmac_normal_rxagg_th_to_8822b {
HALMAC_NORMAL_RXAGG_THRESHOLD_8822B = 0xFF,
HALMAC_NORMAL_RXAGG_TIMEOUT_8822B = 0x01,
};
enum halmac_loopback_rxagg_th_to_8822b {
HALMAC_LOOPBACK_RXAGG_THRESHOLD_8822B = 0xFF,
HALMAC_LOOPBACK_RXAGG_TIMEOUT_8822B = 0x01,
};
#endif
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_8822b_phy.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halmac_88xx_cfg.h"
#include "halmac_8822b_cfg.h"
/**
* ============ip sel item list============
* HALMAC_IP_SEL_INTF_PHY
* USB2 : usb2 phy, 1byte value
* USB3 : usb3 phy, 2byte value
* PCIE1 : pcie gen1 mdio, 2byte value
* PCIE2 : pcie gen2 mdio, 2byte value
* HALMAC_IP_SEL_MAC
* USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value
* HALMAC_IP_SEL_PCIE_DBI
* USB2 USB3 : none
* PCIE1, PCIE2 : pcie dbi, 1byte value
*/
struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB2_PHY[] = {
/* {offset, value, ip sel, cut mask, platform mask} */
{0xFFFF, 0x00, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
};
struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB3_PHY[] = {
/* {offset, value, ip sel, cut mask, platform mask} */
{0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_D,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
};
struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN1[] = {
/* {offset, value, ip sel, cut mask, platform mask} */
{0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0008, 0x3596, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x002A, 0x1840, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
};
struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN2[] = {
/* {offset, value, ip sel, cut mask, platform mask} */
{0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0008, 0x3597, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0x002A, 0x3040, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C,
HALMAC_INTF_PHY_PLATFORM_ALL},
{0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL,
HALMAC_INTF_PHY_PLATFORM_ALL},
};
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halmac_88xx_cfg.h"
#include "halmac_8822b_cfg.h"
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*SWR OCP = SWR OCP = 010 1382.40*/
{0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /*SWR OCP = 010 1382.40 */
{0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0),
BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/
{0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1,
HALMAC_PWRSEQ_DELAY_MS}, /*Delay 1ms*/
{0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5),
0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
(BIT(4) | BIT(3) | BIT(2)),
0}, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/
{0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* Disable USB suspend */
{0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(1),
BIT(1)}, /* wait till 0x04[17] = 1 power ready*/
{0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), 0}, /* Enable USB suspend */
{0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0}, /*0xFF1A = 0 to release resume signals*/
{0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(7), 0}, /* disable HWPDN 0x04[15]=0*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
(BIT(4) | BIT(3)), 0}, /* disable WL suspend*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* polling until return 0*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(0), 0},
{0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3), BIT(3)}, /*Enable XTAL_CLK*/
{0x10A8, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0}, /*NFC pad enabled*/
{0x10A9, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xef}, /*NFC pad enabled*/
{0x10AA, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x0c}, /*NFC pad enabled*/
{0x0068, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO pad power down disabled*/
{0x0029, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xF9}, /*PLL seting*/
{0x0024, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(2), 0}, /*Improve TX EVM of CH13 and some 5G channles */
{0x0074, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(5), BIT(5)}, /*PCIE WAKE# enabled*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0003, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*0x02[10] = 0 Disable MCU Core*/
{0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3), 0}, /*LPS option 0x93[3]=0 , SWR PFM*/
{0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/
{0x00EF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0}, /*0xEF[7:0] = 0 turn off RF*/
{0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x30}, /*0xFF1A = 0x30 to block resume signals*/
{0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*Enable rising edge triggering interrupt*/
{0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /* Whole BB is reset */
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(1),
0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
{0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3), 0}, /* XTAL_CLK gated*/
{0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5),
BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(4) | BIT(3),
(BIT(4) | BIT(3))}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4),
BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/
{0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, 0xFF,
0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3) | BIT(4),
BIT(3) | BIT(4)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(0),
BIT(0)}, /*Set SDIO suspend local register*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_POLLING, BIT(1),
BIT(1)}, /*wait power state to suspend*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(7),
BIT(7)}, /*suspend enable and power down enable*/
{0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF,
0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/
{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(5), 0}, /*0x67[5]=0 , BIT_PAPE_WLBT_SEL*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4),
BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/
{0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(5),
0}, /* 0: BT PAPE control ; 1: WL BB LNAON control*/
{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(4),
0}, /* 0: BT GPIO[11:10] control ; 1: WL BB LNAON control*/
{0x004F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /* 0: BT Control*/
{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(1),
0}, /* turn off BT_3DD_SYNC_B and BT_GPIO[18] */
{0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6)}, /* GPIO[6] : Output mode*/
{0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /* turn off BT_GPIO[16] */
{0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /* GPIO[7] : Output mode*/
{0x0062, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* GPIO[12] : Output mode */
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(0),
BIT(0)}, /*Set SDIO suspend local register*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK,
HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1),
0}, /*0x90[1]=0 , disable 32k clock*/
{0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, 0xFF,
0}, /*0x90[1]=0 , disable 32k clock by indirect access*/
{0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, 0xFF,
0x90}, /*0x90[1]=0 , disable 32k clock by indirect access*/
{0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, 0xFF,
0x00}, /*0x90[1]=0 , disable 32k clock by indirect access*/
{0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, 0xFF,
0x04}, /*0x90[1]=0 , disable 32k clock by indirect access*/
{0x0081, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(7), 0}, /*0x80[15]clean fw init ready bit*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/
{0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_POLLING, BIT(1),
BIT(1)}, /*wait power state to suspend*/
{0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
{0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3) | BIT(4) | BIT(7),
0}, /*clear suspend enable and power down enable*/
{0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0},
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_LPS[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/
{0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3), BIT(3)}, /*Register write data of 32K calibration*/
{0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/
{0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/
{0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* enable 32K CLK*/
{0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x42}, /* LPS Option MAC OFF enable*/
{0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), BIT(1)}, /* enable reg use 32K CLK*/
{0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*PCIe DMA stop*/
{0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*Tx Pause*/
{0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*Whole BB is reset*/
{0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x3F}, /*Reset MAC TRX*/
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*check if removed later*/
{0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/
{0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(4), BIT(4)}, /* switch TSF clock to 32K*/
{0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(7),
BIT(7)}, /*Polling 0x109[7]=0 TSF in 40M*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* enable WL_LPS_EN*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/
{0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(3), BIT(3)}, /*Register write data of 32K calibration*/
{0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/
{0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/
{0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* enable 32K CLK*/
{0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x40}, /* LPS Option MAC OFF enable*/
{0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), BIT(1)}, /* enable reg use 32K CLK*/
{0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*PCIe DMA stop*/
{0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*Tx Pause*/
{0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, 0xFF,
0}, /*Should be zero if no packet is transmitting*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*Whole BB is reset*/
{0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x3F}, /*Reset MAC TRX*/
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /*check if removed later*/
{0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/
{0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(4), BIT(4)}, /* switch TSF clock to 32K*/
{0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(7),
BIT(7)}, /*Polling 0x109[7]=1 TSF in 32K*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(0), BIT(0)}, /* enable WL_LPS_EN*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_LPS_TO_ACT[] = {
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
{0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*SDIO RPWM*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/
{0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /*SDIO RPWM*/
{0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x84}, /*USB RPWM*/
{0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x84}, /*PCIe RPWM*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/
{0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(4), 0}, /* switch TSF to 40M*/
{0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
HALMAC_PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), BIT(1)},
{0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*nable WMAC TRX*/
{0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1) | BIT(0), BIT(1) | BIT(0)}, /*nable BB macro*/
{0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0},
{0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0x03}, /*clear RPWM INT*/
{0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*clear FW INT*/
{0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*clear FW INT*/
{0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*clear FW INT*/
{0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
0xFF, 0xFF}, /*clear FW INT*/
{0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(1), 0}, /* disable reg use 32K CLK*/
{0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
BIT(2), 0}, /*disable 32k calibration and thermal meter*/
{0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
};
/* Card Enable Array */
struct halmac_wl_pwr_cfg_ *halmac_8822b_card_enable_flow[] = {
HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU,
HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, NULL};
/* Card Disable Array */
struct halmac_wl_pwr_cfg_ *halmac_8822b_card_disable_flow[] = {
HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU,
HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS, NULL};
/* Suspend Array */
struct halmac_wl_pwr_cfg_ *halmac_8822b_suspend_flow[] = {
HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU,
HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS, NULL};
/* Resume Array */
struct halmac_wl_pwr_cfg_ *halmac_8822b_resume_flow[] = {
HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU,
HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, NULL};
/* HWPDN Array - HW behavior */
struct halmac_wl_pwr_cfg_ *halmac_8822b_hwpdn_flow[] = {NULL};
/* Enter LPS - FW behavior */
struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_lps_flow[] = {
HALMAC_RTL8822B_TRANS_ACT_TO_LPS, NULL};
/* Enter Deep LPS - FW behavior */
struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_deep_lps_flow[] = {
HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS, NULL};
/* Leave LPS -FW behavior */
struct halmac_wl_pwr_cfg_ *halmac_8822b_leave_lps_flow[] = {
HALMAC_RTL8822B_TRANS_LPS_TO_ACT, NULL};
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef HALMAC_POWER_SEQUENCE_8822B
#define HALMAC_POWER_SEQUENCE_8822B
#include "../../halmac_pwr_seq_cmd.h"
#define HALMAC_8822B_PWR_SEQ_VER "V17"
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_card_disable_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_card_enable_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_suspend_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_resume_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_hwpdn_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_lps_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_deep_lps_flow[];
extern struct halmac_wl_pwr_cfg_ *halmac_8822b_leave_lps_flow[];
#endif
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_8822b_cfg.h"
#include "halmac_func_8822b.h"
#include "../halmac_func_88xx.h"
/**
* halmac_mount_api_8822b() - attach functions to function pointer
* @halmac_adapter
*
* SD1 internal use
*
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
*/
enum halmac_ret_status
halmac_mount_api_8822b(struct halmac_adapter *halmac_adapter)
{
struct halmac_api *halmac_api =
(struct halmac_api *)halmac_adapter->halmac_api;
halmac_adapter->chip_id = HALMAC_CHIP_ID_8822B;
halmac_adapter->hw_config_info.efuse_size = HALMAC_EFUSE_SIZE_8822B;
halmac_adapter->hw_config_info.eeprom_size = HALMAC_EEPROM_SIZE_8822B;
halmac_adapter->hw_config_info.bt_efuse_size =
HALMAC_BT_EFUSE_SIZE_8822B;
halmac_adapter->hw_config_info.cam_entry_num =
HALMAC_SECURITY_CAM_ENTRY_NUM_8822B;
halmac_adapter->hw_config_info.txdesc_size = HALMAC_TX_DESC_SIZE_8822B;
halmac_adapter->hw_config_info.rxdesc_size = HALMAC_RX_DESC_SIZE_8822B;
halmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_8822B;
halmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_8822B;
halmac_adapter->hw_config_info.page_size = HALMAC_TX_PAGE_SIZE_8822B;
halmac_adapter->hw_config_info.tx_align_size =
HALMAC_TX_ALIGN_SIZE_8822B;
halmac_adapter->hw_config_info.page_size_2_power =
HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
halmac_adapter->txff_allocation.rsvd_drv_pg_num =
HALMAC_RSVD_DRV_PGNUM_8822B;
halmac_api->halmac_init_trx_cfg = halmac_init_trx_cfg_8822b;
halmac_api->halmac_init_protocol_cfg = halmac_init_protocol_cfg_8822b;
halmac_api->halmac_init_h2c = halmac_init_h2c_8822b;
if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
halmac_api->halmac_tx_allowed_sdio =
halmac_tx_allowed_sdio_88xx;
halmac_api->halmac_cfg_tx_agg_align =
halmac_cfg_tx_agg_align_sdio_not_support_88xx;
halmac_api->halmac_mac_power_switch =
halmac_mac_power_switch_8822b_sdio;
halmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_sdio;
halmac_api->halmac_interface_integration_tuning =
halmac_interface_integration_tuning_8822b_sdio;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
halmac_api->halmac_mac_power_switch =
halmac_mac_power_switch_8822b_usb;
halmac_api->halmac_cfg_tx_agg_align =
halmac_cfg_tx_agg_align_usb_not_support_88xx;
halmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_usb;
halmac_api->halmac_interface_integration_tuning =
halmac_interface_integration_tuning_8822b_usb;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) {
halmac_api->halmac_mac_power_switch =
halmac_mac_power_switch_8822b_pcie;
halmac_api->halmac_cfg_tx_agg_align =
halmac_cfg_tx_agg_align_pcie_not_support_88xx;
halmac_api->halmac_pcie_switch = halmac_pcie_switch_8822b;
halmac_api->halmac_phy_cfg = halmac_phy_cfg_8822b_pcie;
halmac_api->halmac_interface_integration_tuning =
halmac_interface_integration_tuning_8822b_pcie;
} else {
halmac_api->halmac_pcie_switch = halmac_pcie_switch_8822b_nc;
}
return HALMAC_RET_SUCCESS;
}
/**
* halmac_init_trx_cfg_8822b() - config trx dma register
* @halmac_adapter : the adapter of halmac
* @halmac_trx_mode : trx mode selection
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_trx_cfg_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode)
{
u8 value8;
u32 value32;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_TRX_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
halmac_adapter->trx_mode = halmac_trx_mode;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_init_trx_cfg ==========>halmac_trx_mode = %d\n",
halmac_trx_mode);
status = halmac_txdma_queue_mapping_8822b(halmac_adapter,
halmac_trx_mode);
if (status != HALMAC_RET_SUCCESS) {
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_txdma_queue_mapping fail!\n");
return status;
}
value8 = 0;
HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
value8 = HALMAC_CR_TRX_ENABLE_8822B;
HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2CQ_CSR, BIT(31));
status = halmac_priority_queue_config_8822b(halmac_adapter,
halmac_trx_mode);
if (halmac_adapter->txff_allocation.rx_fifo_expanding_mode !=
HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
HALMAC_REG_WRITE_8(halmac_adapter, REG_RX_DRVINFO_SZ, 0xF);
if (status != HALMAC_RET_SUCCESS) {
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_txdma_queue_mapping fail!\n");
return status;
}
/* Config H2C packet buffer */
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_HEAD);
value32 = (value32 & 0xFFFC0000) |
(halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_HEAD, value32);
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_READ_ADDR);
value32 = (value32 & 0xFFFC0000) |
(halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_READ_ADDR, value32);
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_TAIL);
value32 = (value32 & 0xFFFC0000) |
((halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B) +
(HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B));
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_TAIL, value32);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
value8 = (u8)((value8 & 0xFC) | 0x01);
HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
value8 = (u8)((value8 & 0xFB) | 0x04);
HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1);
value8 = (u8)((value8 & 0x7f) | 0x80);
HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8);
halmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
halmac_get_h2c_buff_free_space_88xx(halmac_adapter);
if (halmac_adapter->h2c_buff_size !=
halmac_adapter->h2c_buf_free_space) {
pr_err("get h2c free space error!\n");
return HALMAC_RET_GET_H2C_SPACE_ERR;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_init_trx_cfg <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_init_protocol_cfg_8822b() - config protocol register
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_protocol_cfg_8822b(struct halmac_adapter *halmac_adapter)
{
u32 value32;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_PROTOCOL_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"[TRACE]%s ==========>\n", __func__);
HALMAC_REG_WRITE_8(halmac_adapter, REG_AMPDU_MAX_TIME_V1,
HALMAC_AMPDU_MAX_TIME_8822B);
HALMAC_REG_WRITE_8(halmac_adapter, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
value32 = HALMAC_PROT_RTS_LEN_TH_8822B |
(HALMAC_PROT_RTS_TX_TIME_TH_8822B << 8) |
(HALMAC_PROT_MAX_AGG_PKT_LIMIT_8822B << 16) |
(HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8822B << 24);
HALMAC_REG_WRITE_32(halmac_adapter, REG_PROT_MODE_CTRL, value32);
HALMAC_REG_WRITE_16(halmac_adapter, REG_BAR_MODE_CTRL + 2,
HALMAC_BAR_RETRY_LIMIT_8822B |
HALMAC_RA_TRY_RATE_AGG_LIMIT_8822B << 8);
HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_VOVI_SETTING,
HALMAC_FAST_EDCA_VO_TH_8822B);
HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_VOVI_SETTING + 2,
HALMAC_FAST_EDCA_VI_TH_8822B);
HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_BEBK_SETTING,
HALMAC_FAST_EDCA_BE_TH_8822B);
HALMAC_REG_WRITE_8(halmac_adapter, REG_FAST_EDCA_BEBK_SETTING + 2,
HALMAC_FAST_EDCA_BK_TH_8822B);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"[TRACE]%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_init_h2c_8822b() - config h2c packet buffer
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_h2c_8822b(struct halmac_adapter *halmac_adapter)
{
u8 value8;
u32 value32;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
value8 = 0;
HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
value8 = HALMAC_CR_TRX_ENABLE_8822B;
HALMAC_REG_WRITE_8(halmac_adapter, REG_CR, value8);
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_HEAD);
value32 = (value32 & 0xFFFC0000) |
(halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_HEAD, value32);
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_READ_ADDR);
value32 = (value32 & 0xFFFC0000) |
(halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_READ_ADDR, value32);
value32 = HALMAC_REG_READ_32(halmac_adapter, REG_H2C_TAIL);
value32 = (value32 & 0xFFFC0000) |
((halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B) +
(HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B));
HALMAC_REG_WRITE_32(halmac_adapter, REG_H2C_TAIL, value32);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
value8 = (u8)((value8 & 0xFC) | 0x01);
HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_H2C_INFO);
value8 = (u8)((value8 & 0xFB) | 0x04);
HALMAC_REG_WRITE_8(halmac_adapter, REG_H2C_INFO, value8);
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1);
value8 = (u8)((value8 & 0x7f) | 0x80);
HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8);
halmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B
<< HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
halmac_get_h2c_buff_free_space_88xx(halmac_adapter);
if (halmac_adapter->h2c_buff_size !=
halmac_adapter->h2c_buf_free_space) {
pr_err("get h2c free space error!\n");
return HALMAC_RET_GET_H2C_SPACE_ERR;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"h2c free space : %d\n",
halmac_adapter->h2c_buf_free_space);
return HALMAC_RET_SUCCESS;
}
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_8822B_H_
#define _HALMAC_API_8822B_H_
#include "../../halmac_2_platform.h"
#include "../../halmac_type.h"
enum halmac_ret_status
halmac_mount_api_8822b(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_init_trx_cfg_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode);
enum halmac_ret_status
halmac_init_protocol_cfg_8822b(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_init_h2c_8822b(struct halmac_adapter *halmac_adapter);
#endif /* _HALMAC_API_8822B_H_ */
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halmac_88xx_cfg.h"
#include "../halmac_api_88xx_pcie.h"
#include "halmac_8822b_cfg.h"
/**
* halmac_mac_power_switch_8822b_pcie() - switch mac power
* @halmac_adapter : the adapter of halmac
* @halmac_power : power state
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_mac_power_switch_8822b_pcie(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power)
{
u8 interface_mask;
u8 value8;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_mac_power_switch_88xx_pcie halmac_power = %x ==========>\n",
halmac_power);
interface_mask = HALMAC_PWR_INTF_PCI_MSK;
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR);
if (value8 == 0xEA)
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
else
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
/* Check if power switch is needed */
if (halmac_power == HALMAC_MAC_POWER_ON &&
halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_WARNING,
"halmac_mac_power_switch power state unchange!\n");
return HALMAC_RET_PWR_UNCHANGE;
}
if (halmac_power == HALMAC_MAC_POWER_OFF) {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_disable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("Handle power off cmd error\n");
return HALMAC_RET_POWER_OFF_FAIL;
}
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
halmac_adapter->halmac_state.ps_state =
HALMAC_PS_STATE_UNDEFINE;
halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
halmac_init_adapter_dynamic_para_88xx(halmac_adapter);
} else {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_enable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("Handle power on cmd error\n");
return HALMAC_RET_POWER_ON_FAIL;
}
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
halmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_mac_power_switch_88xx_pcie <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_pcie_switch_8822b() - pcie gen1/gen2 switch
* @halmac_adapter : the adapter of halmac
* @pcie_cfg : gen1/gen2 selection
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_pcie_switch_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_pcie_cfg pcie_cfg)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
u8 current_link_speed = 0;
u32 count = 0;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PCIE_SWITCH);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"%s ==========>\n", __func__);
/* Link Control 2 Register[3:0] Target Link Speed
* Defined encodings are:
* 0001b Target Link 2.5 GT/s
* 0010b Target Link 5.0 GT/s
* 0100b Target Link 8.0 GT/s
*/
if (pcie_cfg == HALMAC_PCIE_GEN1) {
/* cfg 0xA0[3:0]=4'b0001 */
halmac_dbi_write8_88xx(
halmac_adapter, LINK_CTRL2_REG_OFFSET,
(halmac_dbi_read8_88xx(halmac_adapter,
LINK_CTRL2_REG_OFFSET) &
0xF0) | BIT(0));
/* cfg 0x80C[17]=1 //PCIe DesignWave */
halmac_dbi_write32_88xx(
halmac_adapter, GEN2_CTRL_OFFSET,
halmac_dbi_read32_88xx(halmac_adapter,
GEN2_CTRL_OFFSET) |
BIT(17));
/* check link speed if GEN1 */
/* cfg 0x82[3:0]=4'b0001 */
current_link_speed =
halmac_dbi_read8_88xx(halmac_adapter,
LINK_STATUS_REG_OFFSET) &
0x0F;
count = 2000;
while (current_link_speed != GEN1_SPEED && count != 0) {
usleep_range(50, 60);
current_link_speed =
halmac_dbi_read8_88xx(halmac_adapter,
LINK_STATUS_REG_OFFSET) &
0x0F;
count--;
}
if (current_link_speed != GEN1_SPEED) {
pr_err("Speed change to GEN1 fail !\n");
return HALMAC_RET_FAIL;
}
} else if (pcie_cfg == HALMAC_PCIE_GEN2) {
/* cfg 0xA0[3:0]=4'b0010 */
halmac_dbi_write8_88xx(
halmac_adapter, LINK_CTRL2_REG_OFFSET,
(halmac_dbi_read8_88xx(halmac_adapter,
LINK_CTRL2_REG_OFFSET) &
0xF0) | BIT(1));
/* cfg 0x80C[17]=1 //PCIe DesignWave */
halmac_dbi_write32_88xx(
halmac_adapter, GEN2_CTRL_OFFSET,
halmac_dbi_read32_88xx(halmac_adapter,
GEN2_CTRL_OFFSET) |
BIT(17));
/* check link speed if GEN2 */
/* cfg 0x82[3:0]=4'b0010 */
current_link_speed =
halmac_dbi_read8_88xx(halmac_adapter,
LINK_STATUS_REG_OFFSET) &
0x0F;
count = 2000;
while (current_link_speed != GEN2_SPEED && count != 0) {
usleep_range(50, 60);
current_link_speed =
halmac_dbi_read8_88xx(halmac_adapter,
LINK_STATUS_REG_OFFSET) &
0x0F;
count--;
}
if (current_link_speed != GEN2_SPEED) {
pr_err("Speed change to GEN1 fail !\n");
return HALMAC_RET_FAIL;
}
} else {
pr_err("Error Speed !\n");
return HALMAC_RET_FAIL;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
halmac_pcie_switch_8822b_nc(struct halmac_adapter *halmac_adapter,
enum halmac_pcie_cfg pcie_cfg)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PCIE_SWITCH);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_phy_cfg_8822b_pcie() - phy config
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_phy_cfg_8822b_pcie(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform)
{
void *driver_adapter = NULL;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PHY_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg ==========>\n");
status = halmac_parse_intf_phy_88xx(halmac_adapter,
HALMAC_RTL8822B_PCIE_PHY_GEN1,
platform, HAL_INTF_PHY_PCIE_GEN1);
if (status != HALMAC_RET_SUCCESS)
return status;
status = halmac_parse_intf_phy_88xx(halmac_adapter,
HALMAC_RTL8822B_PCIE_PHY_GEN2,
platform, HAL_INTF_PHY_PCIE_GEN2);
if (status != HALMAC_RET_SUCCESS)
return status;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_interface_integration_tuning_8822b_pcie() - pcie interface fine tuning
* @halmac_adapter : the adapter of halmac
* Author : Rick Liu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_interface_integration_tuning_8822b_pcie(
struct halmac_adapter *halmac_adapter)
{
return HALMAC_RET_SUCCESS;
}
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_8822B_PCIE_H_
#define _HALMAC_API_8822B_PCIE_H_
#include "../../halmac_2_platform.h"
#include "../../halmac_type.h"
extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN1[];
extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN2[];
enum halmac_ret_status
halmac_mac_power_switch_8822b_pcie(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power);
enum halmac_ret_status
halmac_pcie_switch_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_pcie_cfg pcie_cfg);
enum halmac_ret_status
halmac_pcie_switch_8822b_nc(struct halmac_adapter *halmac_adapter,
enum halmac_pcie_cfg pcie_cfg);
enum halmac_ret_status
halmac_phy_cfg_8822b_pcie(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform);
enum halmac_ret_status halmac_interface_integration_tuning_8822b_pcie(
struct halmac_adapter *halmac_adapter);
#endif /* _HALMAC_API_8822B_PCIE_H_ */
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_8822b_cfg.h"
/**
* halmac_mac_power_switch_8822b_sdio() - switch mac power
* @halmac_adapter : the adapter of halmac
* @halmac_power : power state
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_mac_power_switch_8822b_sdio(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power)
{
u8 interface_mask;
u8 value8;
u8 rpwm;
u32 imr_backup;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"[TRACE]halmac_mac_power_switch_88xx_sdio==========>\n");
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"[TRACE]halmac_power = %x ==========>\n", halmac_power);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"[TRACE]8822B pwr seq ver = %s\n",
HALMAC_8822B_PWR_SEQ_VER);
interface_mask = HALMAC_PWR_INTF_SDIO_MSK;
halmac_adapter->rpwm_record =
HALMAC_REG_READ_8(halmac_adapter, REG_SDIO_HRPWM1);
/* Check FW still exist or not */
if (HALMAC_REG_READ_16(halmac_adapter, REG_MCUFW_CTRL) == 0xC078) {
/* Leave 32K */
rpwm = (u8)((halmac_adapter->rpwm_record ^ BIT(7)) & 0x80);
HALMAC_REG_WRITE_8(halmac_adapter, REG_SDIO_HRPWM1, rpwm);
}
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR);
if (value8 == 0xEA)
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
else
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
/*Check if power switch is needed*/
if (halmac_power == HALMAC_MAC_POWER_ON &&
halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_WARNING,
"[WARN]halmac_mac_power_switch power state unchange!\n");
return HALMAC_RET_PWR_UNCHANGE;
}
imr_backup = HALMAC_REG_READ_32(halmac_adapter, REG_SDIO_HIMR);
HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR, 0);
if (halmac_power == HALMAC_MAC_POWER_OFF) {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_disable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("[ERR]Handle power off cmd error\n");
HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR,
imr_backup);
return HALMAC_RET_POWER_OFF_FAIL;
}
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
halmac_adapter->halmac_state.ps_state =
HALMAC_PS_STATE_UNDEFINE;
halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
halmac_init_adapter_dynamic_para_88xx(halmac_adapter);
} else {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_enable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("[ERR]Handle power on cmd error\n");
HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR,
imr_backup);
return HALMAC_RET_POWER_ON_FAIL;
}
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
halmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
}
HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_HIMR, imr_backup);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"[TRACE]halmac_mac_power_switch_88xx_sdio <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_phy_cfg_8822b_sdio() - phy config
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_phy_cfg_8822b_sdio(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PHY_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg ==========>\n");
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"sdio no phy\n");
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_interface_integration_tuning_8822b_sdio() - sdio interface fine tuning
* @halmac_adapter : the adapter of halmac
* Author : Ivan
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_interface_integration_tuning_8822b_sdio(
struct halmac_adapter *halmac_adapter)
{
return HALMAC_RET_SUCCESS;
}
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_8822B_SDIO_H_
#define _HALMAC_API_8822B_SDIO_H_
#include "../../halmac_2_platform.h"
#include "../../halmac_type.h"
enum halmac_ret_status
halmac_mac_power_switch_8822b_sdio(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power);
enum halmac_ret_status
halmac_phy_cfg_8822b_sdio(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform);
enum halmac_ret_status halmac_interface_integration_tuning_8822b_sdio(
struct halmac_adapter *halmac_adapter);
#endif /* _HALMAC_API_8822B_SDIO_H_ */
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../halmac_88xx_cfg.h"
#include "halmac_8822b_cfg.h"
/**
* halmac_mac_power_switch_8822b_usb() - switch mac power
* @halmac_adapter : the adapter of halmac
* @halmac_power : power state
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_mac_power_switch_8822b_usb(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power)
{
u8 interface_mask;
u8 value8;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_mac_power_switch_88xx_usb halmac_power = %x ==========>\n",
halmac_power);
interface_mask = HALMAC_PWR_INTF_USB_MSK;
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_CR);
if (value8 == 0xEA) {
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
} else {
if (BIT(0) ==
(HALMAC_REG_READ_8(halmac_adapter, REG_SYS_STATUS1 + 1) &
BIT(0)))
halmac_adapter->halmac_state.mac_power =
HALMAC_MAC_POWER_OFF;
else
halmac_adapter->halmac_state.mac_power =
HALMAC_MAC_POWER_ON;
}
/*Check if power switch is needed*/
if (halmac_power == HALMAC_MAC_POWER_ON &&
halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) {
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_PWR, DBG_WARNING,
"halmac_mac_power_switch power state unchange!\n");
return HALMAC_RET_PWR_UNCHANGE;
}
if (halmac_power == HALMAC_MAC_POWER_OFF) {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_disable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("Handle power off cmd error\n");
return HALMAC_RET_POWER_OFF_FAIL;
}
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
halmac_adapter->halmac_state.ps_state =
HALMAC_PS_STATE_UNDEFINE;
halmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
halmac_init_adapter_dynamic_para_88xx(halmac_adapter);
} else {
if (halmac_pwr_seq_parser_88xx(
halmac_adapter, HALMAC_PWR_CUT_ALL_MSK,
HALMAC_PWR_FAB_TSMC_MSK, interface_mask,
halmac_8822b_card_enable_flow) !=
HALMAC_RET_SUCCESS) {
pr_err("Handle power on cmd error\n");
return HALMAC_RET_POWER_ON_FAIL;
}
HALMAC_REG_WRITE_8(
halmac_adapter, REG_SYS_STATUS1 + 1,
HALMAC_REG_READ_8(halmac_adapter, REG_SYS_STATUS1 + 1) &
~(BIT(0)));
halmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
halmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_mac_power_switch_88xx_usb <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_phy_cfg_8822b_usb() - phy config
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_phy_cfg_8822b_usb(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform)
{
void *driver_adapter = NULL;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_PHY_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg ==========>\n");
status = halmac_parse_intf_phy_88xx(halmac_adapter,
HALMAC_RTL8822B_USB2_PHY, platform,
HAL_INTF_PHY_USB2);
if (status != HALMAC_RET_SUCCESS)
return status;
status = halmac_parse_intf_phy_88xx(halmac_adapter,
HALMAC_RTL8822B_USB3_PHY, platform,
HAL_INTF_PHY_USB3);
if (status != HALMAC_RET_SUCCESS)
return status;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_PWR, DBG_DMESG,
"halmac_phy_cfg <==========\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_interface_integration_tuning_8822b_usb() - usb interface fine tuning
* @halmac_adapter : the adapter of halmac
* Author : Ivan
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_interface_integration_tuning_8822b_usb(
struct halmac_adapter *halmac_adapter)
{
return HALMAC_RET_SUCCESS;
}
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_8822B_USB_H_
#define _HALMAC_API_8822B_USB_H_
extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB2_PHY[];
extern struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB3_PHY[];
#include "../../halmac_2_platform.h"
#include "../../halmac_type.h"
enum halmac_ret_status
halmac_mac_power_switch_8822b_usb(struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power);
enum halmac_ret_status
halmac_phy_cfg_8822b_usb(struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform);
enum halmac_ret_status halmac_interface_integration_tuning_8822b_usb(
struct halmac_adapter *halmac_adapter);
#endif /* _HALMAC_API_8822B_USB_H_ */
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_8822b_cfg.h"
#include "halmac_func_8822b.h"
/*SDIO RQPN Mapping*/
static struct halmac_rqpn_ HALMAC_RQPN_SDIO_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
};
/*PCIE RQPN Mapping*/
static struct halmac_rqpn_ HALMAC_RQPN_PCIE_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
};
/*USB 2 Bulkout RQPN Mapping*/
static struct halmac_rqpn_ HALMAC_RQPN_2BULKOUT_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
};
/*USB 3 Bulkout RQPN Mapping*/
static struct halmac_rqpn_ HALMAC_RQPN_3BULKOUT_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
};
/*USB 4 Bulkout RQPN Mapping*/
static struct halmac_rqpn_ HALMAC_RQPN_4BULKOUT_8822B[] = {
/* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
{HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ,
HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
};
/*SDIO Page Number*/
static struct halmac_pg_num_ HALMAC_PG_NUM_SDIO_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
};
/*PCIE Page Number*/
static struct halmac_pg_num_ HALMAC_PG_NUM_PCIE_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
};
/*USB 2 Bulkout Page Number*/
static struct halmac_pg_num_ HALMAC_PG_NUM_2BULKOUT_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1024},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1024},
};
/*USB 3 Bulkout Page Number*/
static struct halmac_pg_num_ HALMAC_PG_NUM_3BULKOUT_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1024},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1024},
};
/*USB 4 Bulkout Page Number*/
static struct halmac_pg_num_ HALMAC_PG_NUM_4BULKOUT_8822B[] = {
/* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
{HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
{HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
{HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
};
enum halmac_ret_status
halmac_txdma_queue_mapping_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode)
{
u16 value16;
void *driver_adapter = NULL;
struct halmac_rqpn_ *curr_rqpn_sel = NULL;
enum halmac_ret_status status;
struct halmac_api *halmac_api;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
curr_rqpn_sel = HALMAC_RQPN_SDIO_8822B;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) {
curr_rqpn_sel = HALMAC_RQPN_PCIE_8822B;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
if (halmac_adapter->halmac_bulkout_num == 2) {
curr_rqpn_sel = HALMAC_RQPN_2BULKOUT_8822B;
} else if (halmac_adapter->halmac_bulkout_num == 3) {
curr_rqpn_sel = HALMAC_RQPN_3BULKOUT_8822B;
} else if (halmac_adapter->halmac_bulkout_num == 4) {
curr_rqpn_sel = HALMAC_RQPN_4BULKOUT_8822B;
} else {
pr_err("[ERR]interface not support\n");
return HALMAC_RET_NOT_SUPPORT;
}
} else {
return HALMAC_RET_NOT_SUPPORT;
}
status = halmac_rqpn_parser_88xx(halmac_adapter, halmac_trx_mode,
curr_rqpn_sel);
if (status != HALMAC_RET_SUCCESS)
return status;
value16 = 0;
value16 |= BIT_TXDMA_HIQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]);
value16 |= BIT_TXDMA_MGQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]);
value16 |= BIT_TXDMA_BKQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]);
value16 |= BIT_TXDMA_BEQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]);
value16 |= BIT_TXDMA_VIQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]);
value16 |= BIT_TXDMA_VOQ_MAP(
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]);
HALMAC_REG_WRITE_16(halmac_adapter, REG_TXDMA_PQ_MAP, value16);
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status
halmac_priority_queue_config_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode)
{
u8 transfer_mode = 0;
u8 value8;
u32 counter;
enum halmac_ret_status status;
struct halmac_pg_num_ *curr_pg_num = NULL;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if (halmac_adapter->txff_allocation.la_mode == HALMAC_LA_MODE_DISABLE) {
if (halmac_adapter->txff_allocation.rx_fifo_expanding_mode ==
HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) {
halmac_adapter->txff_allocation.tx_fifo_pg_num =
HALMAC_TX_FIFO_SIZE_8822B >>
HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
} else if (halmac_adapter->txff_allocation
.rx_fifo_expanding_mode ==
HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) {
halmac_adapter->txff_allocation.tx_fifo_pg_num =
HALMAC_TX_FIFO_SIZE_EX_1_BLK_8822B >>
HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
halmac_adapter->hw_config_info.tx_fifo_size =
HALMAC_TX_FIFO_SIZE_EX_1_BLK_8822B;
if (HALMAC_RX_FIFO_SIZE_EX_1_BLK_8822B <=
HALMAC_RX_FIFO_SIZE_EX_1_BLK_MAX_8822B)
halmac_adapter->hw_config_info.rx_fifo_size =
HALMAC_RX_FIFO_SIZE_EX_1_BLK_8822B;
else
halmac_adapter->hw_config_info.rx_fifo_size =
HALMAC_RX_FIFO_SIZE_EX_1_BLK_MAX_8822B;
} else {
halmac_adapter->txff_allocation.tx_fifo_pg_num =
HALMAC_TX_FIFO_SIZE_8822B >>
HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
pr_err("[ERR]rx_fifo_expanding_mode = %d not support\n",
halmac_adapter->txff_allocation
.rx_fifo_expanding_mode);
}
} else {
halmac_adapter->txff_allocation.tx_fifo_pg_num =
HALMAC_TX_FIFO_SIZE_LA_8822B >>
HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
}
halmac_adapter->txff_allocation.rsvd_pg_num =
(halmac_adapter->txff_allocation.rsvd_drv_pg_num +
HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B +
HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B +
HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B +
HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B);
if (halmac_adapter->txff_allocation.rsvd_pg_num >
halmac_adapter->txff_allocation.tx_fifo_pg_num)
return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
halmac_adapter->txff_allocation.ac_q_pg_num =
halmac_adapter->txff_allocation.tx_fifo_pg_num -
halmac_adapter->txff_allocation.rsvd_pg_num;
halmac_adapter->txff_allocation.rsvd_pg_bndy =
halmac_adapter->txff_allocation.tx_fifo_pg_num -
halmac_adapter->txff_allocation.rsvd_pg_num;
halmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy =
halmac_adapter->txff_allocation.tx_fifo_pg_num -
HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B;
halmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy =
halmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy -
HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B;
halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy =
halmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy -
HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B;
halmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy =
halmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy -
HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B;
halmac_adapter->txff_allocation.rsvd_drv_pg_bndy =
halmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy -
halmac_adapter->txff_allocation.rsvd_drv_pg_num;
if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
curr_pg_num = HALMAC_PG_NUM_SDIO_8822B;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_PCIE) {
curr_pg_num = HALMAC_PG_NUM_PCIE_8822B;
} else if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
if (halmac_adapter->halmac_bulkout_num == 2) {
curr_pg_num = HALMAC_PG_NUM_2BULKOUT_8822B;
} else if (halmac_adapter->halmac_bulkout_num == 3) {
curr_pg_num = HALMAC_PG_NUM_3BULKOUT_8822B;
} else if (halmac_adapter->halmac_bulkout_num == 4) {
curr_pg_num = HALMAC_PG_NUM_4BULKOUT_8822B;
} else {
pr_err("[ERR]interface not support\n");
return HALMAC_RET_NOT_SUPPORT;
}
} else {
return HALMAC_RET_NOT_SUPPORT;
}
status = halmac_pg_num_parser_88xx(halmac_adapter, halmac_trx_mode,
curr_pg_num);
if (status != HALMAC_RET_SUCCESS)
return status;
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_1,
halmac_adapter->txff_allocation.high_queue_pg_num);
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_2,
halmac_adapter->txff_allocation.low_queue_pg_num);
HALMAC_REG_WRITE_16(
halmac_adapter, REG_FIFOPAGE_INFO_3,
halmac_adapter->txff_allocation.normal_queue_pg_num);
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_4,
halmac_adapter->txff_allocation.extra_queue_pg_num);
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_INFO_5,
halmac_adapter->txff_allocation.pub_queue_pg_num);
halmac_adapter->sdio_free_space.high_queue_number =
halmac_adapter->txff_allocation.high_queue_pg_num;
halmac_adapter->sdio_free_space.normal_queue_number =
halmac_adapter->txff_allocation.normal_queue_pg_num;
halmac_adapter->sdio_free_space.low_queue_number =
halmac_adapter->txff_allocation.low_queue_pg_num;
halmac_adapter->sdio_free_space.public_queue_number =
halmac_adapter->txff_allocation.pub_queue_pg_num;
halmac_adapter->sdio_free_space.extra_queue_number =
halmac_adapter->txff_allocation.extra_queue_pg_num;
HALMAC_REG_WRITE_32(
halmac_adapter, REG_RQPN_CTRL_2,
HALMAC_REG_READ_32(halmac_adapter, REG_RQPN_CTRL_2) | BIT(31));
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2,
(u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
BIT_MASK_BCN_HEAD_1_V1));
HALMAC_REG_WRITE_16(halmac_adapter, REG_BCNQ_BDNY_V1,
(u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
BIT_MASK_BCNQ_PGBNDY_V1));
HALMAC_REG_WRITE_16(halmac_adapter, REG_FIFOPAGE_CTRL_2 + 2,
(u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
BIT_MASK_BCN_HEAD_1_V1));
HALMAC_REG_WRITE_16(halmac_adapter, REG_BCNQ1_BDNY_V1,
(u16)(halmac_adapter->txff_allocation.rsvd_pg_bndy &
BIT_MASK_BCNQ_PGBNDY_V1));
HALMAC_REG_WRITE_32(halmac_adapter, REG_RXFF_BNDY,
halmac_adapter->hw_config_info.rx_fifo_size -
HALMAC_C2H_PKT_BUF_8822B - 1);
if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_USB) {
value8 = (u8)(
HALMAC_REG_READ_8(halmac_adapter, REG_AUTO_LLT_V1) &
~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM));
value8 = (u8)(value8 | (HALMAC_BLK_DESC_NUM_8822B
<< BIT_SHIFT_BLK_DESC_NUM));
HALMAC_REG_WRITE_8(halmac_adapter, REG_AUTO_LLT_V1, value8);
HALMAC_REG_WRITE_8(halmac_adapter, REG_AUTO_LLT_V1 + 3,
HALMAC_BLK_DESC_NUM_8822B);
HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_OFFSET_CHK + 1,
HALMAC_REG_READ_8(halmac_adapter,
REG_TXDMA_OFFSET_CHK + 1) |
BIT(1));
}
HALMAC_REG_WRITE_8(
halmac_adapter, REG_AUTO_LLT_V1,
(u8)(HALMAC_REG_READ_8(halmac_adapter, REG_AUTO_LLT_V1) |
BIT_AUTO_INIT_LLT_V1));
counter = 1000;
while (HALMAC_REG_READ_8(halmac_adapter, REG_AUTO_LLT_V1) &
BIT_AUTO_INIT_LLT_V1) {
counter--;
if (counter == 0)
return HALMAC_RET_INIT_LLT_FAIL;
}
if (halmac_trx_mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) {
transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY;
HALMAC_REG_WRITE_16(
halmac_adapter, REG_WMAC_LBK_BUF_HD_V1,
(u16)halmac_adapter->txff_allocation.rsvd_pg_bndy);
} else if (halmac_trx_mode == HALMAC_TRX_MODE_LOOPBACK) {
transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;
} else {
transfer_mode = HALMAC_TRNSFER_NORMAL;
}
HALMAC_REG_WRITE_8(halmac_adapter, REG_CR + 3, (u8)transfer_mode);
return HALMAC_RET_SUCCESS;
}
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_FUNC_8822B_H_
#define _HALMAC_FUNC_8822B_H_
#include "../../halmac_type.h"
enum halmac_ret_status
halmac_txdma_queue_mapping_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode);
enum halmac_ret_status
halmac_priority_queue_config_8822b(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode);
#endif /* _HALMAC_FUNC_8822B_H_ */
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_88xx_cfg.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_88XX_CFG_H_
#define _HALMAC_88XX_CFG_H_
#include "../halmac_2_platform.h"
#include "../halmac_type.h"
#include "../halmac_api.h"
#include "../halmac_bit2.h"
#include "../halmac_reg2.h"
#include "../halmac_pwr_seq_cmd.h"
#include "halmac_func_88xx.h"
#include "halmac_api_88xx.h"
#include "halmac_api_88xx_usb.h"
#include "halmac_api_88xx_pcie.h"
#include "halmac_api_88xx_sdio.h"
#define HALMAC_SVN_VER_88XX "13359M"
#define HALMAC_MAJOR_VER_88XX 0x0001 /* major version, ver_1 for async_api */
/* For halmac_api num change or prototype change, increment prototype version.
* Otherwise, increase minor version
*/
#define HALMAC_PROTOTYPE_VER_88XX 0x0003 /* prototype version */
#define HALMAC_MINOR_VER_88XX 0x0005 /* minor version */
#define HALMAC_PATCH_VER_88XX 0x0000 /* patch version */
#define HALMAC_C2H_DATA_OFFSET_88XX 10
#define HALMAC_RX_AGG_ALIGNMENT_SIZE_88XX 8
#define HALMAC_TX_AGG_ALIGNMENT_SIZE_88XX 8
#define HALMAC_TX_AGG_BUFF_SIZE_88XX 32768
#define HALMAC_EXTRA_INFO_BUFF_SIZE_88XX 4096 /*4K*/
#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX 16384 /*16K*/
#define HALMAC_FW_OFFLOAD_CMD_SIZE_88XX \
12 /*Fw config parameter cmd size, each 12 byte*/
#define HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX 8
#define HALMAC_H2C_CMD_SIZE_UNIT_88XX 32 /* Only support 32 byte packet now */
#define HALMAC_NLO_INFO_SIZE_88XX 1024
/* Download FW */
#define HALMAC_FW_SIZE_MAX_88XX 0x40000
#define HALMAC_FWHDR_SIZE_88XX 64
#define HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX 8
#define HALMAC_FW_MAX_DL_SIZE_88XX 0x2000 /* need power of 2 */
/* Max dlfw size can not over 31K, because SDIO HW restriction */
#define HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX 0x7C00
#define DLFW_RESTORE_REG_NUM_88XX 9
#define ID_INFORM_DLEMEM_RDY 0x80
/* FW header information */
#define HALMAC_FWHDR_OFFSET_VERSION_88XX 4
#define HALMAC_FWHDR_OFFSET_SUBVERSION_88XX 6
#define HALMAC_FWHDR_OFFSET_SUBINDEX_88XX 7
#define HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX 24
#define HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX 28
#define HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX 32
#define HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX 36
#define HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX 48
#define HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX 52
#define HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX 56
#define HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX 60
/* HW memory address */
#define HALMAC_OCPBASE_TXBUF_88XX 0x18780000
#define HALMAC_OCPBASE_DMEM_88XX 0x00200000
#define HALMAC_OCPBASE_IMEM_88XX 0x00000000
/* define the SDIO Bus CLK threshold, for avoiding CMD53 fails that
* result from SDIO CLK sync to ana_clk fail
*/
#define HALMAC_SD_CLK_THRESHOLD_88XX 150000000 /* 150MHz */
/* MAC clock */
#define HALMAC_MAC_CLOCK_88XX 80 /* 80M */
/* H2C/C2H*/
#define HALMAC_H2C_CMD_SIZE_88XX 32
#define HALMAC_H2C_CMD_HDR_SIZE_88XX 8
#define HALMAC_PROTECTED_EFUSE_SIZE_88XX 0x60
/* Function enable */
#define HALMAC_FUNCTION_ENABLE_88XX 0xDC
/* FIFO size & packet size */
/* #define HALMAC_WOWLAN_PATTERN_SIZE 256 */
/* CFEND rate */
#define HALMAC_BASIC_CFEND_RATE_88XX 0x5
#define HALMAC_STBC_CFEND_RATE_88XX 0xF
/* Response rate */
#define HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX 0xFFFFF
#define HALMAC_RESPONSE_RATE_88XX HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX
/* Spec SIFS */
#define HALMAC_SIFS_CCK_PTCL_88XX 16
#define HALMAC_SIFS_OFDM_PTCL_88XX 16
/* Retry limit */
#define HALMAC_LONG_RETRY_LIMIT_88XX 8
#define HALMAC_SHORT_RETRY_LIMIT_88XX 7
/* Slot, SIFS, PIFS time */
#define HALMAC_SLOT_TIME_88XX 0x05
#define HALMAC_PIFS_TIME_88XX 0x19
#define HALMAC_SIFS_CCK_CTX_88XX 0xA
#define HALMAC_SIFS_OFDM_CTX_88XX 0xA
#define HALMAC_SIFS_CCK_TRX_88XX 0x10
#define HALMAC_SIFS_OFDM_TRX_88XX 0x10
/* TXOP limit */
#define HALMAC_VO_TXOP_LIMIT_88XX 0x186
#define HALMAC_VI_TXOP_LIMIT_88XX 0x3BC
/* NAV */
#define HALMAC_RDG_NAV_88XX 0x05
#define HALMAC_TXOP_NAV_88XX 0x1B
/* TSF */
#define HALMAC_CCK_RX_TSF_88XX 0x30
#define HALMAC_OFDM_RX_TSF_88XX 0x30
/* Send beacon related */
#define HALMAC_TBTT_PROHIBIT_88XX 0x04
#define HALMAC_TBTT_HOLD_TIME_88XX 0x064
#define HALMAC_DRIVER_EARLY_INT_88XX 0x04
#define HALMAC_BEACON_DMA_TIM_88XX 0x02
/* RX filter */
#define HALMAC_RX_FILTER0_RECIVE_ALL_88XX 0xFFFFFFF
#define HALMAC_RX_FILTER0_88XX HALMAC_RX_FILTER0_RECIVE_ALL_88XX
#define HALMAC_RX_FILTER_RECIVE_ALL_88XX 0xFFFF
#define HALMAC_RX_FILTER_88XX HALMAC_RX_FILTER_RECIVE_ALL_88XX
/* RCR */
#define HALMAC_RCR_CONFIG_88XX 0xE400631E
/* Security config */
#define HALMAC_SECURITY_CONFIG_88XX 0x01CC
/* CCK rate ACK timeout */
#define HALMAC_ACK_TO_CCK_88XX 0x40
#endif
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx.c 0 → 100644
View file @ 938a0447
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_88XX_H_
#define _HALMAC_API_88XX_H_
#include "../halmac_2_platform.h"
#include "../halmac_type.h"
void halmac_init_state_machine_88xx(struct halmac_adapter *halmac_adapter);
void halmac_init_adapter_para_88xx(struct halmac_adapter *halmac_adapter);
void halmac_init_adapter_dynamic_para_88xx(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_mount_api_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_download_firmware_88xx(struct halmac_adapter *halmac_adapter,
u8 *hamacl_fw, u32 halmac_fw_size);
enum halmac_ret_status
halmac_free_download_firmware_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_dlfw_mem dlfw_mem, u8 *hamacl_fw,
u32 halmac_fw_size);
enum halmac_ret_status
halmac_get_fw_version_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_fw_version *fw_version);
enum halmac_ret_status
halmac_cfg_mac_addr_88xx(struct halmac_adapter *halmac_adapter, u8 halmac_port,
union halmac_wlan_addr *hal_address);
enum halmac_ret_status
halmac_cfg_bssid_88xx(struct halmac_adapter *halmac_adapter, u8 halmac_port,
union halmac_wlan_addr *hal_address);
enum halmac_ret_status
halmac_cfg_multicast_addr_88xx(struct halmac_adapter *halmac_adapter,
union halmac_wlan_addr *hal_address);
enum halmac_ret_status
halmac_pre_init_system_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_init_system_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg halmac_rxagg_cfg);
enum halmac_ret_status
halmac_init_edca_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_operation_mode_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_wireless_mode wireless_mode);
enum halmac_ret_status
halmac_cfg_ch_bw_88xx(struct halmac_adapter *halmac_adapter, u8 channel,
enum halmac_pri_ch_idx pri_ch_idx, enum halmac_bw bw);
enum halmac_ret_status halmac_cfg_ch_88xx(struct halmac_adapter *halmac_adapter,
u8 channel);
enum halmac_ret_status
halmac_cfg_pri_ch_idx_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_pri_ch_idx pri_ch_idx);
enum halmac_ret_status halmac_cfg_bw_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_bw bw);
enum halmac_ret_status
halmac_init_wmac_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_init_mac_cfg_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode mode);
enum halmac_ret_status
halmac_dump_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
halmac_dump_efuse_map_bt_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_efuse_bank halmac_efuse_bank,
u32 bt_efuse_map_size, u8 *bt_efuse_map);
enum halmac_ret_status
halmac_write_efuse_bt_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_value,
enum halmac_efuse_bank halmac_efuse_bank);
enum halmac_ret_status
halmac_pg_efuse_by_map_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_pg_efuse_info *pg_efuse_info,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
halmac_get_efuse_size_88xx(struct halmac_adapter *halmac_adapter,
u32 *halmac_size);
enum halmac_ret_status
halmac_get_efuse_available_size_88xx(struct halmac_adapter *halmac_adapter,
u32 *halmac_size);
enum halmac_ret_status
halmac_get_c2h_info_88xx(struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
u32 halmac_size);
enum halmac_ret_status
halmac_get_logical_efuse_size_88xx(struct halmac_adapter *halmac_adapter,
u32 *halmac_size);
enum halmac_ret_status
halmac_dump_logical_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
halmac_write_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_value);
enum halmac_ret_status
halmac_read_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 *value);
enum halmac_ret_status
halmac_cfg_fwlps_option_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_fwlps_option *lps_option);
enum halmac_ret_status
halmac_cfg_fwips_option_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_fwips_option *ips_option);
enum halmac_ret_status
halmac_enter_wowlan_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_wowlan_option *wowlan_option);
enum halmac_ret_status
halmac_leave_wowlan_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_enter_ps_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_ps_state ps_state);
enum halmac_ret_status
halmac_leave_ps_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_h2c_lb_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_debug_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_parameter_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_phy_parameter_info *para_info,
u8 full_fifo);
enum halmac_ret_status
halmac_update_packet_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_packet_id pkt_id, u8 *pkt, u32 pkt_size);
enum halmac_ret_status
halmac_bcn_ie_filter_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_bcn_ie_info *bcn_ie_info);
enum halmac_ret_status
halmac_send_original_h2c_88xx(struct halmac_adapter *halmac_adapter,
u8 *original_h2c, u16 *seq, u8 ack);
enum halmac_ret_status
halmac_update_datapack_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_data_type halmac_data_type,
struct halmac_phy_parameter_info *para_info);
enum halmac_ret_status
halmac_run_datapack_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_data_type halmac_data_type);
enum halmac_ret_status
halmac_cfg_drv_info_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_drv_info halmac_drv_info);
enum halmac_ret_status
halmac_send_bt_coex_88xx(struct halmac_adapter *halmac_adapter, u8 *bt_buf,
u32 bt_size, u8 ack);
enum halmac_ret_status
halmac_verify_platform_api_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_timer_2s_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_fill_txdesc_check_sum_88xx(struct halmac_adapter *halmac_adapter,
u8 *cur_desc);
enum halmac_ret_status
halmac_dump_fifo_88xx(struct halmac_adapter *halmac_adapter,
enum hal_fifo_sel halmac_fifo_sel, u32 halmac_start_addr,
u32 halmac_fifo_dump_size, u8 *fifo_map);
u32 halmac_get_fifo_size_88xx(struct halmac_adapter *halmac_adapter,
enum hal_fifo_sel halmac_fifo_sel);
enum halmac_ret_status
halmac_cfg_txbf_88xx(struct halmac_adapter *halmac_adapter, u8 userid,
enum halmac_bw bw, u8 txbf_en);
enum halmac_ret_status
halmac_cfg_mumimo_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_cfg_mumimo_para *cfgmu);
enum halmac_ret_status
halmac_cfg_sounding_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_snd_role role,
enum halmac_data_rate datarate);
enum halmac_ret_status
halmac_del_sounding_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_snd_role role);
enum halmac_ret_status
halmac_su_bfee_entry_init_88xx(struct halmac_adapter *halmac_adapter, u8 userid,
u16 paid);
enum halmac_ret_status
halmac_su_bfer_entry_init_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_su_bfer_init_para *su_bfer_init);
enum halmac_ret_status
halmac_mu_bfee_entry_init_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_mu_bfee_init_para *mu_bfee_init);
enum halmac_ret_status
halmac_mu_bfer_entry_init_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_mu_bfer_init_para *mu_bfer_init);
enum halmac_ret_status
halmac_su_bfee_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid);
enum halmac_ret_status
halmac_su_bfer_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid);
enum halmac_ret_status
halmac_mu_bfee_entry_del_88xx(struct halmac_adapter *halmac_adapter, u8 userid);
enum halmac_ret_status
halmac_mu_bfer_entry_del_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_add_ch_info_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ch_info *ch_info);
enum halmac_ret_status
halmac_add_extra_ch_info_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ch_extra_info *ch_extra_info);
enum halmac_ret_status
halmac_ctrl_ch_switch_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ch_switch_option *cs_option);
enum halmac_ret_status halmac_p2pps_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_p2pps *p2p_ps);
enum halmac_ret_status
halmac_func_p2pps_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_p2pps *p2p_ps);
enum halmac_ret_status
halmac_clear_ch_info_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_send_general_info_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_general_info *general_info);
enum halmac_ret_status
halmac_start_iqk_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_iqk_para_ *iqk_para);
enum halmac_ret_status halmac_ctrl_pwr_tracking_88xx(
struct halmac_adapter *halmac_adapter,
struct halmac_pwr_tracking_option *pwr_tracking_opt);
enum halmac_ret_status
halmac_query_status_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_feature_id feature_id,
enum halmac_cmd_process_status *process_status,
u8 *data, u32 *size);
enum halmac_ret_status
halmac_reset_feature_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_feature_id feature_id);
enum halmac_ret_status
halmac_check_fw_status_88xx(struct halmac_adapter *halmac_adapter,
bool *fw_status);
enum halmac_ret_status
halmac_dump_fw_dmem_88xx(struct halmac_adapter *halmac_adapter, u8 *dmem,
u32 *size);
enum halmac_ret_status
halmac_cfg_max_dl_size_88xx(struct halmac_adapter *halmac_adapter, u32 size);
enum halmac_ret_status halmac_psd_88xx(struct halmac_adapter *halmac_adapter,
u16 start_psd, u16 end_psd);
enum halmac_ret_status
halmac_cfg_la_mode_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_la_mode la_mode);
enum halmac_ret_status halmac_cfg_rx_fifo_expanding_mode_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode);
enum halmac_ret_status
halmac_config_security_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_security_setting *sec_setting);
u8 halmac_get_used_cam_entry_num_88xx(struct halmac_adapter *halmac_adapter,
enum hal_security_type sec_type);
enum halmac_ret_status
halmac_write_cam_88xx(struct halmac_adapter *halmac_adapter, u32 entry_index,
struct halmac_cam_entry_info *cam_entry_info);
enum halmac_ret_status
halmac_read_cam_entry_88xx(struct halmac_adapter *halmac_adapter,
u32 entry_index,
struct halmac_cam_entry_format *content);
enum halmac_ret_status
halmac_clear_cam_entry_88xx(struct halmac_adapter *halmac_adapter,
u32 entry_index);
enum halmac_ret_status
halmac_get_hw_value_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_hw_id hw_id, void *pvalue);
enum halmac_ret_status
halmac_set_hw_value_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_hw_id hw_id, void *pvalue);
enum halmac_ret_status
halmac_cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_drv_rsvd_pg_num pg_num);
enum halmac_ret_status
halmac_get_chip_version_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ver *version);
enum halmac_ret_status
halmac_chk_txdesc_88xx(struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
u32 halmac_size);
enum halmac_ret_status
halmac_dl_drv_rsvd_page_88xx(struct halmac_adapter *halmac_adapter,
u8 pg_offset, u8 *halmac_buf, u32 halmac_size);
enum halmac_ret_status
halmac_cfg_csi_rate_88xx(struct halmac_adapter *halmac_adapter, u8 rssi,
u8 current_rate, u8 fixrate_en, u8 *new_rate);
enum halmac_ret_status halmac_sdio_cmd53_4byte_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_sdio_cmd53_4byte_mode cmd53_4byte_mode);
enum halmac_ret_status
halmac_txfifo_is_empty_88xx(struct halmac_adapter *halmac_adapter, u32 chk_num);
#endif /* _HALMAC_API_H_ */
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_pcie.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_88xx_cfg.h"
/**
* halmac_init_pcie_cfg_88xx() - init PCIe
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_PCIE_CFG);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_deinit_pcie_cfg_88xx() - deinit PCIE
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_deinit_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEINIT_PCIE_CFG);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_rx_aggregation_88xx_pcie() - config rx aggregation
* @halmac_adapter : the adapter of halmac
* @halmac_rx_agg_mode
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_pcie(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter,
HALMAC_API_CFG_RX_AGGREGATION);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_8_pcie_88xx() - read 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u8 halmac_reg_read_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
return PLATFORM_REG_READ_8(driver_adapter, halmac_offset);
}
/**
* halmac_reg_write_8_pcie_88xx() - write 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_8(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_16_pcie_88xx() - read 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u16 halmac_reg_read_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
return PLATFORM_REG_READ_16(driver_adapter, halmac_offset);
}
/**
* halmac_reg_write_16_pcie_88xx() - write 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_16(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_32_pcie_88xx() - read 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32 halmac_reg_read_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
return PLATFORM_REG_READ_32(driver_adapter, halmac_offset);
}
/**
* halmac_reg_write_32_pcie_88xx() - write 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_32(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_tx_agg_align_pcie_88xx() -config sdio bus tx agg alignment
* @halmac_adapter : the adapter of halmac
* @enable : function enable(1)/disable(0)
* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
* Author : Soar Tu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_cfg_tx_agg_align_pcie_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size)
{
struct halmac_api *halmac_api;
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s not support\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_pcie.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_88XX_PCIE_H_
#define _HALMAC_API_88XX_PCIE_H_
#include "../halmac_2_platform.h"
#include "../halmac_type.h"
#define LINK_CTRL2_REG_OFFSET 0xA0
#define GEN2_CTRL_OFFSET 0x80C
#define LINK_STATUS_REG_OFFSET 0x82
#define GEN1_SPEED 0x01
#define GEN2_SPEED 0x02
enum halmac_ret_status
halmac_init_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_deinit_pcie_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_pcie(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
u8 halmac_reg_read_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_8_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data);
u16 halmac_reg_read_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_16_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data);
u32 halmac_reg_read_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_32_pcie_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data);
enum halmac_ret_status halmac_cfg_tx_agg_align_pcie_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size);
#endif /* _HALMAC_API_88XX_PCIE_H_ */
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_sdio.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_88xx_cfg.h"
/**
* halmac_init_sdio_cfg_88xx() - init SDIO
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_SDIO_CFG);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_REG_READ_32(halmac_adapter, REG_SDIO_FREE_TXPG);
HALMAC_REG_WRITE_32(halmac_adapter, REG_SDIO_TX_CTRL, 0x00000000);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_deinit_sdio_cfg_88xx() - deinit SDIO
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_deinit_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEINIT_SDIO_CFG);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_rx_aggregation_88xx_sdio() - config rx aggregation
* @halmac_adapter : the adapter of halmac
* @halmac_rx_agg_mode
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_sdio(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg)
{
u8 value8;
u8 size = 0, timeout = 0, agg_enable = 0;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter,
HALMAC_API_CFG_RX_AGGREGATION);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
agg_enable = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_PQ_MAP);
switch (phalmac_rxagg_cfg->mode) {
case HALMAC_RX_AGG_MODE_NONE:
agg_enable &= ~(BIT_RXDMA_AGG_EN);
break;
case HALMAC_RX_AGG_MODE_DMA:
case HALMAC_RX_AGG_MODE_USB:
agg_enable |= BIT_RXDMA_AGG_EN;
break;
default:
pr_err("halmac_cfg_rx_aggregation_88xx_usb switch case not support\n");
agg_enable &= ~BIT_RXDMA_AGG_EN;
break;
}
if (!phalmac_rxagg_cfg->threshold.drv_define) {
size = 0xFF;
timeout = 0x01;
} else {
size = phalmac_rxagg_cfg->threshold.size;
timeout = phalmac_rxagg_cfg->threshold.timeout;
}
HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_PQ_MAP, agg_enable);
HALMAC_REG_WRITE_16(halmac_adapter, REG_RXDMA_AGG_PG_TH,
(u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO)));
value8 = HALMAC_REG_READ_8(halmac_adapter, REG_RXDMA_MODE);
if ((agg_enable & BIT_RXDMA_AGG_EN) != 0)
HALMAC_REG_WRITE_8(halmac_adapter, REG_RXDMA_MODE,
value8 | BIT_DMA_MODE);
else
HALMAC_REG_WRITE_8(halmac_adapter, REG_RXDMA_MODE,
value8 & ~(BIT_DMA_MODE));
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_8_sdio_88xx() - read 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u8 halmac_reg_read_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
u8 value8;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
value8 = PLATFORM_SDIO_CMD52_READ(driver_adapter, halmac_offset);
return value8;
}
/**
* halmac_reg_write_8_sdio_88xx() - write 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_16_sdio_88xx() - read 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u16 halmac_reg_read_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
union {
u16 word;
u8 byte[2];
__le16 le_word;
} value16 = {0x0000};
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
(halmac_offset & (2 - 1)) != 0 ||
halmac_adapter->sdio_cmd53_4byte ==
HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
halmac_adapter->sdio_cmd53_4byte ==
HALMAC_SDIO_CMD53_4BYTE_MODE_R) {
value16.byte[0] =
PLATFORM_SDIO_CMD52_READ(driver_adapter, halmac_offset);
value16.byte[1] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
halmac_offset + 1);
value16.word = le16_to_cpu(value16.le_word);
} else {
#if (PLATFORM_SD_CLK > HALMAC_SD_CLK_THRESHOLD_88XX)
if ((halmac_offset & 0xffffef00) == 0x00000000) {
value16.byte[0] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset);
value16.byte[1] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset + 1);
value16.word = le16_to_cpu(value16.word);
} else {
value16.word = PLATFORM_SDIO_CMD53_READ_16(
driver_adapter, halmac_offset);
}
#else
value16.word = PLATFORM_SDIO_CMD53_READ_16(driver_adapter,
halmac_offset);
#endif
}
return value16.word;
}
/**
* halmac_reg_write_16_sdio_88xx() - write 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
(halmac_offset & (2 - 1)) != 0 ||
halmac_adapter->sdio_cmd53_4byte ==
HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
halmac_adapter->sdio_cmd53_4byte ==
HALMAC_SDIO_CMD53_4BYTE_MODE_W) {
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset,
(u8)(halmac_data & 0xFF));
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 1,
(u8)((halmac_data & 0xFF00) >> 8));
} else {
PLATFORM_SDIO_CMD53_WRITE_16(driver_adapter, halmac_offset,
halmac_data);
}
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_32_sdio_88xx() - read 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32 halmac_reg_read_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
u32 halmac_offset_old = 0;
union {
u32 dword;
u8 byte[4];
__le32 le_dword;
} value32 = {0x00000000};
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
halmac_offset_old = halmac_offset;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
(halmac_offset & (4 - 1)) != 0) {
value32.byte[0] =
PLATFORM_SDIO_CMD52_READ(driver_adapter, halmac_offset);
value32.byte[1] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
halmac_offset + 1);
value32.byte[2] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
halmac_offset + 2);
value32.byte[3] = PLATFORM_SDIO_CMD52_READ(driver_adapter,
halmac_offset + 3);
value32.dword = le32_to_cpu(value32.le_dword);
} else {
#if (PLATFORM_SD_CLK > HALMAC_SD_CLK_THRESHOLD_88XX)
if ((halmac_offset_old & 0xffffef00) == 0x00000000) {
value32.byte[0] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset);
value32.byte[1] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset + 1);
value32.byte[2] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset + 2);
value32.byte[3] = PLATFORM_SDIO_CMD52_READ(
driver_adapter, halmac_offset + 3);
value32.dword = le32_to_cpu(value32.dword);
} else {
value32.dword = PLATFORM_SDIO_CMD53_READ_32(
driver_adapter, halmac_offset);
}
#else
value32.dword = PLATFORM_SDIO_CMD53_READ_32(driver_adapter,
halmac_offset);
#endif
}
return value32.dword;
}
/**
* halmac_reg_write_32_sdio_88xx() - write 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF ||
(halmac_offset & (4 - 1)) != 0) {
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset,
(u8)(halmac_data & 0xFF));
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 1,
(u8)((halmac_data & 0xFF00) >> 8));
PLATFORM_SDIO_CMD52_WRITE(driver_adapter, halmac_offset + 2,
(u8)((halmac_data & 0xFF0000) >> 16));
PLATFORM_SDIO_CMD52_WRITE(
driver_adapter, halmac_offset + 3,
(u8)((halmac_data & 0xFF000000) >> 24));
} else {
PLATFORM_SDIO_CMD53_WRITE_32(driver_adapter, halmac_offset,
halmac_data);
}
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_nbyte_sdio_88xx() - read n byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_size : register value size
* @halmac_data : register value
* Author : Soar
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u8 halmac_reg_read_nbyte_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_size,
u8 *halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
if ((halmac_offset & 0xFFFF0000) == 0) {
pr_err("halmac_offset error = 0x%x\n", halmac_offset);
return HALMAC_RET_FAIL;
}
status = halmac_convert_to_sdio_bus_offset_88xx(halmac_adapter,
&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
if (halmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_OFF) {
pr_err("halmac_state error = 0x%x\n",
halmac_adapter->halmac_state.mac_power);
return HALMAC_RET_FAIL;
}
PLATFORM_SDIO_CMD53_READ_N(driver_adapter, halmac_offset, halmac_size,
halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet
* @halmac_adapter : the adapter of halmac
* @halmac_buf : tx packet, include txdesc
* @halmac_size : tx packet size
* @pcmd53_addr : cmd53 addr value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_get_sdio_tx_addr_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr)
{
u32 four_byte_len;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_queue_select queue_sel;
enum halmac_dma_mapping dma_mapping;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_GET_SDIO_TX_ADDR);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
if (!halmac_buf) {
pr_err("halmac_buf is NULL!!\n");
return HALMAC_RET_DATA_BUF_NULL;
}
if (halmac_size == 0) {
pr_err("halmac_size is 0!!\n");
return HALMAC_RET_DATA_SIZE_INCORRECT;
}
queue_sel = (enum halmac_queue_select)GET_TX_DESC_QSEL(halmac_buf);
switch (queue_sel) {
case HALMAC_QUEUE_SELECT_VO:
case HALMAC_QUEUE_SELECT_VO_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
break;
case HALMAC_QUEUE_SELECT_VI:
case HALMAC_QUEUE_SELECT_VI_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
break;
case HALMAC_QUEUE_SELECT_BE:
case HALMAC_QUEUE_SELECT_BE_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
break;
case HALMAC_QUEUE_SELECT_BK:
case HALMAC_QUEUE_SELECT_BK_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
break;
case HALMAC_QUEUE_SELECT_MGNT:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
break;
case HALMAC_QUEUE_SELECT_HIGH:
case HALMAC_QUEUE_SELECT_BCN:
case HALMAC_QUEUE_SELECT_CMD:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
break;
default:
pr_err("Qsel is out of range\n");
return HALMAC_RET_QSEL_INCORRECT;
}
four_byte_len = (halmac_size >> 2) + ((halmac_size & (4 - 1)) ? 1 : 0);
switch (dma_mapping) {
case HALMAC_DMA_MAPPING_HIGH:
*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH;
break;
case HALMAC_DMA_MAPPING_NORMAL:
*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL;
break;
case HALMAC_DMA_MAPPING_LOW:
*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW;
break;
case HALMAC_DMA_MAPPING_EXTRA:
*pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA;
break;
default:
pr_err("DmaMapping is out of range\n");
return HALMAC_RET_DMA_MAP_INCORRECT;
}
*pcmd53_addr = (*pcmd53_addr << 13) |
(four_byte_len & HALMAC_SDIO_4BYTE_LEN_MASK);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_tx_agg_align_sdio_88xx() -config sdio bus tx agg alignment
* @halmac_adapter : the adapter of halmac
* @enable : function enable(1)/disable(0)
* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
* Author : Soar Tu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_cfg_tx_agg_align_sdio_88xx(struct halmac_adapter *halmac_adapter,
u8 enable, u16 align_size)
{
struct halmac_api *halmac_api;
void *driver_adapter = NULL;
u8 i, align_size_ok = 0;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
if ((align_size & 0xF000) != 0) {
pr_err("Align size is out of range\n");
return HALMAC_RET_FAIL;
}
for (i = 3; i <= 11; i++) {
if (align_size == 1 << i) {
align_size_ok = 1;
break;
}
}
if (align_size_ok == 0) {
pr_err("Align size is not 2^3 ~ 2^11\n");
return HALMAC_RET_FAIL;
}
/*Keep sdio tx agg alignment size for driver query*/
halmac_adapter->hw_config_info.tx_align_size = align_size;
if (enable)
HALMAC_REG_WRITE_16(halmac_adapter, REG_RQPN_CTRL_2,
0x8000 | align_size);
else
HALMAC_REG_WRITE_16(halmac_adapter, REG_RQPN_CTRL_2,
align_size);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
enum halmac_ret_status halmac_cfg_tx_agg_align_sdio_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size)
{
struct halmac_api *halmac_api;
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s not support\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_tx_allowed_sdio_88xx() - check tx status
* @halmac_adapter : the adapter of halmac
* @halmac_buf : tx packet, include txdesc
* @halmac_size : tx packet size, include txdesc
* Author : Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_tx_allowed_sdio_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size)
{
u8 *curr_packet;
u16 *curr_free_space;
u32 i, counter;
u32 tx_agg_num, packet_size = 0;
u32 tx_required_page_num, total_required_page_num = 0;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
void *driver_adapter = NULL;
enum halmac_dma_mapping dma_mapping;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_TX_ALLOWED_SDIO);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(halmac_buf);
curr_packet = halmac_buf;
tx_agg_num = tx_agg_num == 0 ? 1 : tx_agg_num;
switch ((enum halmac_queue_select)GET_TX_DESC_QSEL(curr_packet)) {
case HALMAC_QUEUE_SELECT_VO:
case HALMAC_QUEUE_SELECT_VO_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
break;
case HALMAC_QUEUE_SELECT_VI:
case HALMAC_QUEUE_SELECT_VI_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
break;
case HALMAC_QUEUE_SELECT_BE:
case HALMAC_QUEUE_SELECT_BE_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
break;
case HALMAC_QUEUE_SELECT_BK:
case HALMAC_QUEUE_SELECT_BK_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
break;
case HALMAC_QUEUE_SELECT_MGNT:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
break;
case HALMAC_QUEUE_SELECT_HIGH:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
break;
case HALMAC_QUEUE_SELECT_BCN:
case HALMAC_QUEUE_SELECT_CMD:
return HALMAC_RET_SUCCESS;
default:
pr_err("Qsel is out of range\n");
return HALMAC_RET_QSEL_INCORRECT;
}
switch (dma_mapping) {
case HALMAC_DMA_MAPPING_HIGH:
curr_free_space =
&halmac_adapter->sdio_free_space.high_queue_number;
break;
case HALMAC_DMA_MAPPING_NORMAL:
curr_free_space =
&halmac_adapter->sdio_free_space.normal_queue_number;
break;
case HALMAC_DMA_MAPPING_LOW:
curr_free_space =
&halmac_adapter->sdio_free_space.low_queue_number;
break;
case HALMAC_DMA_MAPPING_EXTRA:
curr_free_space =
&halmac_adapter->sdio_free_space.extra_queue_number;
break;
default:
pr_err("DmaMapping is out of range\n");
return HALMAC_RET_DMA_MAP_INCORRECT;
}
for (i = 0; i < tx_agg_num; i++) {
packet_size = GET_TX_DESC_TXPKTSIZE(curr_packet) +
GET_TX_DESC_OFFSET(curr_packet) +
(GET_TX_DESC_PKT_OFFSET(curr_packet) << 3);
tx_required_page_num =
(packet_size >>
halmac_adapter->hw_config_info.page_size_2_power) +
((packet_size &
(halmac_adapter->hw_config_info.page_size - 1)) ?
1 :
0);
total_required_page_num += tx_required_page_num;
packet_size = HALMAC_ALIGN(packet_size, 8);
curr_packet += packet_size;
}
counter = 10;
do {
if ((u32)(*curr_free_space +
halmac_adapter->sdio_free_space.public_queue_number) >
total_required_page_num) {
if (*curr_free_space >= total_required_page_num) {
*curr_free_space -=
(u16)total_required_page_num;
} else {
halmac_adapter->sdio_free_space
.public_queue_number -=
(u16)(total_required_page_num -
*curr_free_space);
*curr_free_space = 0;
}
status = halmac_check_oqt_88xx(halmac_adapter,
tx_agg_num, halmac_buf);
if (status != HALMAC_RET_SUCCESS)
return status;
break;
}
halmac_update_sdio_free_page_88xx(halmac_adapter);
counter--;
if (counter == 0)
return HALMAC_RET_FREE_SPACE_NOT_ENOUGH;
} while (1);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_indirect_32_sdio_88xx() - read MAC reg by SDIO reg
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : Soar
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32 halmac_reg_read_indirect_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
u8 rtemp;
u32 counter = 1000;
void *driver_adapter = NULL;
union {
u32 dword;
u8 byte[4];
} value32 = {0x00000000};
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
PLATFORM_SDIO_CMD53_WRITE_32(
driver_adapter,
(HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
(REG_SDIO_INDIRECT_REG_CFG & HALMAC_SDIO_LOCAL_MSK),
halmac_offset | BIT(19) | BIT(17));
do {
rtemp = PLATFORM_SDIO_CMD52_READ(
driver_adapter,
(HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
((REG_SDIO_INDIRECT_REG_CFG + 2) &
HALMAC_SDIO_LOCAL_MSK));
counter--;
} while ((rtemp & BIT(4)) != 0 && counter > 0);
value32.dword = PLATFORM_SDIO_CMD53_READ_32(
driver_adapter,
(HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
(REG_SDIO_INDIRECT_REG_DATA & HALMAC_SDIO_LOCAL_MSK));
return value32.dword;
}
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_sdio.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_88XX_SDIO_H_
#define _HALMAC_API_88XX_SDIO_H_
#include "../halmac_2_platform.h"
#include "../halmac_type.h"
enum halmac_ret_status
halmac_init_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_deinit_sdio_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_sdio(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
u8 halmac_reg_read_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_8_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data);
u16 halmac_reg_read_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_16_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data);
u32 halmac_reg_read_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data);
enum halmac_ret_status
halmac_get_sdio_tx_addr_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr);
enum halmac_ret_status
halmac_cfg_tx_agg_align_sdio_88xx(struct halmac_adapter *halmac_adapter,
u8 enable, u16 align_size);
enum halmac_ret_status halmac_cfg_tx_agg_align_sdio_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size);
enum halmac_ret_status
halmac_tx_allowed_sdio_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size);
u32 halmac_reg_read_indirect_32_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
u8 halmac_reg_read_nbyte_sdio_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_size,
u8 *halmac_data);
#endif /* _HALMAC_API_88XX_SDIO_H_ */
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_usb.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_88xx_cfg.h"
/**
* halmac_init_usb_cfg_88xx() - init USB
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_usb_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
u8 value8 = 0;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_INIT_USB_CFG);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
value8 |= (BIT_DMA_MODE |
(0x3 << BIT_SHIFT_BURST_CNT)); /* burst number = 4 */
if (PLATFORM_REG_READ_8(driver_adapter, REG_SYS_CFG2 + 3) ==
0x20) { /* usb3.0 */
value8 |= (HALMAC_USB_BURST_SIZE_3_0 << BIT_SHIFT_BURST_SIZE);
} else {
if ((PLATFORM_REG_READ_8(driver_adapter, REG_USB_USBSTAT) &
0x3) == 0x1) /* usb2.0 */
value8 |= HALMAC_USB_BURST_SIZE_2_0_HSPEED
<< BIT_SHIFT_BURST_SIZE;
else /* usb1.1 */
value8 |= HALMAC_USB_BURST_SIZE_2_0_FSPEED
<< BIT_SHIFT_BURST_SIZE;
}
PLATFORM_REG_WRITE_8(driver_adapter, REG_RXDMA_MODE, value8);
PLATFORM_REG_WRITE_16(
driver_adapter, REG_TXDMA_OFFSET_CHK,
PLATFORM_REG_READ_16(driver_adapter, REG_TXDMA_OFFSET_CHK) |
BIT_DROP_DATA_EN);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_deinit_usb_cfg_88xx() - deinit USB
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_deinit_usb_cfg_88xx(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_DEINIT_USB_CFG);
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_rx_aggregation_88xx_usb() - config rx aggregation
* @halmac_adapter : the adapter of halmac
* @halmac_rx_agg_mode
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_usb(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg)
{
u8 dma_usb_agg;
u8 size = 0, timeout = 0, agg_enable = 0;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter,
HALMAC_API_CFG_RX_AGGREGATION);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
dma_usb_agg =
HALMAC_REG_READ_8(halmac_adapter, REG_RXDMA_AGG_PG_TH + 3);
agg_enable = HALMAC_REG_READ_8(halmac_adapter, REG_TXDMA_PQ_MAP);
switch (phalmac_rxagg_cfg->mode) {
case HALMAC_RX_AGG_MODE_NONE:
agg_enable &= ~BIT_RXDMA_AGG_EN;
break;
case HALMAC_RX_AGG_MODE_DMA:
agg_enable |= BIT_RXDMA_AGG_EN;
dma_usb_agg |= BIT(7);
break;
case HALMAC_RX_AGG_MODE_USB:
agg_enable |= BIT_RXDMA_AGG_EN;
dma_usb_agg &= ~BIT(7);
break;
default:
pr_err("%s switch case not support\n", __func__);
agg_enable &= ~BIT_RXDMA_AGG_EN;
break;
}
if (!phalmac_rxagg_cfg->threshold.drv_define) {
if (PLATFORM_REG_READ_8(driver_adapter, REG_SYS_CFG2 + 3) ==
0x20) {
/* usb3.0 */
size = 0x5;
timeout = 0xA;
} else {
/* usb2.0 */
size = 0x5;
timeout = 0x20;
}
} else {
size = phalmac_rxagg_cfg->threshold.size;
timeout = phalmac_rxagg_cfg->threshold.timeout;
}
HALMAC_REG_WRITE_8(halmac_adapter, REG_TXDMA_PQ_MAP, agg_enable);
HALMAC_REG_WRITE_8(halmac_adapter, REG_RXDMA_AGG_PG_TH + 3,
dma_usb_agg);
HALMAC_REG_WRITE_16(halmac_adapter, REG_RXDMA_AGG_PG_TH,
(u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO)));
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_8_usb_88xx() - read 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u8 halmac_reg_read_8_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
u8 value8;
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
value8 = PLATFORM_REG_READ_8(driver_adapter, halmac_offset);
return value8;
}
/**
* halmac_reg_write_8_usb_88xx() - write 1byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_8_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_8(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_16_usb_88xx() - read 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u16 halmac_reg_read_16_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
union {
u16 word;
u8 byte[2];
} value16 = {0x0000};
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
value16.word = PLATFORM_REG_READ_16(driver_adapter, halmac_offset);
return value16.word;
}
/**
* halmac_reg_write_16_usb_88xx() - write 2byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_16_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_16(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_reg_read_32_usb_88xx() - read 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
u32 halmac_reg_read_32_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
union {
u32 dword;
u8 byte[4];
} value32 = {0x00000000};
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
value32.dword = PLATFORM_REG_READ_32(driver_adapter, halmac_offset);
return value32.dword;
}
/**
* halmac_reg_write_32_usb_88xx() - write 4byte register
* @halmac_adapter : the adapter of halmac
* @halmac_offset : register offset
* @halmac_data : register value
* Author : KaiYuan Chang/Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_reg_write_32_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
PLATFORM_REG_WRITE_32(driver_adapter, halmac_offset, halmac_data);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_set_bulkout_num_usb_88xx() - inform bulk-out num
* @halmac_adapter : the adapter of halmac
* @bulkout_num : usb bulk-out number
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_set_bulkout_num_88xx(struct halmac_adapter *halmac_adapter,
u8 bulkout_num)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_SET_BULKOUT_NUM);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
halmac_adapter->halmac_bulkout_num = bulkout_num;
return HALMAC_RET_SUCCESS;
}
/**
* halmac_get_usb_bulkout_id_usb_88xx() - get bulk out id for the TX packet
* @halmac_adapter : the adapter of halmac
* @halmac_buf : tx packet, include txdesc
* @halmac_size : tx packet size
* @bulkout_id : usb bulk-out id
* Author : KaiYuan Chang
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_get_usb_bulkout_id_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id)
{
void *driver_adapter = NULL;
struct halmac_api *halmac_api;
enum halmac_queue_select queue_sel;
enum halmac_dma_mapping dma_mapping;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter,
HALMAC_API_GET_USB_BULKOUT_ID);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
if (!halmac_buf) {
pr_err("halmac_buf is NULL!!\n");
return HALMAC_RET_DATA_BUF_NULL;
}
if (halmac_size == 0) {
pr_err("halmac_size is 0!!\n");
return HALMAC_RET_DATA_SIZE_INCORRECT;
}
queue_sel = (enum halmac_queue_select)GET_TX_DESC_QSEL(halmac_buf);
switch (queue_sel) {
case HALMAC_QUEUE_SELECT_VO:
case HALMAC_QUEUE_SELECT_VO_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
break;
case HALMAC_QUEUE_SELECT_VI:
case HALMAC_QUEUE_SELECT_VI_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
break;
case HALMAC_QUEUE_SELECT_BE:
case HALMAC_QUEUE_SELECT_BE_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
break;
case HALMAC_QUEUE_SELECT_BK:
case HALMAC_QUEUE_SELECT_BK_V2:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
break;
case HALMAC_QUEUE_SELECT_MGNT:
dma_mapping =
halmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
break;
case HALMAC_QUEUE_SELECT_HIGH:
case HALMAC_QUEUE_SELECT_BCN:
case HALMAC_QUEUE_SELECT_CMD:
dma_mapping = HALMAC_DMA_MAPPING_HIGH;
break;
default:
pr_err("Qsel is out of range\n");
return HALMAC_RET_QSEL_INCORRECT;
}
switch (dma_mapping) {
case HALMAC_DMA_MAPPING_HIGH:
*bulkout_id = 0;
break;
case HALMAC_DMA_MAPPING_NORMAL:
*bulkout_id = 1;
break;
case HALMAC_DMA_MAPPING_LOW:
*bulkout_id = 2;
break;
case HALMAC_DMA_MAPPING_EXTRA:
*bulkout_id = 3;
break;
default:
pr_err("DmaMapping is out of range\n");
return HALMAC_RET_DMA_MAP_INCORRECT;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_cfg_tx_agg_align_usb_88xx() -config sdio bus tx agg alignment
* @halmac_adapter : the adapter of halmac
* @enable : function enable(1)/disable(0)
* @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
* Author : Soar Tu
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_cfg_tx_agg_align_usb_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size)
{
struct halmac_api *halmac_api;
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
if (halmac_api_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_API_INVALID;
halmac_api_record_id_88xx(halmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
driver_adapter = halmac_adapter->driver_adapter;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s not support\n", __func__);
HALMAC_RT_TRACE(
driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s <==========\n", __func__);
return HALMAC_RET_SUCCESS;
}
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_api_88xx_usb.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_88XX_USB_H_
#define _HALMAC_API_88XX_USB_H_
#include "../halmac_2_platform.h"
#include "../halmac_type.h"
enum halmac_ret_status
halmac_init_usb_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_deinit_usb_cfg_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_cfg_rx_aggregation_88xx_usb(struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
u8 halmac_reg_read_8_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_8_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u8 halmac_data);
u16 halmac_reg_read_16_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_16_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u16 halmac_data);
u32 halmac_reg_read_32_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status
halmac_reg_write_32_usb_88xx(struct halmac_adapter *halmac_adapter,
u32 halmac_offset, u32 halmac_data);
enum halmac_ret_status
halmac_set_bulkout_num_88xx(struct halmac_adapter *halmac_adapter,
u8 bulkout_num);
enum halmac_ret_status
halmac_get_usb_bulkout_id_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id);
enum halmac_ret_status halmac_cfg_tx_agg_align_usb_not_support_88xx(
struct halmac_adapter *halmac_adapter, u8 enable, u16 align_size);
#endif /* _HALMAC_API_88XX_USB_H_ */
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_func_88xx.c 0 → 100644
View file @ 938a0447
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_func_88xx.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_FUNC_88XX_H_
#define _HALMAC_FUNC_88XX_H_
#include "../halmac_type.h"
void halmac_init_offload_feature_state_machine_88xx(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_send_h2c_pkt_88xx(struct halmac_adapter *halmac_adapter, u8 *hal_buff,
u32 size, bool ack);
enum halmac_ret_status
halmac_download_rsvd_page_88xx(struct halmac_adapter *halmac_adapter,
u8 *hal_buf, u32 size);
enum halmac_ret_status
halmac_set_h2c_header_88xx(struct halmac_adapter *halmac_adapter,
u8 *hal_h2c_hdr, u16 *seq, bool ack);
enum halmac_ret_status halmac_set_fw_offload_h2c_header_88xx(
struct halmac_adapter *halmac_adapter, u8 *hal_h2c_hdr,
struct halmac_h2c_header_info *h2c_header_info, u16 *seq_num);
enum halmac_ret_status
halmac_dump_efuse_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
halmac_func_read_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
u32 size, u8 *efuse_map);
enum halmac_ret_status
halmac_func_write_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
u8 value);
enum halmac_ret_status
halmac_func_switch_efuse_bank_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_efuse_bank efuse_bank);
enum halmac_ret_status
halmac_read_logical_efuse_map_88xx(struct halmac_adapter *halmac_adapter,
u8 *map);
enum halmac_ret_status
halmac_func_write_logical_efuse_88xx(struct halmac_adapter *halmac_adapter,
u32 offset, u8 value);
enum halmac_ret_status
halmac_func_pg_efuse_by_map_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_pg_efuse_info *pg_efuse_info,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status
halmac_eeprom_parser_88xx(struct halmac_adapter *halmac_adapter,
u8 *physical_efuse_map, u8 *logical_efuse_map);
enum halmac_ret_status
halmac_read_hw_efuse_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
u32 size, u8 *efuse_map);
enum halmac_ret_status
halmac_dlfw_to_mem_88xx(struct halmac_adapter *halmac_adapter, u8 *ram_code,
u32 dest, u32 code_size);
enum halmac_ret_status
halmac_send_fwpkt_88xx(struct halmac_adapter *halmac_adapter, u8 *ram_code,
u32 code_size);
enum halmac_ret_status
halmac_iddma_dlfw_88xx(struct halmac_adapter *halmac_adapter, u32 source,
u32 dest, u32 length, u8 first);
enum halmac_ret_status
halmac_check_fw_chksum_88xx(struct halmac_adapter *halmac_adapter,
u32 memory_address);
enum halmac_ret_status
halmac_dlfw_end_flow_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_free_dl_fw_end_flow_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_pwr_seq_parser_88xx(struct halmac_adapter *halmac_adapter, u8 cut,
u8 fab, u8 intf,
struct halmac_wl_pwr_cfg_ **pp_pwr_seq_cfg
);
enum halmac_ret_status
halmac_get_h2c_buff_free_space_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_send_h2c_set_pwr_mode_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_fwlps_option *hal_fw_lps_opt);
enum halmac_ret_status
halmac_func_send_original_h2c_88xx(struct halmac_adapter *halmac_adapter,
u8 *original_h2c, u16 *seq, u8 ack);
enum halmac_ret_status
halmac_media_status_rpt_88xx(struct halmac_adapter *halmac_adapter, u8 op_mode,
u8 mac_id_ind, u8 mac_id, u8 mac_id_end);
enum halmac_ret_status halmac_send_h2c_update_datapack_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_data_type halmac_data_type,
struct halmac_phy_parameter_info *para_info);
enum halmac_ret_status
halmac_send_h2c_run_datapack_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_data_type halmac_data_type);
enum halmac_ret_status
halmac_send_bt_coex_cmd_88xx(struct halmac_adapter *halmac_adapter, u8 *bt_buf,
u32 bt_size, u8 ack);
enum halmac_ret_status
halmac_func_ctrl_ch_switch_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ch_switch_option *cs_option);
enum halmac_ret_status
halmac_func_send_general_info_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_general_info *general_info);
enum halmac_ret_status
halmac_send_h2c_ps_tuning_para_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_parse_c2h_packet_88xx(struct halmac_adapter *halmac_adapter,
u8 *halmac_buf, u32 halmac_size);
enum halmac_ret_status
halmac_send_h2c_update_packet_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_packet_id pkt_id, u8 *pkt,
u32 pkt_size);
enum halmac_ret_status
halmac_send_h2c_phy_parameter_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_phy_parameter_info *para_info,
bool full_fifo);
enum halmac_ret_status
halmac_dump_physical_efuse_fw_88xx(struct halmac_adapter *halmac_adapter,
u32 offset, u32 size, u8 *efuse_map);
enum halmac_ret_status halmac_send_h2c_update_bcn_parse_info_88xx(
struct halmac_adapter *halmac_adapter,
struct halmac_bcn_ie_info *bcn_ie_info);
enum halmac_ret_status
halmac_convert_to_sdio_bus_offset_88xx(struct halmac_adapter *halmac_adapter,
u32 *halmac_offset);
enum halmac_ret_status
halmac_update_sdio_free_page_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_update_oqt_free_space_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_efuse_cmd_construct_state
halmac_query_efuse_curr_state_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_transition_efuse_state_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_efuse_cmd_construct_state dest_state);
enum halmac_cfg_para_cmd_construct_state
halmac_query_cfg_para_curr_state_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_transition_cfg_para_state_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cfg_para_cmd_construct_state dest_state);
enum halmac_scan_cmd_construct_state
halmac_query_scan_curr_state_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_transition_scan_state_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_scan_cmd_construct_state dest_state);
enum halmac_ret_status halmac_query_cfg_para_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status halmac_query_dump_physical_efuse_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status halmac_query_dump_logical_efuse_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status halmac_query_channel_switch_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status halmac_query_update_packet_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status
halmac_query_iqk_status_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status,
u8 *data, u32 *size);
enum halmac_ret_status halmac_query_power_tracking_status_88xx(
struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status, u8 *data, u32 *size);
enum halmac_ret_status
halmac_query_psd_status_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_cmd_process_status *process_status,
u8 *data, u32 *size);
enum halmac_ret_status
halmac_verify_io_88xx(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status
halmac_verify_send_rsvd_page_88xx(struct halmac_adapter *halmac_adapter);
void halmac_power_save_cb_88xx(void *cb_data);
enum halmac_ret_status
halmac_buffer_read_88xx(struct halmac_adapter *halmac_adapter, u32 offset,
u32 size, enum hal_fifo_sel halmac_fifo_sel,
u8 *fifo_map);
void halmac_restore_mac_register_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_restore_info *restore_info,
u32 restore_num);
void halmac_api_record_id_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_api_id api_id);
enum halmac_ret_status
halmac_set_usb_mode_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_usb_mode usb_mode);
void halmac_enable_bb_rf_88xx(struct halmac_adapter *halmac_adapter, u8 enable);
void halmac_config_sdio_tx_page_threshold_88xx(
struct halmac_adapter *halmac_adapter,
struct halmac_tx_page_threshold_info *threshold_info);
enum halmac_ret_status
halmac_rqpn_parser_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode,
struct halmac_rqpn_ *pwr_seq_cfg);
enum halmac_ret_status
halmac_check_oqt_88xx(struct halmac_adapter *halmac_adapter, u32 tx_agg_num,
u8 *halmac_buf);
enum halmac_ret_status
halmac_pg_num_parser_88xx(struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode halmac_trx_mode,
struct halmac_pg_num_ *pg_num_table);
enum halmac_ret_status
halmac_parse_intf_phy_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_intf_phy_para_ *intf_phy_para,
enum halmac_intf_phy_platform platform,
enum hal_intf_phy intf_phy);
enum halmac_ret_status
halmac_dbi_write32_88xx(struct halmac_adapter *halmac_adapter, u16 addr,
u32 data);
u32 halmac_dbi_read32_88xx(struct halmac_adapter *halmac_adapter, u16 addr);
enum halmac_ret_status
halmac_dbi_write8_88xx(struct halmac_adapter *halmac_adapter, u16 addr,
u8 data);
u8 halmac_dbi_read8_88xx(struct halmac_adapter *halmac_adapter, u16 addr);
u16 halmac_mdio_read_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
u8 speed
);
enum halmac_ret_status
halmac_mdio_write_88xx(struct halmac_adapter *halmac_adapter, u8 addr, u16 data,
u8 speed);
void halmac_config_ampdu_88xx(struct halmac_adapter *halmac_adapter,
struct halmac_ampdu_config *ampdu_config);
enum halmac_ret_status
halmac_usbphy_write_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
u16 data, u8 speed);
u16 halmac_usbphy_read_88xx(struct halmac_adapter *halmac_adapter, u8 addr,
u8 speed);
#endif /* _HALMAC_FUNC_88XX_H_ */
drivers/staging/rtlwifi/halmac/halmac_api.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_2_platform.h"
#include "halmac_type.h"
#include "halmac_88xx/halmac_api_88xx.h"
#include "halmac_88xx/halmac_88xx_cfg.h"
#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h"
static enum halmac_ret_status
halmac_check_platform_api(void *driver_adapter,
enum halmac_interface halmac_interface,
struct halmac_platform_api *halmac_platform_api)
{
void *adapter_local = NULL;
adapter_local = driver_adapter;
if (!halmac_platform_api)
return HALMAC_RET_PLATFORM_API_NULL;
if (halmac_interface == HALMAC_INTERFACE_SDIO) {
if (!halmac_platform_api->SDIO_CMD52_READ) {
pr_err("(!halmac_platform_api->SDIO_CMD52_READ)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_READ_8) {
pr_err("(!halmac_platform_api->SDIO_CMD53_READ_8)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_READ_16) {
pr_err("(!halmac_platform_api->SDIO_CMD53_READ_16)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_READ_32) {
pr_err("(!halmac_platform_api->SDIO_CMD53_READ_32)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_READ_N) {
pr_err("(!halmac_platform_api->SDIO_CMD53_READ_N)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD52_WRITE) {
pr_err("(!halmac_platform_api->SDIO_CMD52_WRITE)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_WRITE_8) {
pr_err("(!halmac_platform_api->SDIO_CMD53_WRITE_8)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_WRITE_16) {
pr_err("(!halmac_platform_api->SDIO_CMD53_WRITE_16)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->SDIO_CMD53_WRITE_32) {
pr_err("(!halmac_platform_api->SDIO_CMD53_WRITE_32)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
}
if (halmac_interface == HALMAC_INTERFACE_USB ||
halmac_interface == HALMAC_INTERFACE_PCIE) {
if (!halmac_platform_api->REG_READ_8) {
pr_err("(!halmac_platform_api->REG_READ_8)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->REG_READ_16) {
pr_err("(!halmac_platform_api->REG_READ_16)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->REG_READ_32) {
pr_err("(!halmac_platform_api->REG_READ_32)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->REG_WRITE_8) {
pr_err("(!halmac_platform_api->REG_WRITE_8)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->REG_WRITE_16) {
pr_err("(!halmac_platform_api->REG_WRITE_16)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
if (!halmac_platform_api->REG_WRITE_32) {
pr_err("(!halmac_platform_api->REG_WRITE_32)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
}
if (!halmac_platform_api->EVENT_INDICATION) {
pr_err("(!halmac_platform_api->EVENT_INDICATION)\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
halmac_convert_to_sdio_bus_offset(u32 *halmac_offset)
{
switch ((*halmac_offset) & 0xFFFF0000) {
case WLAN_IOREG_OFFSET:
*halmac_offset = (HALMAC_SDIO_CMD_ADDR_MAC_REG << 13) |
(*halmac_offset & HALMAC_WLAN_MAC_REG_MSK);
break;
case SDIO_LOCAL_OFFSET:
*halmac_offset = (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) |
(*halmac_offset & HALMAC_SDIO_LOCAL_MSK);
break;
default:
*halmac_offset = 0xFFFFFFFF;
return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
}
return HALMAC_RET_SUCCESS;
}
static u8
platform_reg_read_8_sdio(void *driver_adapter,
struct halmac_platform_api *halmac_platform_api,
u32 offset)
{
u8 value8;
u32 halmac_offset = offset;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset(&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("%s error = %x\n", __func__, status);
return status;
}
value8 = halmac_platform_api->SDIO_CMD52_READ(driver_adapter,
halmac_offset);
return value8;
}
static enum halmac_ret_status
platform_reg_write_8_sdio(void *driver_adapter,
struct halmac_platform_api *halmac_platform_api,
u32 offset, u8 data)
{
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
u32 halmac_offset = offset;
if ((halmac_offset & 0xFFFF0000) == 0)
halmac_offset |= WLAN_IOREG_OFFSET;
status = halmac_convert_to_sdio_bus_offset(&halmac_offset);
if (status != HALMAC_RET_SUCCESS) {
pr_err("halmac_reg_write_8_sdio_88xx error = %x\n", status);
return status;
}
halmac_platform_api->SDIO_CMD52_WRITE(driver_adapter, halmac_offset,
data);
return HALMAC_RET_SUCCESS;
}
static enum halmac_ret_status
halmac_get_chip_info(void *driver_adapter,
struct halmac_platform_api *halmac_platform_api,
enum halmac_interface halmac_interface,
struct halmac_adapter *halmac_adapter)
{
struct halmac_api *halmac_api = (struct halmac_api *)NULL;
u8 chip_id, chip_version;
u32 polling_count;
halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
/* Get Chip_id and Chip_version */
if (halmac_adapter->halmac_interface == HALMAC_INTERFACE_SDIO) {
platform_reg_write_8_sdio(
driver_adapter, halmac_platform_api, REG_SDIO_HSUS_CTRL,
platform_reg_read_8_sdio(driver_adapter,
halmac_platform_api,
REG_SDIO_HSUS_CTRL) &
~(BIT(0)));
polling_count = 10000;
while (!(platform_reg_read_8_sdio(driver_adapter,
halmac_platform_api,
REG_SDIO_HSUS_CTRL) &
0x02)) {
polling_count--;
if (polling_count == 0)
return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
}
chip_id = platform_reg_read_8_sdio(
driver_adapter, halmac_platform_api, REG_SYS_CFG2);
chip_version = platform_reg_read_8_sdio(driver_adapter,
halmac_platform_api,
REG_SYS_CFG1 + 1) >>
4;
} else {
chip_id = halmac_platform_api->REG_READ_8(driver_adapter,
REG_SYS_CFG2);
chip_version = halmac_platform_api->REG_READ_8(
driver_adapter, REG_SYS_CFG1 + 1) >>
4;
}
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"[TRACE]Chip id : 0x%X\n", chip_id);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"[TRACE]Chip version : 0x%X\n", chip_version);
halmac_adapter->chip_version = (enum halmac_chip_ver)chip_version;
if (chip_id == HALMAC_CHIP_ID_HW_DEF_8822B)
halmac_adapter->chip_id = HALMAC_CHIP_ID_8822B;
else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8821C)
halmac_adapter->chip_id = HALMAC_CHIP_ID_8821C;
else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8814B)
halmac_adapter->chip_id = HALMAC_CHIP_ID_8814B;
else if (chip_id == HALMAC_CHIP_ID_HW_DEF_8197F)
halmac_adapter->chip_id = HALMAC_CHIP_ID_8197F;
else
halmac_adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE;
if (halmac_adapter->chip_id == HALMAC_CHIP_ID_UNDEFINE)
return HALMAC_RET_CHIP_NOT_SUPPORT;
return HALMAC_RET_SUCCESS;
}
/**
* halmac_init_adapter() - init halmac_adapter
* @driver_adapter : the adapter of caller
* @halmac_platform_api : the platform APIs which is used in halmac APIs
* @halmac_interface : bus interface
* @pp_halmac_adapter : the adapter of halmac
* @pp_halmac_api : the function pointer of APIs, caller shall call APIs by
* function pointer
* Author : KaiYuan Chang / Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_init_adapter(void *driver_adapter,
struct halmac_platform_api *halmac_platform_api,
enum halmac_interface halmac_interface,
struct halmac_adapter **pp_halmac_adapter,
struct halmac_api **pp_halmac_api)
{
struct halmac_adapter *halmac_adapter = (struct halmac_adapter *)NULL;
enum halmac_ret_status status = HALMAC_RET_SUCCESS;
union {
u32 i;
u8 x[4];
} ENDIAN_CHECK = {0x01000000};
status = halmac_check_platform_api(driver_adapter, halmac_interface,
halmac_platform_api);
if (status != HALMAC_RET_SUCCESS)
return status;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
HALMAC_SVN_VER "\n");
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"HALMAC_MAJOR_VER = %x\n", HALMAC_MAJOR_VER);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"HALMAC_PROTOTYPE_VER = %x\n", HALMAC_PROTOTYPE_VER);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"HALMAC_MINOR_VER = %x\n", HALMAC_MINOR_VER);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"HALMAC_PATCH_VER = %x\n", HALMAC_PATCH_VER);
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_init_adapter_88xx ==========>\n");
/* Check endian setting - Little endian : 1, Big endian : 0*/
if (ENDIAN_CHECK.x[0] == HALMAC_SYSTEM_ENDIAN) {
pr_err("Endian setting Err!!\n");
return HALMAC_RET_ENDIAN_ERR;
}
halmac_adapter = kzalloc(sizeof(*halmac_adapter), GFP_KERNEL);
if (!halmac_adapter) {
/* out of memory */
return HALMAC_RET_MALLOC_FAIL;
}
/* return halmac adapter address to caller */
*pp_halmac_adapter = halmac_adapter;
/* Record caller info */
halmac_adapter->halmac_platform_api = halmac_platform_api;
halmac_adapter->driver_adapter = driver_adapter;
halmac_interface = halmac_interface == HALMAC_INTERFACE_AXI ?
HALMAC_INTERFACE_PCIE :
halmac_interface;
halmac_adapter->halmac_interface = halmac_interface;
spin_lock_init(&halmac_adapter->efuse_lock);
spin_lock_init(&halmac_adapter->h2c_seq_lock);
/*Get Chip*/
if (halmac_get_chip_info(driver_adapter, halmac_platform_api,
halmac_interface,
halmac_adapter) != HALMAC_RET_SUCCESS) {
pr_err("HALMAC_RET_CHIP_NOT_SUPPORT\n");
return HALMAC_RET_CHIP_NOT_SUPPORT;
}
/* Assign function pointer to halmac API */
halmac_init_adapter_para_88xx(halmac_adapter);
status = halmac_mount_api_88xx(halmac_adapter);
/* Return halmac API function pointer */
*pp_halmac_api = (struct halmac_api *)halmac_adapter->halmac_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"halmac_init_adapter_88xx <==========\n");
return status;
}
/**
* halmac_halt_api() - stop halmac_api action
* @halmac_adapter : the adapter of halmac
* Author : Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_halt_api(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
struct halmac_platform_api *halmac_platform_api =
(struct halmac_platform_api *)NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
halmac_platform_api = halmac_adapter->halmac_platform_api;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
halmac_adapter->halmac_state.api_state = HALMAC_API_STATE_HALT;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"%s ==========>\n", __func__);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_deinit_adapter() - deinit halmac adapter
* @halmac_adapter : the adapter of halmac
* Author : KaiYuan Chang / Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status
halmac_deinit_adapter(struct halmac_adapter *halmac_adapter)
{
void *driver_adapter = NULL;
if (halmac_adapter_validate(halmac_adapter) != HALMAC_RET_SUCCESS)
return HALMAC_RET_ADAPTER_INVALID;
driver_adapter = halmac_adapter->driver_adapter;
HALMAC_RT_TRACE(driver_adapter, HALMAC_MSG_INIT, DBG_DMESG,
"[TRACE]halmac_deinit_adapter_88xx ==========>\n");
kfree(halmac_adapter->hal_efuse_map);
halmac_adapter->hal_efuse_map = (u8 *)NULL;
kfree(halmac_adapter->halmac_state.psd_set.data);
halmac_adapter->halmac_state.psd_set.data = (u8 *)NULL;
kfree(halmac_adapter->halmac_api);
halmac_adapter->halmac_api = NULL;
halmac_adapter->hal_adapter_backup = NULL;
kfree(halmac_adapter);
return HALMAC_RET_SUCCESS;
}
/**
* halmac_get_version() - get HALMAC version
* @version : return version of major, prototype and minor information
* Author : KaiYuan Chang / Ivan Lin
* Return : enum halmac_ret_status
* More details of status code can be found in prototype document
*/
enum halmac_ret_status halmac_get_version(struct halmac_ver *version)
{
version->major_ver = (u8)HALMAC_MAJOR_VER;
version->prototype_ver = (u8)HALMAC_PROTOTYPE_VER;
version->minor_ver = (u8)HALMAC_MINOR_VER;
return HALMAC_RET_SUCCESS;
}
drivers/staging/rtlwifi/halmac/halmac_api.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_API_H_
#define _HALMAC_API_H_
#define HALMAC_SVN_VER "13348M"
#define HALMAC_MAJOR_VER 0x0001 /* major version, ver_1 for async_api */
/* For halmac_api num change or prototype change, increment prototype version.
* Otherwise, increase minor version
*/
#define HALMAC_PROTOTYPE_VER 0x0003 /* prototype version */
#define HALMAC_MINOR_VER 0x0005 /* minor version */
#define HALMAC_PATCH_VER 0x0000 /* patch version */
#include "halmac_2_platform.h"
#include "halmac_type.h"
#include "halmac_usb_reg.h"
#include "halmac_sdio_reg.h"
#include "halmac_pcie_reg.h"
#include "halmac_bit2.h"
#include "halmac_reg2.h"
#include "halmac_tx_desc_nic.h"
#include "halmac_rx_desc_nic.h"
#include "halmac_tx_bd_nic.h"
#include "halmac_rx_bd_nic.h"
#include "halmac_fw_offload_c2h_nic.h"
#include "halmac_fw_offload_h2c_nic.h"
#include "halmac_h2c_extra_info_nic.h"
#include "halmac_original_c2h_nic.h"
#include "halmac_original_h2c_nic.h"
#include "halmac_tx_desc_chip.h"
#include "halmac_rx_desc_chip.h"
#include "halmac_tx_bd_chip.h"
#include "halmac_rx_bd_chip.h"
#include "halmac_88xx/halmac_88xx_cfg.h"
#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h"
#include "halmac_reg_8822b.h"
#include "halmac_bit_8822b.h"
enum halmac_ret_status
halmac_init_adapter(void *driver_adapter,
struct halmac_platform_api *halmac_platform_api,
enum halmac_interface halmac_interface,
struct halmac_adapter **pp_halmac_adapter,
struct halmac_api **pp_halmac_api);
enum halmac_ret_status
halmac_deinit_adapter(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_halt_api(struct halmac_adapter *halmac_adapter);
enum halmac_ret_status halmac_get_version(struct halmac_ver *version);
#endif
drivers/staging/rtlwifi/halmac/halmac_bit2.h 0 → 100644
View file @ 938a0447
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/staging/rtlwifi/halmac/halmac_bit_8822b.h 0 → 100644
View file @ 938a0447
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/staging/rtlwifi/halmac/halmac_fw_info.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_FW_INFO_H_
#define _HALMAC_FW_INFO_H_
#define H2C_FORMAT_VERSION 6
#define H2C_ACK_HDR_CONTENT_LENGTH 8
#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16
#define SCAN_STATUS_RPT_CONTENT_LENGTH 4
#define C2H_DBG_HEADER_LENGTH 4
#define C2H_DBG_CONTENT_MAX_LENGTH 228
#define C2H_DBG_CONTENT_SEQ_OFFSET 1
/* Rename from FW SysHalCom_Debug_RAM.h */
#define FW_REG_H2CPKT_DONE_SEQ 0x1C8
#define fw_reg_wow_reason 0x1C7
enum halmac_data_type {
HALMAC_DATA_TYPE_MAC_REG = 0x00,
HALMAC_DATA_TYPE_BB_REG = 0x01,
HALMAC_DATA_TYPE_RADIO_A = 0x02,
HALMAC_DATA_TYPE_RADIO_B = 0x03,
HALMAC_DATA_TYPE_RADIO_C = 0x04,
HALMAC_DATA_TYPE_RADIO_D = 0x05,
HALMAC_DATA_TYPE_DRV_DEFINE_0 = 0x80,
HALMAC_DATA_TYPE_DRV_DEFINE_1 = 0x81,
HALMAC_DATA_TYPE_DRV_DEFINE_2 = 0x82,
HALMAC_DATA_TYPE_DRV_DEFINE_3 = 0x83,
HALMAC_DATA_TYPE_UNDEFINE = 0x7FFFFFFF,
};
enum halmac_packet_id {
HALMAC_PACKET_PROBE_REQ = 0x00,
HALMAC_PACKET_SYNC_BCN = 0x01,
HALMAC_PACKET_DISCOVERY_BCN = 0x02,
HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF,
};
/* Channel Switch Action ID */
enum halmac_cs_action_id {
HALMAC_CS_ACTION_NONE = 0x00,
HALMAC_CS_ACTIVE_SCAN = 0x01,
HALMAC_CS_NAN_NONMASTER_DW = 0x02,
HALMAC_CS_NAN_NONMASTER_NONDW = 0x03,
HALMAC_CS_NAN_MASTER_NONDW = 0x04,
HALMAC_CS_NAN_MASTER_DW = 0x05,
HALMAC_CS_ACTION_UNDEFINE = 0x7FFFFFFF,
};
/* Channel Switch Extra Action ID */
enum halmac_cs_extra_action_id {
HALMAC_CS_EXTRA_ACTION_NONE = 0x00,
HALMAC_CS_EXTRA_UPDATE_PROBE = 0x01,
HALMAC_CS_EXTRA_UPDATE_BEACON = 0x02,
HALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF,
};
enum halmac_h2c_return_code {
HALMAC_H2C_RETURN_SUCCESS = 0x00,
HALMAC_H2C_RETURN_CFG_ERR_LEN = 0x01,
HALMAC_H2C_RETURN_CFG_ERR_CMD = 0x02,
HALMAC_H2C_RETURN_EFUSE_ERR_DUMP = 0x03,
HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04, /* DMEM buffer full */
HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05, /* Invalid pack id */
HALMAC_H2C_RETURN_RUN_ERR_EMPTY =
0x06, /* No data in dedicated buffer */
HALMAC_H2C_RETURN_RUN_ERR_LEN = 0x07,
HALMAC_H2C_RETURN_RUN_ERR_CMD = 0x08,
HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09, /* Invalid pack id */
HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A, /* DMEM buffer full */
HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B, /* Invalid packet id */
HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C, /* DMEM buffer full */
HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D, /* PHYDM API return fail */
HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E, /* Invalid original H2C cmd id */
HALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF,
};
enum halmac_scan_report_code {
HALMAC_SCAN_REPORT_DONE = 0x00,
HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01, /* PHYDM API return fail */
HALMAC_SCAN_REPORT_ERR_ID = 0x02, /* Invalid ActionID */
HALMAC_SCAN_REPORT_ERR_TX = 0x03, /* Tx RsvdPage fail */
HALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF,
};
#endif
drivers/staging/rtlwifi/halmac/halmac_fw_offload_c2h_nic.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
#define C2H_SUB_CMD_ID_C2H_DBG 0X00
#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01
#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01
#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01
#define C2H_SUB_CMD_ID_IQK_ACK 0X01
#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01
#define C2H_SUB_CMD_ID_PSD_ACK 0X01
#define C2H_SUB_CMD_ID_PSD_DATA 0X04
#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
#define C2H_SUB_CMD_ID_IQK_DATA 0X06
#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07
#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08
#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09
#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A
#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B
#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C
#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D
#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E
#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET
#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH
#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING
#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF
#define H2C_CMD_ID_BT_COEX_ACK 0XFF
#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF
#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF
#define H2C_CMD_ID_IQK_ACK 0XFF
#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF
#define H2C_CMD_ID_PSD_ACK 0XFF
#define H2C_CMD_ID_CCX_RPT 0XFF
#define C2H_HDR_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_HDR_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_HDR_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_HDR_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_HDR_GET_C2H_SUB_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define C2H_HDR_SET_C2H_SUB_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define C2H_HDR_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_HDR_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_DBG_GET_DBG_MSG(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define C2H_DBG_SET_DBG_MSG(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define BT_COEX_INFO_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define BT_COEX_INFO_SET_DATA_START(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define SCAN_STATUS_RPT_GET_H2C_SEQ(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
#define SCAN_STATUS_RPT_SET_H2C_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define H2C_ACK_HDR_GET_H2C_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define H2C_ACK_HDR_SET_H2C_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
#define H2C_ACK_HDR_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 16)
#define H2C_ACK_HDR_SET_H2C_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 16, __value)
#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0XC, 0, 32)
#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0XC, 0, 32, __value)
#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X10, 0, 32)
#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X10, 0, 32, __value)
#define BT_COEX_ACK_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0XC, 0, 8)
#define BT_COEX_ACK_SET_DATA_START(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0XC, 0, 8, __value)
#define PSD_DATA_GET_SEGMENT_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 7)
#define PSD_DATA_SET_SEGMENT_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 7, __value)
#define PSD_DATA_GET_END_SEGMENT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 7, 1)
#define PSD_DATA_SET_END_SEGMENT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 7, 1, __value)
#define PSD_DATA_GET_SEGMENT_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define PSD_DATA_SET_SEGMENT_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define PSD_DATA_GET_TOTAL_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
#define PSD_DATA_SET_TOTAL_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
#define PSD_DATA_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 0, 16)
#define PSD_DATA_SET_H2C_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 0, 16, __value)
#define PSD_DATA_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 16, 8)
#define PSD_DATA_SET_DATA_START(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 16, 8, __value)
#define EFUSE_DATA_GET_SEGMENT_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 7)
#define EFUSE_DATA_SET_SEGMENT_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 7, __value)
#define EFUSE_DATA_GET_END_SEGMENT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 7, 1)
#define EFUSE_DATA_SET_END_SEGMENT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 7, 1, __value)
#define EFUSE_DATA_GET_SEGMENT_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define EFUSE_DATA_SET_SEGMENT_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define EFUSE_DATA_GET_TOTAL_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
#define EFUSE_DATA_SET_TOTAL_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
#define EFUSE_DATA_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 0, 16)
#define EFUSE_DATA_SET_H2C_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 0, 16, __value)
#define EFUSE_DATA_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 16, 8)
#define EFUSE_DATA_SET_DATA_START(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 16, 8, __value)
#define IQK_DATA_GET_SEGMENT_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 7)
#define IQK_DATA_SET_SEGMENT_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 7, __value)
#define IQK_DATA_GET_END_SEGMENT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 7, 1)
#define IQK_DATA_SET_END_SEGMENT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 7, 1, __value)
#define IQK_DATA_GET_SEGMENT_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define IQK_DATA_SET_SEGMENT_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define IQK_DATA_GET_TOTAL_SIZE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 16)
#define IQK_DATA_SET_TOTAL_SIZE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 16, __value)
#define IQK_DATA_GET_H2C_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 0, 16)
#define IQK_DATA_SET_H2C_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 0, 16, __value)
#define IQK_DATA_GET_DATA_START(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X8, 16, 8)
#define IQK_DATA_SET_DATA_START(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X8, 16, 8, __value)
#define CCX_RPT_GET_CCX_RPT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X4, 0, 129)
#define CCX_RPT_SET_CCX_RPT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X4, 0, 129, __value)
#endif
drivers/staging/rtlwifi/halmac/halmac_fw_offload_h2c_nic.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
#define CMD_ID_FW_OFFLOAD_H2C 0XFF
#define CMD_ID_CHANNEL_SWITCH 0XFF
#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
#define CMD_ID_CFG_PARAMETER 0XFF
#define CMD_ID_UPDATE_DATAPACK 0XFF
#define CMD_ID_RUN_DATAPACK 0XFF
#define CMD_ID_DOWNLOAD_FLASH 0XFF
#define CMD_ID_UPDATE_PACKET 0XFF
#define CMD_ID_GENERAL_INFO 0XFF
#define CMD_ID_IQK 0XFF
#define CMD_ID_POWER_TRACKING 0XFF
#define CMD_ID_PSD 0XFF
#define CMD_ID_P2PPS 0XFF
#define CMD_ID_BT_COEX 0XFF
#define CMD_ID_NAN_CTRL 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
#define CATEGORY_H2C_CMD_HEADER 0X00
#define CATEGORY_FW_OFFLOAD_H2C 0X01
#define CATEGORY_CHANNEL_SWITCH 0X01
#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
#define CATEGORY_CFG_PARAMETER 0X01
#define CATEGORY_UPDATE_DATAPACK 0X01
#define CATEGORY_RUN_DATAPACK 0X01
#define CATEGORY_DOWNLOAD_FLASH 0X01
#define CATEGORY_UPDATE_PACKET 0X01
#define CATEGORY_GENERAL_INFO 0X01
#define CATEGORY_IQK 0X01
#define CATEGORY_POWER_TRACKING 0X01
#define CATEGORY_PSD 0X01
#define CATEGORY_P2PPS 0X01
#define CATEGORY_BT_COEX 0X01
#define CATEGORY_NAN_CTRL 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
#define SUB_CMD_ID_CHANNEL_SWITCH 0X02
#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
#define SUB_CMD_ID_CFG_PARAMETER 0X08
#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
#define SUB_CMD_ID_RUN_DATAPACK 0X0A
#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
#define SUB_CMD_ID_UPDATE_PACKET 0X0C
#define SUB_CMD_ID_GENERAL_INFO 0X0D
#define SUB_CMD_ID_IQK 0X0E
#define SUB_CMD_ID_POWER_TRACKING 0X0F
#define SUB_CMD_ID_PSD 0X10
#define SUB_CMD_ID_P2PPS 0X24
#define SUB_CMD_ID_BT_COEX 0X60
#define SUB_CMD_ID_NAN_CTRL 0XB2
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
#define H2C_CMD_HEADER_GET_CATEGORY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 7)
#define H2C_CMD_HEADER_SET_CATEGORY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 7, __value)
#define H2C_CMD_HEADER_GET_ACK(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 7, 1)
#define H2C_CMD_HEADER_SET_ACK(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 7, 1, __value)
#define H2C_CMD_HEADER_GET_TOTAL_LEN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 16)
#define H2C_CMD_HEADER_SET_TOTAL_LEN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 16, __value)
#define H2C_CMD_HEADER_GET_SEQ_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 16)
#define H2C_CMD_HEADER_SET_SEQ_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 16, __value)
#define FW_OFFLOAD_H2C_GET_CATEGORY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 7)
#define FW_OFFLOAD_H2C_SET_CATEGORY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 7, __value)
#define FW_OFFLOAD_H2C_GET_ACK(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 7, 1)
#define FW_OFFLOAD_H2C_SET_ACK(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 7, 1, __value)
#define FW_OFFLOAD_H2C_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define FW_OFFLOAD_H2C_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 16)
#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 16, __value)
#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 16)
#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 16, __value)
#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 16)
#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 16, __value)
#define CHANNEL_SWITCH_GET_SWITCH_START(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
#define CHANNEL_SWITCH_SET_SWITCH_START(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
#define CHANNEL_SWITCH_GET_DEST_CH_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
#define CHANNEL_SWITCH_SET_DEST_CH_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 2, 1)
#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 2, 1, __value)
#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 3, 2)
#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 3, 2, __value)
#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 4)
#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 4, __value)
#define CHANNEL_SWITCH_GET_DEST_BW(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 28, 4)
#define CHANNEL_SWITCH_SET_DEST_BW(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 28, 4, __value)
#define CHANNEL_SWITCH_GET_DEST_CH(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
#define CHANNEL_SWITCH_SET_DEST_CH(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 8, 8)
#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 8, 8, __value)
#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 8)
#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 8, __value)
#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 24, 8)
#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 24, 8, __value)
#define CHANNEL_SWITCH_GET_TSF_HIGH(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
#define CHANNEL_SWITCH_SET_TSF_HIGH(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
#define CHANNEL_SWITCH_GET_TSF_LOW(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 32)
#define CHANNEL_SWITCH_SET_TSF_LOW(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 32, __value)
#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 16)
#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 16, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 4)
#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 4, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 12, 4)
#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 12, 4, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 32)
#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 32, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 32)
#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 32, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 32)
#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 32, __value)
#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 32)
#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 32, __value)
#define CFG_PARAMETER_GET_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
#define CFG_PARAMETER_SET_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
#define CFG_PARAMETER_GET_INIT_CASE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 1)
#define CFG_PARAMETER_SET_INIT_CASE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 1, __value)
#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
#define UPDATE_DATAPACK_GET_SIZE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
#define UPDATE_DATAPACK_SET_SIZE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
#define UPDATE_DATAPACK_GET_DATAPACK_ID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define UPDATE_DATAPACK_SET_DATAPACK_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
#define UPDATE_DATAPACK_GET_END_SEGMENT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 8, 1)
#define UPDATE_DATAPACK_SET_END_SEGMENT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 8, 1, __value)
#define RUN_DATAPACK_GET_DATAPACK_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define RUN_DATAPACK_SET_DATAPACK_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define DOWNLOAD_FLASH_GET_SPI_CMD(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define DOWNLOAD_FLASH_SET_SPI_CMD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define DOWNLOAD_FLASH_GET_LOCATION(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 16)
#define DOWNLOAD_FLASH_SET_LOCATION(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 16, __value)
#define DOWNLOAD_FLASH_GET_SIZE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 32)
#define DOWNLOAD_FLASH_SET_SIZE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 32, __value)
#define DOWNLOAD_FLASH_GET_START_ADDR(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
#define DOWNLOAD_FLASH_SET_START_ADDR(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
#define UPDATE_PACKET_GET_SIZE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
#define UPDATE_PACKET_SET_SIZE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
#define UPDATE_PACKET_GET_PACKET_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define UPDATE_PACKET_SET_PACKET_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define UPDATE_PACKET_GET_PACKET_LOC(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
#define UPDATE_PACKET_SET_PACKET_LOC(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
#define GENERAL_INFO_GET_REF_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define GENERAL_INFO_SET_REF_TYPE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define GENERAL_INFO_GET_RF_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 9)
#define GENERAL_INFO_SET_RF_TYPE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 9, __value)
#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define IQK_GET_CLEAR(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
#define IQK_SET_CLEAR(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
#define IQK_GET_SEGMENT_IQK(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
#define IQK_SET_SEGMENT_IQK(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
#define POWER_TRACKING_GET_ENABLE_A(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
#define POWER_TRACKING_SET_ENABLE_A(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
#define POWER_TRACKING_GET_ENABLE_B(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
#define POWER_TRACKING_SET_ENABLE_B(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
#define POWER_TRACKING_GET_ENABLE_C(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 2, 1)
#define POWER_TRACKING_SET_ENABLE_C(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 2, 1, __value)
#define POWER_TRACKING_GET_ENABLE_D(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 3, 1)
#define POWER_TRACKING_SET_ENABLE_D(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 3, 1, __value)
#define POWER_TRACKING_GET_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 4, 3)
#define POWER_TRACKING_SET_TYPE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 4, 3, __value)
#define POWER_TRACKING_GET_BBSWING_INDEX(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
#define POWER_TRACKING_SET_BBSWING_INDEX(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 8, 8)
#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 8, 8, __value)
#define POWER_TRACKING_GET_TSSI_VALUE_A(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 8)
#define POWER_TRACKING_SET_TSSI_VALUE_A(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 8, __value)
#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 8)
#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 8, __value)
#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 8, 8)
#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 8, 8, __value)
#define POWER_TRACKING_GET_TSSI_VALUE_B(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 16, 8)
#define POWER_TRACKING_SET_TSSI_VALUE_B(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 16, 8, __value)
#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 8)
#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 8, __value)
#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 8, 8)
#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 8, 8, __value)
#define POWER_TRACKING_GET_TSSI_VALUE_C(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 16, 8)
#define POWER_TRACKING_SET_TSSI_VALUE_C(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 16, 8, __value)
#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 8)
#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 8, __value)
#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 8, 8)
#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 8, 8, __value)
#define POWER_TRACKING_GET_TSSI_VALUE_D(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 16, 8)
#define POWER_TRACKING_SET_TSSI_VALUE_D(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 16, 8, __value)
#define PSD_GET_START_PSD(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 16)
#define PSD_SET_START_PSD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 16, __value)
#define PSD_GET_END_PSD(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 16)
#define PSD_SET_END_PSD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 16, __value)
#define P2PPS_GET_OFFLOAD_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 1)
#define P2PPS_SET_OFFLOAD_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 1, __value)
#define P2PPS_GET_ROLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 1, 1)
#define P2PPS_SET_ROLE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 1, 1, __value)
#define P2PPS_GET_CTWINDOW_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 2, 1)
#define P2PPS_SET_CTWINDOW_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 2, 1, __value)
#define P2PPS_GET_NOA_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 3, 1)
#define P2PPS_SET_NOA_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 3, 1, __value)
#define P2PPS_GET_NOA_SEL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 4, 1)
#define P2PPS_SET_NOA_SEL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 4, 1, __value)
#define P2PPS_GET_ALLSTASLEEP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 5, 1)
#define P2PPS_SET_ALLSTASLEEP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 5, 1, __value)
#define P2PPS_GET_DISCOVERY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 6, 1)
#define P2PPS_SET_DISCOVERY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 6, 1, __value)
#define P2PPS_GET_P2P_PORT_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
#define P2PPS_SET_P2P_PORT_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
#define P2PPS_GET_P2P_GROUP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define P2PPS_SET_P2P_GROUP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define P2PPS_GET_P2P_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
#define P2PPS_SET_P2P_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
#define P2PPS_GET_CTWINDOW_LENGTH(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
#define P2PPS_SET_CTWINDOW_LENGTH(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
#define P2PPS_GET_NOA_DURATION_PARA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 32)
#define P2PPS_SET_NOA_DURATION_PARA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 32, __value)
#define P2PPS_GET_NOA_INTERVAL_PARA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 32)
#define P2PPS_SET_NOA_INTERVAL_PARA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 32, __value)
#define P2PPS_GET_NOA_START_TIME_PARA(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 32)
#define P2PPS_SET_NOA_START_TIME_PARA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 32, __value)
#define P2PPS_GET_NOA_COUNT_PARA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 32)
#define P2PPS_SET_NOA_COUNT_PARA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 32, __value)
#define BT_COEX_GET_DATA_START(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define BT_COEX_SET_DATA_START(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define NAN_CTRL_GET_NAN_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 2)
#define NAN_CTRL_SET_NAN_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 2, __value)
#define NAN_CTRL_GET_SUPPORT_BAND(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 2)
#define NAN_CTRL_SET_SUPPORT_BAND(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 2, __value)
#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 10, 1)
#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 10, 1, __value)
#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 11, 1)
#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 11, 1, __value)
#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 16, 8)
#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 16, 8, __value)
#define NAN_CTRL_GET_CHANNEL_2G(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X08, 24, 8)
#define NAN_CTRL_SET_CHANNEL_2G(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 24, 8, __value)
#define NAN_CTRL_GET_CHANNEL_5G(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 8)
#define NAN_CTRL_SET_CHANNEL_5G(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 16)
#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 16, __value)
#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 16)
#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 16, __value)
#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 8)
#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 8, 8)
#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 8, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 16)
#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 16, __value)
#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 16, 16)
#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 16, 16, __value)
#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 8)
#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 8, 8)
#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 8, 8, __value)
#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 16)
#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 16, __value)
#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X1C, 16, 16)
#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 16, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 0, 8)
#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 0, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X08, 8, 8)
#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X08, 8, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 0, 16)
#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 0, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X0C, 16, 16)
#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X0C, 16, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 0, 8)
#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 0, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X10, 8, 8)
#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X10, 8, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 0, 16)
#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 0, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X14, 16, 16)
#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X14, 16, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 0, 8)
#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 0, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X18, 8, 8)
#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X18, 8, 8, __value)
#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X1C, 0, 16)
#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 0, 16, __value)
#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X1C, 16, 16)
#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X1C, 16, 16, __value)
#endif
drivers/staging/rtlwifi/halmac/halmac_h2c_extra_info_nic.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
#define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
#define PHY_PARAMETER_INFO_GET_LENGTH(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 0, 8)
#define PHY_PARAMETER_INFO_SET_LENGTH(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 0, 8, __value)
#define PHY_PARAMETER_INFO_GET_IO_CMD(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 8, 7)
#define PHY_PARAMETER_INFO_SET_IO_CMD(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 8, 7, __value)
#define PHY_PARAMETER_INFO_GET_MSK_EN(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 15, 1)
#define PHY_PARAMETER_INFO_SET_MSK_EN(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 15, 1, __value)
#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
#define PHY_PARAMETER_INFO_GET_RF_ADDR(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
#define PHY_PARAMETER_INFO_SET_RF_ADDR(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
#define PHY_PARAMETER_INFO_GET_IO_ADDR(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 16)
#define PHY_PARAMETER_INFO_SET_IO_ADDR(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 16, __value)
#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 16)
#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 16, __value)
#define PHY_PARAMETER_INFO_GET_RF_PATH(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 24, 8)
#define PHY_PARAMETER_INFO_SET_RF_PATH(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 24, 8, __value)
#define PHY_PARAMETER_INFO_GET_DATA(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X04, 0, 32)
#define PHY_PARAMETER_INFO_SET_DATA(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X04, 0, 32, __value)
#define PHY_PARAMETER_INFO_GET_MASK(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X08, 0, 32)
#define PHY_PARAMETER_INFO_SET_MASK(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X08, 0, 32, __value)
#define CHANNEL_INFO_GET_CHANNEL(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 0, 8)
#define CHANNEL_INFO_SET_CHANNEL(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 0, 8, __value)
#define CHANNEL_INFO_GET_PRI_CH_IDX(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 8, 4)
#define CHANNEL_INFO_SET_PRI_CH_IDX(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 8, 4, __value)
#define CHANNEL_INFO_GET_BANDWIDTH(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 12, 4)
#define CHANNEL_INFO_SET_BANDWIDTH(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 12, 4, __value)
#define CHANNEL_INFO_GET_TIMEOUT(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 8)
#define CHANNEL_INFO_SET_TIMEOUT(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 8, __value)
#define CHANNEL_INFO_GET_ACTION_ID(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 24, 7)
#define CHANNEL_INFO_SET_ACTION_ID(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 24, 7, __value)
#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 31, 1)
#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 31, 1, __value)
#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 0, 7)
#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 0, 7, __value)
#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 7, 1)
#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 7, 1, __value)
#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 8, 8)
#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 8, 8, __value)
#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__extra_info) \
LE_BITS_TO_4BYTE(__extra_info + 0X00, 16, 1)
#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__extra_info, __value) \
SET_BITS_TO_LE_4BYTE(__extra_info + 0X00, 16, 1, __value)
#endif
drivers/staging/rtlwifi/halmac/halmac_intf_phy_cmd.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef HALMAC_INTF_PHY_CMD
#define HALMAC_INTF_PHY_CMD
/* Cut mask */
enum halmac_intf_phy_cut {
HALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0),
HALMAC_INTF_PHY_CUT_A = BIT(1),
HALMAC_INTF_PHY_CUT_B = BIT(2),
HALMAC_INTF_PHY_CUT_C = BIT(3),
HALMAC_INTF_PHY_CUT_D = BIT(4),
HALMAC_INTF_PHY_CUT_E = BIT(5),
HALMAC_INTF_PHY_CUT_F = BIT(6),
HALMAC_INTF_PHY_CUT_G = BIT(7),
HALMAC_INTF_PHY_CUT_ALL = 0x7FFF,
};
/* IP selection */
enum halmac_ip_sel {
HALMAC_IP_SEL_INTF_PHY = 0,
HALMAC_IP_SEL_MAC = 1,
HALMAC_IP_SEL_PCIE_DBI = 2,
HALMAC_IP_SEL_UNDEFINE = 0x7FFF,
};
/* Platform mask */
enum halmac_intf_phy_platform {
HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF,
};
#endif
drivers/staging/rtlwifi/halmac/halmac_original_c2h_nic.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
#define CMD_ID_C2H 0X00
#define CMD_ID_DBG 0X00
#define CMD_ID_C2H_LB 0X01
#define CMD_ID_C2H_SND_TXBF 0X02
#define CMD_ID_C2H_CCX_RPT 0X03
#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
#define CMD_ID_C2H_RA_RPT 0X0C
#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
#define CMD_ID_C2H_RA_PARA_RPT 0X0E
#define CMD_ID_C2H_CUR_CHANNEL 0X10
#define CMD_ID_C2H_GPIO_WAKEUP 0X14
#define C2H_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define DBG_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define DBG_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define DBG_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define DBG_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define DBG_GET_DBG_STR1(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define DBG_SET_DBG_STR1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define DBG_GET_DBG_STR2(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define DBG_SET_DBG_STR2(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define DBG_GET_DBG_STR3(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define DBG_SET_DBG_STR3(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define DBG_GET_DBG_STR4(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define DBG_SET_DBG_STR4(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define DBG_GET_DBG_STR5(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
#define DBG_SET_DBG_STR5(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
#define DBG_GET_DBG_STR6(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
#define DBG_SET_DBG_STR6(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
#define DBG_GET_DBG_STR7(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
#define DBG_SET_DBG_STR7(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
#define DBG_GET_DBG_STR8(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
#define DBG_SET_DBG_STR8(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
#define DBG_GET_DBG_STR9(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 16, 8)
#define DBG_SET_DBG_STR9(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 16, 8, __value)
#define DBG_GET_DBG_STR10(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 24, 8)
#define DBG_SET_DBG_STR10(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 24, 8, __value)
#define DBG_GET_DBG_STR11(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 0, 8)
#define DBG_SET_DBG_STR11(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 0, 8, __value)
#define DBG_GET_DBG_STR12(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 8, 8)
#define DBG_SET_DBG_STR12(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 8, 8, __value)
#define DBG_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define DBG_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define DBG_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define DBG_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_LB_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_LB_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_LB_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_LB_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_LB_GET_PAYLOAD1(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 16)
#define C2H_LB_SET_PAYLOAD1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 16, __value)
#define C2H_LB_GET_PAYLOAD2(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 32)
#define C2H_LB_SET_PAYLOAD2(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 32, __value)
#define C2H_LB_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_LB_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_LB_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_LB_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_SND_TXBF_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_SND_TXBF_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_SND_TXBF_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_SND_TXBF_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_SND_TXBF_GET_SND_RESULT(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 1)
#define C2H_SND_TXBF_SET_SND_RESULT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 1, __value)
#define C2H_SND_TXBF_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_SND_TXBF_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_SND_TXBF_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_SND_TXBF_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_CCX_RPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_CCX_RPT_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_CCX_RPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_CCX_RPT_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_CCX_RPT_GET_QSEL(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 5)
#define C2H_CCX_RPT_SET_QSEL(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 5, __value)
#define C2H_CCX_RPT_GET_BMC(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 21, 1)
#define C2H_CCX_RPT_SET_BMC(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 21, 1, __value)
#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 22, 1)
#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 22, 1, __value)
#define C2H_CCX_RPT_GET_RETRY_OVER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 23, 1)
#define C2H_CCX_RPT_SET_RETRY_OVER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 23, 1, __value)
#define C2H_CCX_RPT_GET_MACID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_CCX_RPT_SET_MACID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 6)
#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 6, __value)
#define C2H_CCX_RPT_GET_QUEUE7_0(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define C2H_CCX_RPT_SET_QUEUE7_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define C2H_CCX_RPT_GET_QUEUE15_8(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
#define C2H_CCX_RPT_SET_QUEUE15_8(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
#define C2H_CCX_RPT_GET_SW_DEFINE_0(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
#define C2H_CCX_RPT_SET_SW_DEFINE_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
#define C2H_CCX_RPT_GET_SW_DEFINE_1(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 4)
#define C2H_CCX_RPT_SET_SW_DEFINE_1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 4, __value)
#define C2H_CCX_RPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_CCX_RPT_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_CCX_RPT_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_CCX_RPT_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_AP_REQ_TXRPT_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 16, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 16, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 24, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 24, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 0, 8)
#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 0, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 8, 8)
#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 8, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_AP_REQ_TXRPT_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 7)
#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 7, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_RA_RPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_RA_RPT_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_RA_RPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_RA_RPT_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_RA_RPT_GET_RATE(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define C2H_RA_RPT_SET_RATE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define C2H_RA_RPT_GET_MACID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_RA_RPT_SET_MACID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_RA_RPT_GET_USE_LDPC(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 1)
#define C2H_RA_RPT_SET_USE_LDPC(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 1, __value)
#define C2H_RA_RPT_GET_USE_TXBF(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X04, 1, 1)
#define C2H_RA_RPT_SET_USE_TXBF(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 1, 1, __value)
#define C2H_RA_RPT_GET_COLLISION_STATE(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define C2H_RA_RPT_SET_COLLISION_STATE(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define C2H_RA_RPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_RA_RPT_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_RA_RPT_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_RA_RPT_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_SEQ(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_SPECIAL_STATISTICS_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA0(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 24, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA0(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 24, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA1(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 0, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA1(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 0, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA2(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 8, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA2(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 8, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA3(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 16, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA3(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 16, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA4(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X04, 24, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA4(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X04, 24, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA5(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 0, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA5(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 0, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA6(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 8, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA6(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 8, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_DATA7(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X08, 16, 8)
#define C2H_SPECIAL_STATISTICS_SET_DATA7(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X08, 16, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_LEN(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_SPECIAL_STATISTICS_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_RA_PARA_RPT_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_RA_PARA_RPT_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_RA_PARA_RPT_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_RA_PARA_RPT_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_RA_PARA_RPT_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_RA_PARA_RPT_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_RA_PARA_RPT_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_RA_PARA_RPT_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_CUR_CHANNEL_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_CUR_CHANNEL_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_CUR_CHANNEL_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_CUR_CHANNEL_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__c2h) \
LE_BITS_TO_4BYTE(__c2h + 0X00, 16, 8)
#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 16, 8, __value)
#define C2H_CUR_CHANNEL_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_CUR_CHANNEL_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_CUR_CHANNEL_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_CUR_CHANNEL_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#define C2H_GPIO_WAKEUP_GET_CMD_ID(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 0, 8)
#define C2H_GPIO_WAKEUP_SET_CMD_ID(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 0, 8, __value)
#define C2H_GPIO_WAKEUP_GET_SEQ(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X00, 8, 8)
#define C2H_GPIO_WAKEUP_SET_SEQ(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X00, 8, 8, __value)
#define C2H_GPIO_WAKEUP_GET_LEN(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 16, 8)
#define C2H_GPIO_WAKEUP_SET_LEN(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 16, 8, __value)
#define C2H_GPIO_WAKEUP_GET_TRIGGER(__c2h) LE_BITS_TO_4BYTE(__c2h + 0X0C, 24, 8)
#define C2H_GPIO_WAKEUP_SET_TRIGGER(__c2h, __value) \
SET_BITS_TO_LE_4BYTE(__c2h + 0X0C, 24, 8, __value)
#endif
drivers/staging/rtlwifi/halmac/halmac_original_h2c_nic.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_
#define _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_
#define CMD_ID_ORIGINAL_H2C 0X00
#define CMD_ID_H2C2H_LB 0X0
#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06
#define CMD_ID_RSVD_PAGE 0X0
#define CMD_ID_MEDIA_STATUS_RPT 0X01
#define CMD_ID_KEEP_ALIVE 0X03
#define CMD_ID_DISCONNECT_DECISION 0X04
#define CMD_ID_AP_OFFLOAD 0X08
#define CMD_ID_BCN_RSVDPAGE 0X09
#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A
#define CMD_ID_SET_PWR_MODE 0X00
#define CMD_ID_PS_TUNING_PARA 0X01
#define CMD_ID_PS_TUNING_PARA_II 0X02
#define CMD_ID_PS_LPS_PARA 0X03
#define CMD_ID_P2P_PS_OFFLOAD 0X04
#define CMD_ID_PS_SCAN_EN 0X05
#define CMD_ID_SAP_PS 0X06
#define CMD_ID_INACTIVE_PS 0X07
#define CMD_ID_MACID_CFG 0X00
#define CMD_ID_TXBF 0X01
#define CMD_ID_RSSI_SETTING 0X02
#define CMD_ID_AP_REQ_TXRPT 0X03
#define CMD_ID_INIT_RATE_COLLECTION 0X04
#define CMD_ID_IQK_OFFLOAD 0X05
#define CMD_ID_MACID_CFG_3SS 0X06
#define CMD_ID_RA_PARA_ADJUST 0X07
#define CMD_ID_WWLAN 0X00
#define CMD_ID_REMOTE_WAKE_CTRL 0X01
#define CMD_ID_AOAC_GLOBAL_INFO 0X02
#define CMD_ID_AOAC_RSVD_PAGE 0X03
#define CMD_ID_AOAC_RSVD_PAGE2 0X04
#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05
#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07
#define CMD_ID_AOAC_RSVD_PAGE3 0X08
#define CLASS_ORIGINAL_H2C 0X00
#define CLASS_H2C2H_LB 0X07
#define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04
#define CLASS_RSVD_PAGE 0X0
#define CLASS_MEDIA_STATUS_RPT 0X0
#define CLASS_KEEP_ALIVE 0X0
#define CLASS_DISCONNECT_DECISION 0X0
#define CLASS_AP_OFFLOAD 0X0
#define CLASS_BCN_RSVDPAGE 0X0
#define CLASS_PROBE_RSP_RSVDPAGE 0X0
#define CLASS_SET_PWR_MODE 0X01
#define CLASS_PS_TUNING_PARA 0X01
#define CLASS_PS_TUNING_PARA_II 0X01
#define CLASS_PS_LPS_PARA 0X01
#define CLASS_P2P_PS_OFFLOAD 0X01
#define CLASS_PS_SCAN_EN 0X1
#define CLASS_SAP_PS 0X1
#define CLASS_INACTIVE_PS 0X1
#define CLASS_MACID_CFG 0X2
#define CLASS_TXBF 0X2
#define CLASS_RSSI_SETTING 0X2
#define CLASS_AP_REQ_TXRPT 0X2
#define CLASS_INIT_RATE_COLLECTION 0X2
#define CLASS_IQK_OFFLOAD 0X2
#define CLASS_MACID_CFG_3SS 0X2
#define CLASS_RA_PARA_ADJUST 0X02
#define CLASS_WWLAN 0X4
#define CLASS_REMOTE_WAKE_CTRL 0X4
#define CLASS_AOAC_GLOBAL_INFO 0X04
#define CLASS_AOAC_RSVD_PAGE 0X04
#define CLASS_AOAC_RSVD_PAGE2 0X04
#define CLASS_D0_SCAN_OFFLOAD_INFO 0X04
#define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04
#define CLASS_AOAC_RSVD_PAGE3 0X04
#define ORIGINAL_H2C_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define ORIGINAL_H2C_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define ORIGINAL_H2C_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define ORIGINAL_H2C_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define H2C2H_LB_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define H2C2H_LB_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define H2C2H_LB_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define H2C2H_LB_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define H2C2H_LB_GET_SEQ(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define H2C2H_LB_SET_SEQ(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define H2C2H_LB_GET_PAYLOAD1(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 16)
#define H2C2H_LB_SET_PAYLOAD1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 16, __value)
#define H2C2H_LB_GET_PAYLOAD2(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 32)
#define H2C2H_LB_SET_PAYLOAD2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 32, __value)
#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 12, 1)
#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 12, 1, __value)
#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 17)
#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 17, __value)
#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define RSVD_PAGE_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define RSVD_PAGE_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define RSVD_PAGE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define RSVD_PAGE_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define RSVD_PAGE_GET_LOC_PROBE_RSP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define RSVD_PAGE_SET_LOC_PROBE_RSP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define RSVD_PAGE_GET_LOC_PS_POLL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define RSVD_PAGE_SET_LOC_PS_POLL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define RSVD_PAGE_GET_LOC_NULL_DATA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define RSVD_PAGE_SET_LOC_NULL_DATA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define RSVD_PAGE_GET_LOC_QOS_NULL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define RSVD_PAGE_SET_LOC_QOS_NULL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define RSVD_PAGE_GET_LOC_CTS2SELF(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
#define RSVD_PAGE_SET_LOC_CTS2SELF(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
#define MEDIA_STATUS_RPT_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define MEDIA_STATUS_RPT_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define MEDIA_STATUS_RPT_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define MEDIA_STATUS_RPT_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define MEDIA_STATUS_RPT_GET_OP_MODE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define MEDIA_STATUS_RPT_SET_OP_MODE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define MEDIA_STATUS_RPT_GET_MACID_IN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
#define MEDIA_STATUS_RPT_SET_MACID_IN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
#define MEDIA_STATUS_RPT_GET_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define MEDIA_STATUS_RPT_SET_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define MEDIA_STATUS_RPT_GET_MACID_END(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define MEDIA_STATUS_RPT_SET_MACID_END(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define KEEP_ALIVE_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define KEEP_ALIVE_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define KEEP_ALIVE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define KEEP_ALIVE_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define KEEP_ALIVE_GET_ENABLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define KEEP_ALIVE_SET_ENABLE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
#define KEEP_ALIVE_GET_PKT_TYPE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
#define KEEP_ALIVE_SET_PKT_TYPE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define DISCONNECT_DECISION_GET_CMD_ID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define DISCONNECT_DECISION_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define DISCONNECT_DECISION_GET_CLASS(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define DISCONNECT_DECISION_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define DISCONNECT_DECISION_GET_ENABLE(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define DISCONNECT_DECISION_SET_ENABLE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
#define DISCONNECT_DECISION_GET_DISCONNECT_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
#define DISCONNECT_DECISION_SET_DISCONNECT_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define AP_OFFLOAD_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define AP_OFFLOAD_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define AP_OFFLOAD_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define AP_OFFLOAD_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define AP_OFFLOAD_GET_ON(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define AP_OFFLOAD_SET_ON(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
#define AP_OFFLOAD_GET_LINKED(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
#define AP_OFFLOAD_SET_LINKED(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
#define AP_OFFLOAD_GET_EN_AUTO_WAKE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
#define AP_OFFLOAD_SET_EN_AUTO_WAKE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
#define AP_OFFLOAD_GET_WAKE_FLAG(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 12, 1)
#define AP_OFFLOAD_SET_WAKE_FLAG(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 12, 1, __value)
#define AP_OFFLOAD_GET_HIDDEN_ROOT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 1)
#define AP_OFFLOAD_SET_HIDDEN_ROOT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 1, __value)
#define AP_OFFLOAD_GET_HIDDEN_VAP1(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 17, 1)
#define AP_OFFLOAD_SET_HIDDEN_VAP1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 17, 1, __value)
#define AP_OFFLOAD_GET_HIDDEN_VAP2(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 18, 1)
#define AP_OFFLOAD_SET_HIDDEN_VAP2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 18, 1, __value)
#define AP_OFFLOAD_GET_HIDDEN_VAP3(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 19, 1)
#define AP_OFFLOAD_SET_HIDDEN_VAP3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 19, 1, __value)
#define AP_OFFLOAD_GET_HIDDEN_VAP4(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 20, 1)
#define AP_OFFLOAD_SET_HIDDEN_VAP4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 20, 1, __value)
#define AP_OFFLOAD_GET_DENYANY_ROOT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 1)
#define AP_OFFLOAD_SET_DENYANY_ROOT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 1, __value)
#define AP_OFFLOAD_GET_DENYANY_VAP1(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 25, 1)
#define AP_OFFLOAD_SET_DENYANY_VAP1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 25, 1, __value)
#define AP_OFFLOAD_GET_DENYANY_VAP2(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 26, 1)
#define AP_OFFLOAD_SET_DENYANY_VAP2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 26, 1, __value)
#define AP_OFFLOAD_GET_DENYANY_VAP3(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 27, 1)
#define AP_OFFLOAD_SET_DENYANY_VAP3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 27, 1, __value)
#define AP_OFFLOAD_GET_DENYANY_VAP4(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 28, 1)
#define AP_OFFLOAD_SET_DENYANY_VAP4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 28, 1, __value)
#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define AP_OFFLOAD_GET_WAKE_TIMEOUT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define AP_OFFLOAD_SET_WAKE_TIMEOUT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define AP_OFFLOAD_GET_LEN_IV_PAIR(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
#define AP_OFFLOAD_SET_LEN_IV_PAIR(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
#define AP_OFFLOAD_GET_LEN_IV_GRP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
#define AP_OFFLOAD_SET_LEN_IV_GRP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
#define BCN_RSVDPAGE_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define BCN_RSVDPAGE_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define BCN_RSVDPAGE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define BCN_RSVDPAGE_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define BCN_RSVDPAGE_GET_LOC_ROOT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define BCN_RSVDPAGE_SET_LOC_ROOT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define BCN_RSVDPAGE_GET_LOC_VAP1(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define BCN_RSVDPAGE_SET_LOC_VAP1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define BCN_RSVDPAGE_GET_LOC_VAP2(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define BCN_RSVDPAGE_SET_LOC_VAP2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define BCN_RSVDPAGE_GET_LOC_VAP3(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define BCN_RSVDPAGE_SET_LOC_VAP3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define BCN_RSVDPAGE_GET_LOC_VAP4(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define BCN_RSVDPAGE_SET_LOC_VAP4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define PROBE_RSP_RSVDPAGE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define PROBE_RSP_RSVDPAGE_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define SET_PWR_MODE_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define SET_PWR_MODE_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define SET_PWR_MODE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define SET_PWR_MODE_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define SET_PWR_MODE_GET_MODE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 7)
#define SET_PWR_MODE_SET_MODE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 7, __value)
#define SET_PWR_MODE_GET_CLK_REQUEST(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 15, 1)
#define SET_PWR_MODE_SET_CLK_REQUEST(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 15, 1, __value)
#define SET_PWR_MODE_GET_RLBM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 4)
#define SET_PWR_MODE_SET_RLBM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 4, __value)
#define SET_PWR_MODE_GET_SMART_PS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 20, 4)
#define SET_PWR_MODE_SET_SMART_PS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 20, 4, __value)
#define SET_PWR_MODE_GET_AWAKE_INTERVAL(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define SET_PWR_MODE_SET_AWAKE_INTERVAL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 1)
#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 1, __value)
#define SET_PWR_MODE_GET_BCN_EARLY_RPT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 2, 1)
#define SET_PWR_MODE_SET_BCN_EARLY_RPT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 2, 1, __value)
#define SET_PWR_MODE_GET_PORT_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 5, 3)
#define SET_PWR_MODE_SET_PORT_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 5, 3, __value)
#define SET_PWR_MODE_GET_PWR_STATE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define SET_PWR_MODE_SET_PWR_STATE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 1)
#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 1, __value)
#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 17, 1)
#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 17, 1, __value)
#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 18, 1)
#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 18, 1, __value)
#define SET_PWR_MODE_GET_PROTECT_BCN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 19, 1)
#define SET_PWR_MODE_SET_PROTECT_BCN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 19, 1, __value)
#define SET_PWR_MODE_GET_SILENCE_PERIOD(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 20, 1)
#define SET_PWR_MODE_SET_SILENCE_PERIOD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 20, 1, __value)
#define SET_PWR_MODE_GET_FAST_BT_CONNECT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 21, 1)
#define SET_PWR_MODE_SET_FAST_BT_CONNECT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 21, 1, __value)
#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 22, 1)
#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 22, 1, __value)
#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 1)
#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 1, __value)
#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 25, 3)
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 25, 3, __value)
#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 28, 4)
#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 28, 4, __value)
#define PS_TUNING_PARA_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define PS_TUNING_PARA_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define PS_TUNING_PARA_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define PS_TUNING_PARA_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 7)
#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 7, __value)
#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 15, 1)
#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 15, 1, __value)
#define PS_TUNING_PARA_GET_PS_TIME_OUT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 4)
#define PS_TUNING_PARA_SET_PS_TIME_OUT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 4, __value)
#define PS_TUNING_PARA_GET_ADOPT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define PS_TUNING_PARA_SET_ADOPT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define PS_TUNING_PARA_II_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define PS_TUNING_PARA_II_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define PS_TUNING_PARA_II_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define PS_TUNING_PARA_II_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 7)
#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 7, __value)
#define PS_TUNING_PARA_II_GET_ADOPT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 15, 1)
#define PS_TUNING_PARA_II_SET_ADOPT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 15, 1, __value)
#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define PS_LPS_PARA_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define PS_LPS_PARA_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define PS_LPS_PARA_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define PS_LPS_PARA_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define PS_LPS_PARA_GET_LPS_CONTROL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define PS_LPS_PARA_SET_LPS_CONTROL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define P2P_PS_OFFLOAD_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define P2P_PS_OFFLOAD_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define P2P_PS_OFFLOAD_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define P2P_PS_OFFLOAD_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define P2P_PS_OFFLOAD_GET_ROLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
#define P2P_PS_OFFLOAD_SET_ROLE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
#define P2P_PS_OFFLOAD_GET_NOA0_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
#define P2P_PS_OFFLOAD_SET_NOA0_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
#define P2P_PS_OFFLOAD_GET_NOA1_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 12, 1)
#define P2P_PS_OFFLOAD_SET_NOA1_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 12, 1, __value)
#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 13, 1)
#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 13, 1, __value)
#define P2P_PS_OFFLOAD_GET_DISCOVERY(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 14, 1)
#define P2P_PS_OFFLOAD_SET_DISCOVERY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 14, 1, __value)
#define PS_SCAN_EN_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define PS_SCAN_EN_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define PS_SCAN_EN_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define PS_SCAN_EN_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define PS_SCAN_EN_GET_ENABLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define PS_SCAN_EN_SET_ENABLE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define SAP_PS_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define SAP_PS_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define SAP_PS_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define SAP_PS_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define SAP_PS_GET_ENABLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define SAP_PS_SET_ENABLE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define SAP_PS_GET_EN_PS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
#define SAP_PS_SET_EN_PS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
#define SAP_PS_GET_EN_LP_RX(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
#define SAP_PS_SET_EN_LP_RX(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
#define SAP_PS_GET_MANUAL_32K(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
#define SAP_PS_SET_MANUAL_32K(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
#define SAP_PS_GET_DURATION(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define SAP_PS_SET_DURATION(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define INACTIVE_PS_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define INACTIVE_PS_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define INACTIVE_PS_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define INACTIVE_PS_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define INACTIVE_PS_GET_ENABLE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define INACTIVE_PS_SET_ENABLE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
#define INACTIVE_PS_GET_FREQUENCY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define INACTIVE_PS_SET_FREQUENCY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define INACTIVE_PS_GET_DURATION(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define INACTIVE_PS_SET_DURATION(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define MACID_CFG_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define MACID_CFG_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define MACID_CFG_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define MACID_CFG_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define MACID_CFG_GET_MAC_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define MACID_CFG_SET_MAC_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define MACID_CFG_GET_RATE_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 5)
#define MACID_CFG_SET_RATE_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 5, __value)
#define MACID_CFG_GET_SGI(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 23, 1)
#define MACID_CFG_SET_SGI(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 23, 1, __value)
#define MACID_CFG_GET_BW(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 2)
#define MACID_CFG_SET_BW(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 2, __value)
#define MACID_CFG_GET_LDPC_CAP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 26, 1)
#define MACID_CFG_SET_LDPC_CAP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 26, 1, __value)
#define MACID_CFG_GET_NO_UPDATE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 27, 1)
#define MACID_CFG_SET_NO_UPDATE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 27, 1, __value)
#define MACID_CFG_GET_WHT_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 28, 2)
#define MACID_CFG_SET_WHT_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 28, 2, __value)
#define MACID_CFG_GET_DISPT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 30, 1)
#define MACID_CFG_SET_DISPT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 30, 1, __value)
#define MACID_CFG_GET_DISRA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 31, 1)
#define MACID_CFG_SET_DISRA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 31, 1, __value)
#define MACID_CFG_GET_RATE_MASK7_0(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define MACID_CFG_SET_RATE_MASK7_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define MACID_CFG_GET_RATE_MASK15_8(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define MACID_CFG_SET_RATE_MASK15_8(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define MACID_CFG_GET_RATE_MASK23_16(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
#define MACID_CFG_SET_RATE_MASK23_16(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
#define MACID_CFG_GET_RATE_MASK31_24(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
#define MACID_CFG_SET_RATE_MASK31_24(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
#define TXBF_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define TXBF_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define TXBF_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define TXBF_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define TXBF_GET_NDPA0_HEAD_PAGE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define TXBF_SET_NDPA0_HEAD_PAGE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define TXBF_GET_NDPA1_HEAD_PAGE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define TXBF_SET_NDPA1_HEAD_PAGE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define TXBF_GET_PERIOD_0(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define TXBF_SET_PERIOD_0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define RSSI_SETTING_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define RSSI_SETTING_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define RSSI_SETTING_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define RSSI_SETTING_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define RSSI_SETTING_GET_MAC_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define RSSI_SETTING_SET_MAC_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define RSSI_SETTING_GET_RSSI(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 7)
#define RSSI_SETTING_SET_RSSI(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 7, __value)
#define RSSI_SETTING_GET_RA_INFO(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define RSSI_SETTING_SET_RA_INFO(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define AP_REQ_TXRPT_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define AP_REQ_TXRPT_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define AP_REQ_TXRPT_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define AP_REQ_TXRPT_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define AP_REQ_TXRPT_GET_STA1_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define AP_REQ_TXRPT_SET_STA1_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define AP_REQ_TXRPT_GET_STA2_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define AP_REQ_TXRPT_SET_STA2_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 1)
#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 1, __value)
#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 25, 1)
#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 25, 1, __value)
#define INIT_RATE_COLLECTION_GET_CMD_ID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define INIT_RATE_COLLECTION_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define INIT_RATE_COLLECTION_GET_CLASS(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define INIT_RATE_COLLECTION_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define INIT_RATE_COLLECTION_GET_STA1_MACID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define INIT_RATE_COLLECTION_SET_STA1_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define INIT_RATE_COLLECTION_GET_STA2_MACID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define INIT_RATE_COLLECTION_SET_STA2_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define INIT_RATE_COLLECTION_GET_STA3_MACID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define INIT_RATE_COLLECTION_SET_STA3_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define INIT_RATE_COLLECTION_GET_STA4_MACID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define INIT_RATE_COLLECTION_SET_STA4_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define INIT_RATE_COLLECTION_GET_STA5_MACID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define INIT_RATE_COLLECTION_SET_STA5_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define INIT_RATE_COLLECTION_GET_STA6_MACID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
#define INIT_RATE_COLLECTION_SET_STA6_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
#define INIT_RATE_COLLECTION_GET_STA7_MACID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
#define INIT_RATE_COLLECTION_SET_STA7_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
#define IQK_OFFLOAD_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define IQK_OFFLOAD_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define IQK_OFFLOAD_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define IQK_OFFLOAD_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define IQK_OFFLOAD_GET_CHANNEL(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define IQK_OFFLOAD_SET_CHANNEL(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define IQK_OFFLOAD_GET_BWBAND(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define IQK_OFFLOAD_SET_BWBAND(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define IQK_OFFLOAD_GET_EXTPALNA(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define IQK_OFFLOAD_SET_EXTPALNA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define MACID_CFG_3SS_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define MACID_CFG_3SS_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define MACID_CFG_3SS_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define MACID_CFG_3SS_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define MACID_CFG_3SS_GET_MACID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define MACID_CFG_3SS_SET_MACID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define MACID_CFG_3SS_GET_RATE_MASK_39_32(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define MACID_CFG_3SS_SET_RATE_MASK_39_32(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define MACID_CFG_3SS_GET_RATE_MASK_47_40(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define MACID_CFG_3SS_SET_RATE_MASK_47_40(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define RA_PARA_ADJUST_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define RA_PARA_ADJUST_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define RA_PARA_ADJUST_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define RA_PARA_ADJUST_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define RA_PARA_ADJUST_GET_MAC_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define RA_PARA_ADJUST_SET_MAC_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define RA_PARA_ADJUST_GET_RATE_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define RA_PARA_ADJUST_SET_RATE_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define RA_PARA_ADJUST_GET_VALUE_BYTE0(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define RA_PARA_ADJUST_SET_VALUE_BYTE0(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define RA_PARA_ADJUST_GET_VALUE_BYTE1(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define RA_PARA_ADJUST_SET_VALUE_BYTE1(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
#define WWLAN_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define WWLAN_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define WWLAN_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define WWLAN_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define WWLAN_GET_FUNC_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define WWLAN_SET_FUNC_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define WWLAN_GET_PATTERM_MAT_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
#define WWLAN_SET_PATTERM_MAT_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
#define WWLAN_GET_MAGIC_PKT_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
#define WWLAN_SET_MAGIC_PKT_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
#define WWLAN_GET_UNICAST_WAKEUP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
#define WWLAN_SET_UNICAST_WAKEUP_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
#define WWLAN_GET_ALL_PKT_DROP(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 12, 1)
#define WWLAN_SET_ALL_PKT_DROP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 12, 1, __value)
#define WWLAN_GET_GPIO_ACTIVE(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 13, 1)
#define WWLAN_SET_GPIO_ACTIVE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 13, 1, __value)
#define WWLAN_GET_REKEY_WAKEUP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 14, 1)
#define WWLAN_SET_REKEY_WAKEUP_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 14, 1, __value)
#define WWLAN_GET_DEAUTH_WAKEUP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 15, 1)
#define WWLAN_SET_DEAUTH_WAKEUP_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 15, 1, __value)
#define WWLAN_GET_GPIO_NUM(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 7)
#define WWLAN_SET_GPIO_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 7, __value)
#define WWLAN_GET_DATAPIN_WAKEUP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 23, 1)
#define WWLAN_SET_DATAPIN_WAKEUP_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 23, 1, __value)
#define WWLAN_GET_GPIO_DURATION(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define WWLAN_SET_GPIO_DURATION(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define WWLAN_GET_GPIO_PLUS_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 1)
#define WWLAN_SET_GPIO_PLUS_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 1, __value)
#define WWLAN_GET_GPIO_PULSE_COUNT(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 1, 7)
#define WWLAN_SET_GPIO_PULSE_COUNT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 1, 7, __value)
#define WWLAN_GET_DISABLE_UPHY(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 1)
#define WWLAN_SET_DISABLE_UPHY(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 1, __value)
#define WWLAN_GET_HST2DEV_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 9, 1)
#define WWLAN_SET_HST2DEV_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 9, 1, __value)
#define WWLAN_GET_GPIO_DURATION_MS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X04, 10, 1)
#define WWLAN_SET_GPIO_DURATION_MS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 10, 1, __value)
#define REMOTE_WAKE_CTRL_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define REMOTE_WAKE_CTRL_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define REMOTE_WAKE_CTRL_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define REMOTE_WAKE_CTRL_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 1)
#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 1, __value)
#define REMOTE_WAKE_CTRL_GET_ARP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 9, 1)
#define REMOTE_WAKE_CTRL_SET_ARP_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 9, 1, __value)
#define REMOTE_WAKE_CTRL_GET_NDP_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 10, 1)
#define REMOTE_WAKE_CTRL_SET_NDP_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 10, 1, __value)
#define REMOTE_WAKE_CTRL_GET_GTK_EN(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 11, 1)
#define REMOTE_WAKE_CTRL_SET_GTK_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 11, 1, __value)
#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 12, 1)
#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 12, 1, __value)
#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 13, 1)
#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 13, 1, __value)
#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 14, 1)
#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 14, 1, __value)
#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 15, 1)
#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 15, 1, __value)
#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 1)
#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 1, __value)
#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 17, 1)
#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 17, 1, __value)
#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 18, 1)
#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 18, 1, __value)
#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 1)
#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 1, __value)
#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 28, 1)
#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 28, 1, __value)
#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 29, 1)
#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 29, 1, __value)
#define AOAC_GLOBAL_INFO_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define AOAC_GLOBAL_INFO_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define AOAC_GLOBAL_INFO_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define AOAC_GLOBAL_INFO_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define AOAC_RSVD_PAGE_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define AOAC_RSVD_PAGE_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define AOAC_RSVD_PAGE_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define AOAC_RSVD_PAGE_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
#define AOAC_RSVD_PAGE2_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define AOAC_RSVD_PAGE2_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define AOAC_RSVD_PAGE2_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define AOAC_RSVD_PAGE2_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 0, 8)
#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 0, 8, __value)
#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 8, 8)
#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 8, 8, __value)
#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 16, 8)
#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 16, 8, __value)
#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X04, 24, 8)
#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X04, 24, 8, __value)
#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 24, 8)
#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 24, 8, __value)
#define AOAC_RSVD_PAGE3_GET_CMD_ID(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 0, 5)
#define AOAC_RSVD_PAGE3_SET_CMD_ID(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 0, 5, __value)
#define AOAC_RSVD_PAGE3_GET_CLASS(__h2c) LE_BITS_TO_4BYTE(__h2c + 0X00, 5, 3)
#define AOAC_RSVD_PAGE3_SET_CLASS(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 5, 3, __value)
#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 8, 8)
#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 8, 8, __value)
#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(__h2c) \
LE_BITS_TO_4BYTE(__h2c + 0X00, 16, 8)
#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(__h2c, __value) \
SET_BITS_TO_LE_4BYTE(__h2c + 0X00, 16, 8, __value)
#endif
drivers/staging/rtlwifi/halmac/halmac_pcie_reg.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALMAC_PCIE_REG_H__
#define __HALMAC_PCIE_REG_H__
#endif /* __HALMAC_PCIE_REG_H__ */
drivers/staging/rtlwifi/halmac/halmac_pwr_seq_cmd.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef HALMAC_POWER_SEQUENCE_CMD
#define HALMAC_POWER_SEQUENCE_CMD
#include "halmac_2_platform.h"
#include "halmac_type.h"
#define HALMAC_POLLING_READY_TIMEOUT_COUNT 20000
/* The value of cmd : 4 bits */
/* offset : the read register offset
* msk : the mask of the read value
* value : N/A, left by 0
* Note : dirver shall implement this function by read & msk
*/
#define HALMAC_PWR_CMD_READ 0x00
/*
* offset: the read register offset
* msk: the mask of the write bits
* value: write value
* Note: driver shall implement this cmd by read & msk after write
*/
#define HALMAC_PWR_CMD_WRITE 0x01
/* offset: the read register offset
* msk: the mask of the polled value
* value: the value to be polled, masked by the msd field.
* Note: driver shall implement this cmd by
* do{
* if( (Read(offset) & msk) == (value & msk) )
* break;
* } while(not timeout);
*/
#define HALMAC_PWR_CMD_POLLING 0x02
/* offset: the value to delay
* msk: N/A
* value: the unit of delay, 0: us, 1: ms
*/
#define HALMAC_PWR_CMD_DELAY 0x03
/* offset: N/A
* msk: N/A
* value: N/A
*/
#define HALMAC_PWR_CMD_END 0x04
/* The value of base : 4 bits */
/* define the base address of each block */
#define HALMAC_PWR_BASEADDR_MAC 0x00
#define HALMAC_PWR_BASEADDR_USB 0x01
#define HALMAC_PWR_BASEADDR_PCIE 0x02
#define HALMAC_PWR_BASEADDR_SDIO 0x03
/* The value of interface_msk : 4 bits */
#define HALMAC_PWR_INTF_SDIO_MSK BIT(0)
#define HALMAC_PWR_INTF_USB_MSK BIT(1)
#define HALMAC_PWR_INTF_PCI_MSK BIT(2)
#define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
/* The value of fab_msk : 4 bits */
#define HALMAC_PWR_FAB_TSMC_MSK BIT(0)
#define HALMAC_PWR_FAB_UMC_MSK BIT(1)
#define HALMAC_PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
/* The value of cut_msk : 8 bits */
#define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0)
#define HALMAC_PWR_CUT_A_MSK BIT(1)
#define HALMAC_PWR_CUT_B_MSK BIT(2)
#define HALMAC_PWR_CUT_C_MSK BIT(3)
#define HALMAC_PWR_CUT_D_MSK BIT(4)
#define HALMAC_PWR_CUT_E_MSK BIT(5)
#define HALMAC_PWR_CUT_F_MSK BIT(6)
#define HALMAC_PWR_CUT_G_MSK BIT(7)
#define HALMAC_PWR_CUT_ALL_MSK 0xFF
enum halmac_pwrseq_cmd_delay_unit_ {
HALMAC_PWRSEQ_DELAY_US,
HALMAC_PWRSEQ_DELAY_MS,
};
/*Don't care endian issue, because element of pwer seq vector is fixed address*/
struct halmac_wl_pwr_cfg_ {
u16 offset;
u8 cut_msk;
u8 fab_msk : 4;
u8 interface_msk : 4;
u8 base : 4;
u8 cmd : 4;
u8 msk;
u8 value;
};
#endif
drivers/staging/rtlwifi/halmac/halmac_reg2.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALMAC_COM_REG_H__
#define __HALMAC_COM_REG_H__
/*-------------------------Modification Log-----------------------------------
* For Page0, it is based on Combo_And_WL_Only_Page0_Reg.xls SVN524
* The supported IC are 8723A, 8881A, 8723B, 8192E, 8881A
* 8812A and 8188E is not included in page0 register
*
* For other pages, it is based on MAC_Register.doc SVN502
* Most IC is the same with 8812A
*-------------------------Modification Log-----------------------------------
*/
/*--------------------------Include File--------------------------------------*/
/*--------------------------Include File--------------------------------------*/
#define REG_SYS_ISO_CTRL 0x0000
#define REG_SDIO_TX_CTRL 0x10250000
#define REG_SYS_FUNC_EN 0x0002
#define REG_SYS_PW_CTRL 0x0004
#define REG_SYS_CLK_CTRL 0x0008
#define REG_SYS_EEPROM_CTRL 0x000A
#define REG_EE_VPD 0x000C
#define REG_SYS_SWR_CTRL1 0x0010
#define REG_SYS_SWR_CTRL2 0x0014
#define REG_SDIO_HIMR 0x10250014
#define REG_SYS_SWR_CTRL3 0x0018
#define REG_SDIO_HISR 0x10250018
#define REG_RSV_CTRL 0x001C
#define REG_SDIO_RX_REQ_LEN 0x1025001C
#define REG_RF_CTRL 0x001F
#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F
#define REG_AFE_LDO_CTRL 0x0020
#define REG_SDIO_FREE_TXPG 0x10250020
#define REG_AFE_CTRL1 0x0024
#define REG_SDIO_FREE_TXPG2 0x10250024
#define REG_AFE_CTRL2 0x0028
#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028
#define REG_AFE_CTRL3 0x002C
#define REG_EFUSE_CTRL 0x0030
#define REG_SDIO_HTSFR_INFO 0x10250030
#define REG_LDO_EFUSE_CTRL 0x0034
#define REG_PWR_OPTION_CTRL 0x0038
#define REG_SDIO_HCPWM1_V2 0x10250038
#define REG_SDIO_HCPWM2_V2 0x1025003A
#define REG_CAL_TIMER 0x003C
#define REG_ACLK_MON 0x003E
#define REG_GPIO_MUXCFG 0x0040
#define REG_SDIO_INDIRECT_REG_CFG 0x10250040
#define REG_GPIO_PIN_CTRL 0x0044
#define REG_SDIO_INDIRECT_REG_DATA 0x10250044
#define REG_GPIO_INTM 0x0048
#define REG_LED_CFG 0x004C
#define REG_FSIMR 0x0050
#define REG_FSISR 0x0054
#define REG_HSIMR 0x0058
#define REG_HSISR 0x005C
#define REG_GPIO_EXT_CTRL 0x0060
#define REG_SDIO_H2C 0x10250060
#define REG_PAD_CTRL1 0x0064
#define REG_SDIO_C2H 0x10250064
#define REG_WL_BT_PWR_CTRL 0x0068
#define REG_SDM_DEBUG 0x006C
#define REG_SYS_SDIO_CTRL 0x0070
#define REG_HCI_OPT_CTRL 0x0074
#define REG_AFE_CTRL4 0x0078
#define REG_LDO_SWR_CTRL 0x007C
#define REG_MCUFW_CTRL 0x0080
#define REG_SDIO_HRPWM1 0x10250080
#define REG_SDIO_HRPWM2 0x10250082
#define REG_MCU_TST_CFG 0x0084
#define REG_SDIO_HPS_CLKR 0x10250084
#define REG_SDIO_BUS_CTRL 0x10250085
#define REG_SDIO_HSUS_CTRL 0x10250086
#define REG_HMEBOX_E0_E1 0x0088
#define REG_SDIO_RESPONSE_TIMER 0x10250088
#define REG_SDIO_CMD_CRC 0x1025008A
#define REG_HMEBOX_E2_E3 0x008C
#define REG_WLLPS_CTRL 0x0090
#define REG_SDIO_HSISR 0x10250090
#define REG_SDIO_HSIMR 0x10250091
#define REG_AFE_CTRL5 0x0094
#define REG_GPIO_DEBOUNCE_CTRL 0x0098
#define REG_RPWM2 0x009C
#define REG_SYSON_FSM_MON 0x00A0
#define REG_AFE_CTRL6 0x00A4
#define REG_PMC_DBG_CTRL1 0x00A8
#define REG_AFE_CTRL7 0x00AC
#define REG_HIMR0 0x00B0
#define REG_HISR0 0x00B4
#define REG_HIMR1 0x00B8
#define REG_HISR1 0x00BC
#define REG_DBG_PORT_SEL 0x00C0
#define REG_SDIO_ERR_RPT 0x102500C0
#define REG_SDIO_CMD_ERRCNT 0x102500C1
#define REG_SDIO_DATA_ERRCNT 0x102500C2
#define REG_PAD_CTRL2 0x00C4
#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4
#define REG_SDIO_CRC_ERR_IDX 0x102500C9
#define REG_SDIO_DATA_CRC 0x102500CA
#define REG_SDIO_DATA_REPLY_TIME 0x102500CB
#define REG_PMC_DBG_CTRL2 0x00CC
#define REG_BIST_CTRL 0x00D0
#define REG_BIST_RPT 0x00D4
#define REG_MEM_CTRL 0x00D8
#define REG_AFE_CTRL8 0x00DC
#define REG_USB_SIE_INTF 0x00E0
#define REG_PCIE_MIO_INTF 0x00E4
#define REG_PCIE_MIO_INTD 0x00E8
#define REG_WLRF1 0x00EC
#define REG_SYS_CFG1 0x00F0
#define REG_SYS_STATUS1 0x00F4
#define REG_SYS_STATUS2 0x00F8
#define REG_SYS_CFG2 0x00FC
#define REG_CR 0x0100
#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
#define REG_TSF_CLK_STATE 0x0108
#define REG_TXDMA_PQ_MAP 0x010C
#define REG_TRXFF_BNDY 0x0114
#define REG_PTA_I2C_MBOX 0x0118
#define REG_RXFF_BNDY 0x011C
#define REG_FE1IMR 0x0120
#define REG_FE1ISR 0x0124
#define REG_CPWM 0x012C
#define REG_FWIMR 0x0130
#define REG_FWISR 0x0134
#define REG_FTIMR 0x0138
#define REG_FTISR 0x013C
#define REG_PKTBUF_DBG_CTRL 0x0140
#define REG_PKTBUF_DBG_DATA_L 0x0144
#define REG_PKTBUF_DBG_DATA_H 0x0148
#define REG_CPWM2 0x014C
#define REG_TC0_CTRL 0x0150
#define REG_TC1_CTRL 0x0154
#define REG_TC2_CTRL 0x0158
#define REG_TC3_CTRL 0x015C
#define REG_TC4_CTRL 0x0160
#define REG_TCUNIT_BASE 0x0164
#define REG_TC5_CTRL 0x0168
#define REG_TC6_CTRL 0x016C
#define REG_MBIST_FAIL 0x0170
#define REG_MBIST_START_PAUSE 0x0174
#define REG_MBIST_DONE 0x0178
#define REG_MBIST_FAIL_NRML 0x017C
#define REG_AES_DECRPT_DATA 0x0180
#define REG_AES_DECRPT_CFG 0x0184
#define REG_TMETER 0x0190
#define REG_OSC_32K_CTRL 0x0194
#define REG_32K_CAL_REG1 0x0198
#define REG_C2HEVT 0x01A0
#define REG_C2HEVT_1 0x01A4
#define REG_C2HEVT_2 0x01A8
#define REG_C2HEVT_3 0x01AC
#define REG_SW_DEFINED_PAGE1 0x01B8
#define REG_MCUTST_I 0x01C0
#define REG_MCUTST_II 0x01C4
#define REG_FMETHR 0x01C8
#define REG_HMETFR 0x01CC
#define REG_HMEBOX0 0x01D0
#define REG_HMEBOX1 0x01D4
#define REG_HMEBOX2 0x01D8
#define REG_HMEBOX3 0x01DC
#define REG_LLT_INIT 0x01E0
#define REG_LLT_INIT_ADDR 0x01E4
#define REG_BB_ACCESS_CTRL 0x01E8
#define REG_BB_ACCESS_DATA 0x01EC
#define REG_HMEBOX_E0 0x01F0
#define REG_HMEBOX_E1 0x01F4
#define REG_HMEBOX_E2 0x01F8
#define REG_HMEBOX_E3 0x01FC
#define REG_FIFOPAGE_CTRL_1 0x0200
#define REG_FIFOPAGE_CTRL_2 0x0204
#define REG_AUTO_LLT_V1 0x0208
#define REG_TXDMA_OFFSET_CHK 0x020C
#define REG_TXDMA_STATUS 0x0210
#define REG_TX_DMA_DBG 0x0214
#define REG_TQPNT1 0x0218
#define REG_TQPNT2 0x021C
#define REG_TQPNT3 0x0220
#define REG_TQPNT4 0x0224
#define REG_RQPN_CTRL_1 0x0228
#define REG_RQPN_CTRL_2 0x022C
#define REG_FIFOPAGE_INFO_1 0x0230
#define REG_FIFOPAGE_INFO_2 0x0234
#define REG_FIFOPAGE_INFO_3 0x0238
#define REG_FIFOPAGE_INFO_4 0x023C
#define REG_FIFOPAGE_INFO_5 0x0240
#define REG_H2C_HEAD 0x0244
#define REG_H2C_TAIL 0x0248
#define REG_H2C_READ_ADDR 0x024C
#define REG_H2C_WR_ADDR 0x0250
#define REG_H2C_INFO 0x0254
#define REG_RXDMA_AGG_PG_TH 0x0280
#define REG_RXPKT_NUM 0x0284
#define REG_RXDMA_STATUS 0x0288
#define REG_RXDMA_DPR 0x028C
#define REG_RXDMA_MODE 0x0290
#define REG_C2H_PKT 0x0294
#define REG_FWFF_C2H 0x0298
#define REG_FWFF_CTRL 0x029C
#define REG_FWFF_PKT_INFO 0x02A0
#define REG_PCIE_CTRL 0x0300
#define REG_INT_MIG 0x0304
#define REG_BCNQ_TXBD_DESA 0x0308
#define REG_MGQ_TXBD_DESA 0x0310
#define REG_VOQ_TXBD_DESA 0x0318
#define REG_VIQ_TXBD_DESA 0x0320
#define REG_BEQ_TXBD_DESA 0x0328
#define REG_BKQ_TXBD_DESA 0x0330
#define REG_RXQ_RXBD_DESA 0x0338
#define REG_HI0Q_TXBD_DESA 0x0340
#define REG_HI1Q_TXBD_DESA 0x0348
#define REG_HI2Q_TXBD_DESA 0x0350
#define REG_HI3Q_TXBD_DESA 0x0358
#define REG_HI4Q_TXBD_DESA 0x0360
#define REG_HI5Q_TXBD_DESA 0x0368
#define REG_HI6Q_TXBD_DESA 0x0370
#define REG_HI7Q_TXBD_DESA 0x0378
#define REG_MGQ_TXBD_NUM 0x0380
#define REG_RX_RXBD_NUM 0x0382
#define REG_VOQ_TXBD_NUM 0x0384
#define REG_VIQ_TXBD_NUM 0x0386
#define REG_BEQ_TXBD_NUM 0x0388
#define REG_BKQ_TXBD_NUM 0x038A
#define REG_HI0Q_TXBD_NUM 0x038C
#define REG_HI1Q_TXBD_NUM 0x038E
#define REG_HI2Q_TXBD_NUM 0x0390
#define REG_HI3Q_TXBD_NUM 0x0392
#define REG_HI4Q_TXBD_NUM 0x0394
#define REG_HI5Q_TXBD_NUM 0x0396
#define REG_HI6Q_TXBD_NUM 0x0398
#define REG_HI7Q_TXBD_NUM 0x039A
#define REG_TSFTIMER_HCI 0x039C
#define REG_BD_RWPTR_CLR 0x039C
#define REG_VOQ_TXBD_IDX 0x03A0
#define REG_VIQ_TXBD_IDX 0x03A4
#define REG_BEQ_TXBD_IDX 0x03A8
#define REG_BKQ_TXBD_IDX 0x03AC
#define REG_MGQ_TXBD_IDX 0x03B0
#define REG_RXQ_RXBD_IDX 0x03B4
#define REG_HI0Q_TXBD_IDX 0x03B8
#define REG_HI1Q_TXBD_IDX 0x03BC
#define REG_HI2Q_TXBD_IDX 0x03C0
#define REG_HI3Q_TXBD_IDX 0x03C4
#define REG_HI4Q_TXBD_IDX 0x03C8
#define REG_HI5Q_TXBD_IDX 0x03CC
#define REG_HI6Q_TXBD_IDX 0x03D0
#define REG_HI7Q_TXBD_IDX 0x03D4
#define REG_DBG_SEL_V1 0x03D8
#define REG_PCIE_HRPWM1_V1 0x03D9
#define REG_PCIE_HCPWM1_V1 0x03DA
#define REG_PCIE_CTRL2 0x03DB
#define REG_PCIE_HRPWM2_V1 0x03DC
#define REG_PCIE_HCPWM2_V1 0x03DE
#define REG_PCIE_H2C_MSG_V1 0x03E0
#define REG_PCIE_C2H_MSG_V1 0x03E4
#define REG_DBI_WDATA_V1 0x03E8
#define REG_DBI_RDATA_V1 0x03EC
#define REG_DBI_FLAG_V1 0x03F0
#define REG_MDIO_V1 0x03F4
#define REG_PCIE_MIX_CFG 0x03F8
#define REG_HCI_MIX_CFG 0x03FC
#define REG_Q0_INFO 0x0400
#define REG_Q1_INFO 0x0404
#define REG_Q2_INFO 0x0408
#define REG_Q3_INFO 0x040C
#define REG_MGQ_INFO 0x0410
#define REG_HIQ_INFO 0x0414
#define REG_BCNQ_INFO 0x0418
#define REG_TXPKT_EMPTY 0x041A
#define REG_CPU_MGQ_INFO 0x041C
#define REG_FWHW_TXQ_CTRL 0x0420
#define REG_DATAFB_SEL 0x0423
#define REG_BCNQ_BDNY_V1 0x0424
#define REG_LIFETIME_EN 0x0426
#define REG_SPEC_SIFS 0x0428
#define REG_RETRY_LIMIT 0x042A
#define REG_TXBF_CTRL 0x042C
#define REG_DARFRC 0x0430
#define REG_RARFRC 0x0438
#define REG_RRSR 0x0440
#define REG_ARFR0 0x0444
#define REG_ARFR1_V1 0x044C
#define REG_CCK_CHECK 0x0454
#define REG_AMPDU_MAX_TIME_V1 0x0455
#define REG_BCNQ1_BDNY_V1 0x0456
#define REG_AMPDU_MAX_LENGTH 0x0458
#define REG_ACQ_STOP 0x045C
#define REG_NDPA_RATE 0x045D
#define REG_TX_HANG_CTRL 0x045E
#define REG_NDPA_OPT_CTRL 0x045F
#define REG_RD_RESP_PKT_TH 0x0463
#define REG_CMDQ_INFO 0x0464
#define REG_Q4_INFO 0x0468
#define REG_Q5_INFO 0x046C
#define REG_Q6_INFO 0x0470
#define REG_Q7_INFO 0x0474
#define REG_WMAC_LBK_BUF_HD_V1 0x0478
#define REG_MGQ_BDNY_V1 0x047A
#define REG_TXRPT_CTRL 0x047C
#define REG_INIRTS_RATE_SEL 0x0480
#define REG_BASIC_CFEND_RATE 0x0481
#define REG_STBC_CFEND_RATE 0x0482
#define REG_DATA_SC 0x0483
#define REG_MACID_SLEEP3 0x0484
#define REG_MACID_SLEEP1 0x0488
#define REG_ARFR2_V1 0x048C
#define REG_ARFR3_V1 0x0494
#define REG_ARFR4 0x049C
#define REG_ARFR5 0x04A4
#define REG_TXRPT_START_OFFSET 0x04AC
#define REG_POWER_STAGE1 0x04B4
#define REG_POWER_STAGE2 0x04B8
#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
#define REG_PKT_LIFE_TIME 0x04C0
#define REG_STBC_SETTING 0x04C4
#define REG_STBC_SETTING2 0x04C5
#define REG_QUEUE_CTRL 0x04C6
#define REG_SINGLE_AMPDU_CTRL 0x04C7
#define REG_PROT_MODE_CTRL 0x04C8
#define REG_BAR_MODE_CTRL 0x04CC
#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
#define REG_MACID_SLEEP2 0x04D0
#define REG_MACID_SLEEP 0x04D4
#define REG_HW_SEQ0 0x04D8
#define REG_HW_SEQ1 0x04DA
#define REG_HW_SEQ2 0x04DC
#define REG_HW_SEQ3 0x04DE
#define REG_NULL_PKT_STATUS_V1 0x04E0
#define REG_PTCL_ERR_STATUS 0x04E2
#define REG_NULL_PKT_STATUS_EXTEND 0x04E3
#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4
#define REG_BT_POLLUTE_PKT_CNT 0x04E8
#define REG_PTCL_DBG 0x04EC
#define REG_CPUMGQ_TIMER_CTRL2 0x04F4
#define REG_DUMMY_PAGE4_V1 0x04FC
#define REG_MOREDATA 0x04FE
#define REG_EDCA_VO_PARAM 0x0500
#define REG_EDCA_VI_PARAM 0x0504
#define REG_EDCA_BE_PARAM 0x0508
#define REG_EDCA_BK_PARAM 0x050C
#define REG_BCNTCFG 0x0510
#define REG_PIFS 0x0512
#define REG_RDG_PIFS 0x0513
#define REG_SIFS 0x0514
#define REG_TSFTR_SYN_OFFSET 0x0518
#define REG_AGGR_BREAK_TIME 0x051A
#define REG_SLOT 0x051B
#define REG_TX_PTCL_CTRL 0x0520
#define REG_TXPAUSE 0x0522
#define REG_DIS_TXREQ_CLR 0x0523
#define REG_RD_CTRL 0x0524
#define REG_MBSSID_CTRL 0x0526
#define REG_P2PPS_CTRL 0x0527
#define REG_PKT_LIFETIME_CTRL 0x0528
#define REG_P2PPS_SPEC_STATE 0x052B
#define REG_BAR_TX_CTRL 0x0530
#define REG_QUEUE_INCOL_THR 0x0538
#define REG_QUEUE_INCOL_EN 0x053C
#define REG_TBTT_PROHIBIT 0x0540
#define REG_P2PPS_STATE 0x0543
#define REG_RD_NAV_NXT 0x0544
#define REG_NAV_PROT_LEN 0x0546
#define REG_BCN_CTRL 0x0550
#define REG_BCN_CTRL_CLINT0 0x0551
#define REG_MBID_NUM 0x0552
#define REG_DUAL_TSF_RST 0x0553
#define REG_MBSSID_BCN_SPACE 0x0554
#define REG_DRVERLYINT 0x0558
#define REG_BCNDMATIM 0x0559
#define REG_ATIMWND 0x055A
#define REG_USTIME_TSF 0x055C
#define REG_BCN_MAX_ERR 0x055D
#define REG_RXTSF_OFFSET_CCK 0x055E
#define REG_RXTSF_OFFSET_OFDM 0x055F
#define REG_TSFTR 0x0560
#define REG_FREERUN_CNT 0x0568
#define REG_ATIMWND1_V1 0x0570
#define REG_TBTT_PROHIBIT_INFRA 0x0571
#define REG_CTWND 0x0572
#define REG_BCNIVLCUNT 0x0573
#define REG_BCNDROPCTRL 0x0574
#define REG_HGQ_TIMEOUT_PERIOD 0x0575
#define REG_TXCMD_TIMEOUT_PERIOD 0x0576
#define REG_MISC_CTRL 0x0577
#define REG_BCN_CTRL_CLINT1 0x0578
#define REG_BCN_CTRL_CLINT2 0x0579
#define REG_BCN_CTRL_CLINT3 0x057A
#define REG_EXTEND_CTRL 0x057B
#define REG_P2PPS1_SPEC_STATE 0x057C
#define REG_P2PPS1_STATE 0x057D
#define REG_P2PPS2_SPEC_STATE 0x057E
#define REG_P2PPS2_STATE 0x057F
#define REG_PS_TIMER0 0x0580
#define REG_PS_TIMER1 0x0584
#define REG_PS_TIMER2 0x0588
#define REG_TBTT_CTN_AREA 0x058C
#define REG_FORCE_BCN_IFS 0x058E
#define REG_TXOP_MIN 0x0590
#define REG_PRE_BKF_TIME 0x0592
#define REG_CROSS_TXOP_CTRL 0x0593
#define REG_ATIMWND2 0x05A0
#define REG_ATIMWND3 0x05A1
#define REG_ATIMWND4 0x05A2
#define REG_ATIMWND5 0x05A3
#define REG_ATIMWND6 0x05A4
#define REG_ATIMWND7 0x05A5
#define REG_ATIMUGT 0x05A6
#define REG_HIQ_NO_LMT_EN 0x05A7
#define REG_DTIM_COUNTER_ROOT 0x05A8
#define REG_DTIM_COUNTER_VAP1 0x05A9
#define REG_DTIM_COUNTER_VAP2 0x05AA
#define REG_DTIM_COUNTER_VAP3 0x05AB
#define REG_DTIM_COUNTER_VAP4 0x05AC
#define REG_DTIM_COUNTER_VAP5 0x05AD
#define REG_DTIM_COUNTER_VAP6 0x05AE
#define REG_DTIM_COUNTER_VAP7 0x05AF
#define REG_DIS_ATIM 0x05B0
#define REG_EARLY_128US 0x05B1
#define REG_P2PPS1_CTRL 0x05B2
#define REG_P2PPS2_CTRL 0x05B3
#define REG_TIMER0_SRC_SEL 0x05B4
#define REG_NOA_UNIT_SEL 0x05B5
#define REG_P2POFF_DIS_TXTIME 0x05B7
#define REG_MBSSID_BCN_SPACE2 0x05B8
#define REG_MBSSID_BCN_SPACE3 0x05BC
#define REG_ACMHWCTRL 0x05C0
#define REG_ACMRSTCTRL 0x05C1
#define REG_ACMAVG 0x05C2
#define REG_VO_ADMTIME 0x05C4
#define REG_VI_ADMTIME 0x05C6
#define REG_BE_ADMTIME 0x05C8
#define REG_EDCA_RANDOM_GEN 0x05CC
#define REG_TXCMD_NOA_SEL 0x05CF
#define REG_NOA_PARAM 0x05E0
#define REG_P2P_RST 0x05F0
#define REG_SCHEDULER_RST 0x05F1
#define REG_SCH_TXCMD 0x05F8
#define REG_PAGE5_DUMMY 0x05FC
#define REG_WMAC_CR 0x0600
#define REG_WMAC_FWPKT_CR 0x0601
#define REG_BWOPMODE 0x0603
#define REG_TCR 0x0604
#define REG_RCR 0x0608
#define REG_RX_PKT_LIMIT 0x060C
#define REG_RX_DLK_TIME 0x060D
#define REG_RX_DRVINFO_SZ 0x060F
#define REG_MACID 0x0610
#define REG_BSSID 0x0618
#define REG_MAR 0x0620
#define REG_MBIDCAMCFG_1 0x0628
#define REG_MBIDCAMCFG_2 0x062C
#define REG_WMAC_TCR_TSFT_OFS 0x0630
#define REG_UDF_THSD 0x0632
#define REG_ZLD_NUM 0x0633
#define REG_STMP_THSD 0x0634
#define REG_WMAC_TXTIMEOUT 0x0635
#define REG_MCU_TEST_2_V1 0x0636
#define REG_USTIME_EDCA 0x0638
#define REG_MAC_SPEC_SIFS 0x063A
#define REG_RESP_SIFS_CCK 0x063C
#define REG_RESP_SIFS_OFDM 0x063E
#define REG_ACKTO 0x0640
#define REG_CTS2TO 0x0641
#define REG_EIFS 0x0642
#define REG_NAV_CTRL 0x0650
#define REG_BACAMCMD 0x0654
#define REG_BACAMCONTENT 0x0658
#define REG_LBDLY 0x0660
#define REG_WMAC_BACAM_RPMEN 0x0661
#define REG_TX_RX 0x0662
#define REG_WMAC_BITMAP_CTL 0x0663
#define REG_RXERR_RPT 0x0664
#define REG_WMAC_TRXPTCL_CTL 0x0668
#define REG_CAMCMD 0x0670
#define REG_CAMWRITE 0x0674
#define REG_CAMREAD 0x0678
#define REG_CAMDBG 0x067C
#define REG_SECCFG 0x0680
#define REG_RXFILTER_CATEGORY_1 0x0682
#define REG_RXFILTER_ACTION_1 0x0683
#define REG_RXFILTER_CATEGORY_2 0x0684
#define REG_RXFILTER_ACTION_2 0x0685
#define REG_RXFILTER_CATEGORY_3 0x0686
#define REG_RXFILTER_ACTION_3 0x0687
#define REG_RXFLTMAP3 0x0688
#define REG_RXFLTMAP4 0x068A
#define REG_RXFLTMAP5 0x068C
#define REG_RXFLTMAP6 0x068E
#define REG_WOW_CTRL 0x0690
#define REG_NAN_RX_TSF_FILTER 0x0691
#define REG_PS_RX_INFO 0x0692
#define REG_WMMPS_UAPSD_TID 0x0693
#define REG_LPNAV_CTRL 0x0694
#define REG_WKFMCAM_CMD 0x0698
#define REG_WKFMCAM_RWD 0x069C
#define REG_RXFLTMAP0 0x06A0
#define REG_RXFLTMAP1 0x06A2
#define REG_RXFLTMAP 0x06A4
#define REG_BCN_PSR_RPT 0x06A8
#define REG_FLC_RPC 0x06AC
#define REG_FLC_RPCT 0x06AD
#define REG_FLC_PTS 0x06AE
#define REG_FLC_TRPC 0x06AF
#define REG_RXPKTMON_CTRL 0x06B0
#define REG_STATE_MON 0x06B4
#define REG_ERROR_MON 0x06B8
#define REG_SEARCH_MACID 0x06BC
#define REG_BT_COEX_TABLE 0x06C0
#define REG_RXCMD_0 0x06D0
#define REG_RXCMD_1 0x06D4
#define REG_WMAC_RESP_TXINFO 0x06D8
#define REG_BBPSF_CTRL 0x06DC
#define REG_P2P_RX_BCN_NOA 0x06E0
#define REG_ASSOCIATED_BFMER0_INFO 0x06E4
#define REG_ASSOCIATED_BFMER1_INFO 0x06EC
#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4
#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8
#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC
#define REG_MACID1 0x0700
#define REG_BSSID1 0x0708
#define REG_BCN_PSR_RPT1 0x0710
#define REG_ASSOCIATED_BFMEE_SEL 0x0714
#define REG_SND_PTCL_CTRL 0x0718
#define REG_RX_CSI_RPT_INFO 0x071C
#define REG_NS_ARP_CTRL 0x0720
#define REG_NS_ARP_INFO 0x0724
#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728
#define REG_BEAMFORMING_INFO_NSARP 0x072C
#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750
#define REG_WMAC_SWAES_CFG 0x0760
#define REG_BT_COEX_V2 0x0762
#define REG_BT_COEX 0x0764
#define REG_WLAN_ACT_MASK_CTRL 0x0768
#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E
#define REG_BT_ACT_STATISTICS 0x0770
#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778
#define REG_BT_STATUS_REPORT_REGISTER 0x077C
#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780
#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785
#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F
#define REG_BT_TDMA_TIME_REGISTER 0x0790
#define REG_BT_ACT_REGISTER 0x0794
#define REG_OBFF_CTRL_BASIC 0x0798
#define REG_OBFF_CTRL2_TIMER 0x079C
#define REG_LTR_CTRL_BASIC 0x07A0
#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4
#define REG_LTR_IDLE_LATENCY_V1 0x07A8
#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC
#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0
#define REG_WMAC_PKTCNT_RWD 0x07B8
#define REG_WMAC_PKTCNT_CTRL 0x07BC
#define REG_IQ_DUMP 0x07C0
#define REG_WMAC_FTM_CTL 0x07CC
#define REG_WMAC_IQ_MDPK_FUNC 0x07CE
#define REG_WMAC_OPTION_FUNCTION 0x07D0
#define REG_RX_FILTER_FUNCTION 0x07DA
#define REG_NDP_SIG 0x07E0
#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4
#define REG_RTS_ADDRESS_0 0x07F0
#define REG_RTS_ADDRESS_1 0x07F8
#define REG__RPFM_MAP1 0x07FE
#define REG_SYS_CFG3 0x1000
#define REG_SYS_CFG4 0x1034
#define REG_SYS_CFG5 0x1070
#define REG_CPU_DMEM_CON 0x1080
#define REG_BOOT_REASON 0x1088
#define REG_NFCPAD_CTRL 0x10A8
#define REG_HIMR2 0x10B0
#define REG_HISR2 0x10B4
#define REG_HIMR3 0x10B8
#define REG_HISR3 0x10BC
#define REG_SW_MDIO 0x10C0
#define REG_SW_FLUSH 0x10C4
#define REG_H2C_PKT_READADDR 0x10D0
#define REG_H2C_PKT_WRITEADDR 0x10D4
#define REG_MEM_PWR_CRTL 0x10D8
#define REG_FW_DBG0 0x10E0
#define REG_FW_DBG1 0x10E4
#define REG_FW_DBG2 0x10E8
#define REG_FW_DBG3 0x10EC
#define REG_FW_DBG4 0x10F0
#define REG_FW_DBG5 0x10F4
#define REG_FW_DBG6 0x10F8
#define REG_FW_DBG7 0x10FC
#define REG_CR_EXT 0x1100
#define REG_FWFF 0x1114
#define REG_RXFF_PTR_V1 0x1118
#define REG_RXFF_WTR_V1 0x111C
#define REG_FE2IMR 0x1120
#define REG_FE2ISR 0x1124
#define REG_FE3IMR 0x1128
#define REG_FE3ISR 0x112C
#define REG_FE4IMR 0x1130
#define REG_FE4ISR 0x1134
#define REG_FT1IMR 0x1138
#define REG_FT1ISR 0x113C
#define REG_SPWR0 0x1140
#define REG_SPWR1 0x1144
#define REG_SPWR2 0x1148
#define REG_SPWR3 0x114C
#define REG_POWSEQ 0x1150
#define REG_TC7_CTRL_V1 0x1158
#define REG_TC8_CTRL_V1 0x115C
#define REG_FT2IMR 0x11E0
#define REG_FT2ISR 0x11E4
#define REG_MSG2 0x11F0
#define REG_MSG3 0x11F4
#define REG_MSG4 0x11F8
#define REG_MSG5 0x11FC
#define REG_DDMA_CH0SA 0x1200
#define REG_DDMA_CH0DA 0x1204
#define REG_DDMA_CH0CTRL 0x1208
#define REG_DDMA_CH1SA 0x1210
#define REG_DDMA_CH1DA 0x1214
#define REG_DDMA_CH1CTRL 0x1218
#define REG_DDMA_CH2SA 0x1220
#define REG_DDMA_CH2DA 0x1224
#define REG_DDMA_CH2CTRL 0x1228
#define REG_DDMA_CH3SA 0x1230
#define REG_DDMA_CH3DA 0x1234
#define REG_DDMA_CH3CTRL 0x1238
#define REG_DDMA_CH4SA 0x1240
#define REG_DDMA_CH4DA 0x1244
#define REG_DDMA_CH4CTRL 0x1248
#define REG_DDMA_CH5SA 0x1250
#define REG_DDMA_CH5DA 0x1254
#define REG_REG_DDMA_CH5CTRL 0x1258
#define REG_DDMA_INT_MSK 0x12E0
#define REG_DDMA_CHSTATUS 0x12E8
#define REG_DDMA_CHKSUM 0x12F0
#define REG_DDMA_MONITOR 0x12FC
#define REG_STC_INT_CS 0x1300
#define REG_ST_INT_CFG 0x1304
#define REG_CMU_DLY_CTRL 0x1310
#define REG_CMU_DLY_CFG 0x1314
#define REG_H2CQ_TXBD_DESA 0x1320
#define REG_H2CQ_TXBD_NUM 0x1328
#define REG_H2CQ_TXBD_IDX 0x132C
#define REG_H2CQ_CSR 0x1330
#define REG_CHANGE_PCIE_SPEED 0x1350
#define REG_OLD_DEHANG 0x13F4
#define REG_Q0_Q1_INFO 0x1400
#define REG_Q2_Q3_INFO 0x1404
#define REG_Q4_Q5_INFO 0x1408
#define REG_Q6_Q7_INFO 0x140C
#define REG_MGQ_HIQ_INFO 0x1410
#define REG_CMDQ_BCNQ_INFO 0x1414
#define REG_USEREG_SETTING 0x1420
#define REG_AESIV_SETTING 0x1424
#define REG_BF0_TIME_SETTING 0x1428
#define REG_BF1_TIME_SETTING 0x142C
#define REG_BF_TIMEOUT_EN 0x1430
#define REG_MACID_RELEASE0 0x1434
#define REG_MACID_RELEASE1 0x1438
#define REG_MACID_RELEASE2 0x143C
#define REG_MACID_RELEASE3 0x1440
#define REG_MACID_RELEASE_SETTING 0x1444
#define REG_FAST_EDCA_VOVI_SETTING 0x1448
#define REG_FAST_EDCA_BEBK_SETTING 0x144C
#define REG_MACID_DROP0 0x1450
#define REG_MACID_DROP1 0x1454
#define REG_MACID_DROP2 0x1458
#define REG_MACID_DROP3 0x145C
#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460
#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464
#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468
#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C
#define REG_MGG_FIFO_CRTL 0x1470
#define REG_MGG_FIFO_INT 0x1474
#define REG_MGG_FIFO_LIFETIME 0x1478
#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C
#define REG_MACID_SHCUT_OFFSET 0x1480
#define REG_MU_TX_CTL 0x14C0
#define REG_MU_STA_GID_VLD 0x14C4
#define REG_MU_STA_USER_POS_INFO 0x14C8
#define REG_MU_TRX_DBG_CNT 0x14D0
#define REG_CPUMGQ_TX_TIMER 0x1500
#define REG_PS_TIMER_A 0x1504
#define REG_PS_TIMER_B 0x1508
#define REG_PS_TIMER_C 0x150C
#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510
#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514
#define REG_PS_TIMER_A_EARLY 0x1515
#define REG_PS_TIMER_B_EARLY 0x1516
#define REG_PS_TIMER_C_EARLY 0x1517
#define REG_BCN_PSR_RPT2 0x1600
#define REG_BCN_PSR_RPT3 0x1604
#define REG_BCN_PSR_RPT4 0x1608
#define REG_A1_ADDR_MASK 0x160C
#define REG_MACID2 0x1620
#define REG_BSSID2 0x1628
#define REG_MACID3 0x1630
#define REG_BSSID3 0x1638
#define REG_MACID4 0x1640
#define REG_BSSID4 0x1648
#define REG_NOA_REPORT 0x1650
#define REG_PWRBIT_SETTING 0x1660
#define REG_WMAC_MU_BF_OPTION 0x167C
#define REG_WMAC_MU_ARB 0x167E
#define REG_WMAC_MU_OPTION 0x167F
#define REG_WMAC_MU_BF_CTL 0x1680
#define REG_WMAC_MU_BFRPT_PARA 0x1682
#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684
#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686
#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688
#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A
#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C
#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E
#define REG_TRANSMIT_ADDRSS_0 0x16A0
#define REG_TRANSMIT_ADDRSS_1 0x16A8
#define REG_TRANSMIT_ADDRSS_2 0x16B0
#define REG_TRANSMIT_ADDRSS_3 0x16B8
#define REG_TRANSMIT_ADDRSS_4 0x16C0
#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700
#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708
/* ----------------------------------------------------- */
/* */
/* 0xFB00h ~ 0xFCFFh TX/RX packet buffer affress */
/* */
/* ----------------------------------------------------- */
#define REG_RXPKTBUF_STARTADDR 0xFB00
#define REG_TXPKTBUF_STARTADDR 0xFC00
/* ----------------------------------------------------- */
/* */
/* 0xFD00h ~ 0xFDFFh 8051 CPU Local REG */
/* */
/* ----------------------------------------------------- */
#define REG_SYS_CTRL 0xFD00
#define REG_PONSTS_RPT1 0xFD01
#define REG_PONSTS_RPT2 0xFD02
#define REG_PONSTS_RPT3 0xFD03
#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */
#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */
#define REG_8051ERRFLAG 0xFD08
#define REG_8051ERRFLAG_MASK 0xFD09
#define REG_TXADDRH 0xFD10 /* Tx Packet High address */
#define REG_RXADDRH 0xFD11 /* Rx Packet High address */
#define REG_TXADDRH_EXT 0xFD12 /* 0xFD12[0] : for 8051 access txpktbuf
* high64k as external register
*/
#define REG_U3_STATE 0xFD48 /* (Read only)
* [7:4] : usb3 changed last state.
* [3:0] : usb3 state
*/
/* for MAILBOX */
#define REG_OUTDATA0 0xFD50
#define REG_OUTDATA1 0xFD54
#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady,
* bit[1] : OutEmptyIntEn
*/
#define REG_INDATA0 0xFD60
#define REG_INDATA1 0xFD64
#define REG_INRDY 0xFD68 /* bit[0] : InReady,
* bit[1] : InRdyIntEn
*/
/* MCU ERROR debug REG */
#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */
#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */
#define REG_MCUERR_ACC 0xFD92
#define REG_MCUERR_B 0xFD93
#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */
#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */
#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */
#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */
#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */
#define REG_VERA_SIM 0xFD9F
/* 0xFD99~0xFD9F are reserved.. */
/* ----------------------------------------------------- */
/* */
/* 0xFE00h ~ 0xFEFFh USB Configuration */
/* */
/* ----------------------------------------------------- */
/* RTS5101 USB Register Definition */
#define REG_USB_SETUP_DEC_INT 0xFE00
#define REG_USB_DMACTL 0xFE01
#define REG_USB_IRQSTAT0 0xFE02
#define REG_USB_IRQSTAT1 0xFE03
#define REG_USB_IRQEN0 0xFE04
#define REG_USB_IRQEN1 0xFE05
#define REG_USB_AUTOPTRL 0xFE06
#define REG_USB_AUTOPTRH 0xFE07
#define REG_USB_AUTODAT 0xFE08
#define REG_USB_SCRATCH0 0xFE09
#define REG_USB_SCRATCH1 0xFE0A
#define REG_USB_SEEPROM 0xFE0B
#define REG_USB_GPIO0 0xFE0C
#define REG_USB_GPIO0DIR 0xFE0D
#define REG_USB_CLKSEL 0xFE0E
#define REG_USB_BOOTCTL 0xFE0F
#define REG_USB_USBCTL 0xFE10
#define REG_USB_USBSTAT 0xFE11
#define REG_USB_DEVADDR 0xFE12
#define REG_USB_USBTEST 0xFE13
#define REG_USB_FNUM0 0xFE14
#define REG_USB_FNUM1 0xFE15
#define REG_USB_EP_IDX 0xFE20
#define REG_USB_EP_CFG 0xFE21
#define REG_USB_EP_CTL 0xFE22
#define REG_USB_EP_STAT 0xFE23
#define REG_USB_EP_IRQ 0xFE24
#define REG_USB_EP_IRQEN 0xFE25
#define REG_USB_EP_MAXPKT0 0xFE26
#define REG_USB_EP_MAXPKT1 0xFE27
#define REG_USB_EP_DAT 0xFE28
#define REG_USB_EP_BC0 0xFE29
#define REG_USB_EP_BC1 0xFE2A
#define REG_USB_EP_TC0 0xFE2B
#define REG_USB_EP_TC1 0xFE2C
#define REG_USB_EP_TC2 0xFE2D
#define REG_USB_EP_CTL2 0xFE2E
#define REG_USB_INFO 0xFE17
#define REG_USB_SPECIAL_OPTION 0xFE55
#define REG_USB_DMA_AGG_TO 0xFE5B
#define REG_USB_AGG_TO 0xFE5C
#define REG_USB_AGG_TH 0xFE5D
#define REG_USB_VID 0xFE60
#define REG_USB_PID 0xFE62
#define REG_USB_OPT 0xFE64
#define REG_USB_CONFIG 0xFE65 /* RX EP setting.
* 0xFE65 Bit[3:0] : RXQ,
* Bit[7:4] : INTQ
*/
/* TX EP setting.
* 0xFE66 Bit[3:0] : TXQ0,
* Bit[7:4] : TXQ1,
* 0xFE67 Bit[3:0] : TXQ2
*/
#define REG_USB_PHY_PARA1 0xFE68 /* Bit[7:4]: XCVR_SEN (USB PHY 0xE2[7:4]),
* Bit[3:0]: XCVR_SH (USB PHY 0xE2[3:0])
*/
#define REG_USB_PHY_PARA2 0xFE69 /* Bit[7:5]: XCVR_BG (USB PHY 0xE3[5:3]),
* Bit[4:2]: XCVR_DR (USB PHY 0xE3[2:0]),
* Bit[1]: SE0_LVL (USB PHY 0xE5[7]),
* Bit[0]: FORCE_XTL_ON (USB PHY 0xE5[1])
*/
#define REG_USB_PHY_PARA3 0xFE6A /* Bit[7:5]: XCVR_SRC (USB PHY 0xE5[4:2]),
* Bit[4]: LATE_DLLEN (USB PHY 0xF0[4]),
* Bit[3]: HS_LP_MODE (USB PHY 0xF0[3]),
* Bit[2]: UTMI_POS_OUT (USB PHY 0xF1 [7]),
* Bit[1:0]: TX_DELAY (USB PHY 0xF1 [2:1])
*/
#define REG_USB_PHY_PARA4 0xFE6B /* (USB PHY 0xE7[7:0]) */
#define REG_USB_OPT2 0xFE6C
#define REG_USB_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */
#define REG_USB_MANUFACTURE_SETTING 0xFE80 /* 0xFE80~0xFE90 Max: 32 bytes*/
#define REG_USB_PRODUCT_STRING 0xFEA0 /* 0xFEA0~0xFECF Max: 48 bytes*/
#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 /* 0xFED0~0xFEDF Max: 12 bytes*/
#define REG_USB_ALTERNATE_SETTING 0xFE4F
#define REG_USB_INT_BINTERVAL 0xFE6E
#define REG_USB_GPS_EP_CONFIG 0xFE6D
#endif /* __HALMAC_COM_REG_H__ */
drivers/staging/rtlwifi/halmac/halmac_reg_8822b.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_HALMAC_REG_8822B_H
#define __INC_HALMAC_REG_8822B_H
#define REG_SYS_ISO_CTRL_8822B 0x0000
#define REG_SYS_FUNC_EN_8822B 0x0002
#define REG_SYS_PW_CTRL_8822B 0x0004
#define REG_SYS_CLK_CTRL_8822B 0x0008
#define REG_SYS_EEPROM_CTRL_8822B 0x000A
#define REG_EE_VPD_8822B 0x000C
#define REG_SYS_SWR_CTRL1_8822B 0x0010
#define REG_SYS_SWR_CTRL2_8822B 0x0014
#define REG_SYS_SWR_CTRL3_8822B 0x0018
#define REG_RSV_CTRL_8822B 0x001C
#define REG_RF_CTRL_8822B 0x001F
#define REG_AFE_LDO_CTRL_8822B 0x0020
#define REG_AFE_CTRL1_8822B 0x0024
#define REG_AFE_CTRL2_8822B 0x0028
#define REG_AFE_CTRL3_8822B 0x002C
#define REG_EFUSE_CTRL_8822B 0x0030
#define REG_LDO_EFUSE_CTRL_8822B 0x0034
#define REG_PWR_OPTION_CTRL_8822B 0x0038
#define REG_CAL_TIMER_8822B 0x003C
#define REG_ACLK_MON_8822B 0x003E
#define REG_GPIO_MUXCFG_8822B 0x0040
#define REG_GPIO_PIN_CTRL_8822B 0x0044
#define REG_GPIO_INTM_8822B 0x0048
#define REG_LED_CFG_8822B 0x004C
#define REG_FSIMR_8822B 0x0050
#define REG_FSISR_8822B 0x0054
#define REG_HSIMR_8822B 0x0058
#define REG_HSISR_8822B 0x005C
#define REG_GPIO_EXT_CTRL_8822B 0x0060
#define REG_PAD_CTRL1_8822B 0x0064
#define REG_WL_BT_PWR_CTRL_8822B 0x0068
#define REG_SDM_DEBUG_8822B 0x006C
#define REG_SYS_SDIO_CTRL_8822B 0x0070
#define REG_HCI_OPT_CTRL_8822B 0x0074
#define REG_AFE_CTRL4_8822B 0x0078
#define REG_LDO_SWR_CTRL_8822B 0x007C
#define REG_MCUFW_CTRL_8822B 0x0080
#define REG_MCU_TST_CFG_8822B 0x0084
#define REG_HMEBOX_E0_E1_8822B 0x0088
#define REG_HMEBOX_E2_E3_8822B 0x008C
#define REG_WLLPS_CTRL_8822B 0x0090
#define REG_AFE_CTRL5_8822B 0x0094
#define REG_GPIO_DEBOUNCE_CTRL_8822B 0x0098
#define REG_RPWM2_8822B 0x009C
#define REG_SYSON_FSM_MON_8822B 0x00A0
#define REG_AFE_CTRL6_8822B 0x00A4
#define REG_PMC_DBG_CTRL1_8822B 0x00A8
#define REG_AFE_CTRL7_8822B 0x00AC
#define REG_HIMR0_8822B 0x00B0
#define REG_HISR0_8822B 0x00B4
#define REG_HIMR1_8822B 0x00B8
#define REG_HISR1_8822B 0x00BC
#define REG_DBG_PORT_SEL_8822B 0x00C0
#define REG_PAD_CTRL2_8822B 0x00C4
#define REG_PMC_DBG_CTRL2_8822B 0x00CC
#define REG_BIST_CTRL_8822B 0x00D0
#define REG_BIST_RPT_8822B 0x00D4
#define REG_MEM_CTRL_8822B 0x00D8
#define REG_AFE_CTRL8_8822B 0x00DC
#define REG_USB_SIE_INTF_8822B 0x00E0
#define REG_PCIE_MIO_INTF_8822B 0x00E4
#define REG_PCIE_MIO_INTD_8822B 0x00E8
#define REG_WLRF1_8822B 0x00EC
#define REG_SYS_CFG1_8822B 0x00F0
#define REG_SYS_STATUS1_8822B 0x00F4
#define REG_SYS_STATUS2_8822B 0x00F8
#define REG_SYS_CFG2_8822B 0x00FC
#define REG_SYS_CFG3_8822B 0x1000
#define REG_SYS_CFG4_8822B 0x1034
#define REG_SYS_CFG5_8822B 0x1070
#define REG_CPU_DMEM_CON_8822B 0x1080
#define REG_BOOT_REASON_8822B 0x1088
#define REG_NFCPAD_CTRL_8822B 0x10A8
#define REG_HIMR2_8822B 0x10B0
#define REG_HISR2_8822B 0x10B4
#define REG_HIMR3_8822B 0x10B8
#define REG_HISR3_8822B 0x10BC
#define REG_SW_MDIO_8822B 0x10C0
#define REG_SW_FLUSH_8822B 0x10C4
#define REG_H2C_PKT_READADDR_8822B 0x10D0
#define REG_H2C_PKT_WRITEADDR_8822B 0x10D4
#define REG_MEM_PWR_CRTL_8822B 0x10D8
#define REG_FW_DBG0_8822B 0x10E0
#define REG_FW_DBG1_8822B 0x10E4
#define REG_FW_DBG2_8822B 0x10E8
#define REG_FW_DBG3_8822B 0x10EC
#define REG_FW_DBG4_8822B 0x10F0
#define REG_FW_DBG5_8822B 0x10F4
#define REG_FW_DBG6_8822B 0x10F8
#define REG_FW_DBG7_8822B 0x10FC
#define REG_CR_8822B 0x0100
#define REG_PKT_BUFF_ACCESS_CTRL_8822B 0x0106
#define REG_TSF_CLK_STATE_8822B 0x0108
#define REG_TXDMA_PQ_MAP_8822B 0x010C
#define REG_TRXFF_BNDY_8822B 0x0114
#define REG_PTA_I2C_MBOX_8822B 0x0118
#define REG_RXFF_BNDY_8822B 0x011C
#define REG_FE1IMR_8822B 0x0120
#define REG_FE1ISR_8822B 0x0124
#define REG_CPWM_8822B 0x012C
#define REG_FWIMR_8822B 0x0130
#define REG_FWISR_8822B 0x0134
#define REG_FTIMR_8822B 0x0138
#define REG_FTISR_8822B 0x013C
#define REG_PKTBUF_DBG_CTRL_8822B 0x0140
#define REG_PKTBUF_DBG_DATA_L_8822B 0x0144
#define REG_PKTBUF_DBG_DATA_H_8822B 0x0148
#define REG_CPWM2_8822B 0x014C
#define REG_TC0_CTRL_8822B 0x0150
#define REG_TC1_CTRL_8822B 0x0154
#define REG_TC2_CTRL_8822B 0x0158
#define REG_TC3_CTRL_8822B 0x015C
#define REG_TC4_CTRL_8822B 0x0160
#define REG_TCUNIT_BASE_8822B 0x0164
#define REG_TC5_CTRL_8822B 0x0168
#define REG_TC6_CTRL_8822B 0x016C
#define REG_MBIST_FAIL_8822B 0x0170
#define REG_MBIST_START_PAUSE_8822B 0x0174
#define REG_MBIST_DONE_8822B 0x0178
#define REG_MBIST_FAIL_NRML_8822B 0x017C
#define REG_AES_DECRPT_DATA_8822B 0x0180
#define REG_AES_DECRPT_CFG_8822B 0x0184
#define REG_TMETER_8822B 0x0190
#define REG_OSC_32K_CTRL_8822B 0x0194
#define REG_32K_CAL_REG1_8822B 0x0198
#define REG_C2HEVT_8822B 0x01A0
#define REG_SW_DEFINED_PAGE1_8822B 0x01B8
#define REG_MCUTST_I_8822B 0x01C0
#define REG_MCUTST_II_8822B 0x01C4
#define REG_FMETHR_8822B 0x01C8
#define REG_HMETFR_8822B 0x01CC
#define REG_HMEBOX0_8822B 0x01D0
#define REG_HMEBOX1_8822B 0x01D4
#define REG_HMEBOX2_8822B 0x01D8
#define REG_HMEBOX3_8822B 0x01DC
#define REG_LLT_INIT_8822B 0x01E0
#define REG_LLT_INIT_ADDR_8822B 0x01E4
#define REG_BB_ACCESS_CTRL_8822B 0x01E8
#define REG_BB_ACCESS_DATA_8822B 0x01EC
#define REG_HMEBOX_E0_8822B 0x01F0
#define REG_HMEBOX_E1_8822B 0x01F4
#define REG_HMEBOX_E2_8822B 0x01F8
#define REG_HMEBOX_E3_8822B 0x01FC
#define REG_CR_EXT_8822B 0x1100
#define REG_FWFF_8822B 0x1114
#define REG_RXFF_PTR_V1_8822B 0x1118
#define REG_RXFF_WTR_V1_8822B 0x111C
#define REG_FE2IMR_8822B 0x1120
#define REG_FE2ISR_8822B 0x1124
#define REG_FE3IMR_8822B 0x1128
#define REG_FE3ISR_8822B 0x112C
#define REG_FE4IMR_8822B 0x1130
#define REG_FE4ISR_8822B 0x1134
#define REG_FT1IMR_8822B 0x1138
#define REG_FT1ISR_8822B 0x113C
#define REG_SPWR0_8822B 0x1140
#define REG_SPWR1_8822B 0x1144
#define REG_SPWR2_8822B 0x1148
#define REG_SPWR3_8822B 0x114C
#define REG_POWSEQ_8822B 0x1150
#define REG_TC7_CTRL_V1_8822B 0x1158
#define REG_TC8_CTRL_V1_8822B 0x115C
#define REG_FT2IMR_8822B 0x11E0
#define REG_FT2ISR_8822B 0x11E4
#define REG_MSG2_8822B 0x11F0
#define REG_MSG3_8822B 0x11F4
#define REG_MSG4_8822B 0x11F8
#define REG_MSG5_8822B 0x11FC
#define REG_FIFOPAGE_CTRL_1_8822B 0x0200
#define REG_FIFOPAGE_CTRL_2_8822B 0x0204
#define REG_AUTO_LLT_V1_8822B 0x0208
#define REG_TXDMA_OFFSET_CHK_8822B 0x020C
#define REG_TXDMA_STATUS_8822B 0x0210
#define REG_TX_DMA_DBG_8822B 0x0214
#define REG_TQPNT1_8822B 0x0218
#define REG_TQPNT2_8822B 0x021C
#define REG_TQPNT3_8822B 0x0220
#define REG_TQPNT4_8822B 0x0224
#define REG_RQPN_CTRL_1_8822B 0x0228
#define REG_RQPN_CTRL_2_8822B 0x022C
#define REG_FIFOPAGE_INFO_1_8822B 0x0230
#define REG_FIFOPAGE_INFO_2_8822B 0x0234
#define REG_FIFOPAGE_INFO_3_8822B 0x0238
#define REG_FIFOPAGE_INFO_4_8822B 0x023C
#define REG_FIFOPAGE_INFO_5_8822B 0x0240
#define REG_H2C_HEAD_8822B 0x0244
#define REG_H2C_TAIL_8822B 0x0248
#define REG_H2C_READ_ADDR_8822B 0x024C
#define REG_H2C_WR_ADDR_8822B 0x0250
#define REG_H2C_INFO_8822B 0x0254
#define REG_RXDMA_AGG_PG_TH_8822B 0x0280
#define REG_RXPKT_NUM_8822B 0x0284
#define REG_RXDMA_STATUS_8822B 0x0288
#define REG_RXDMA_DPR_8822B 0x028C
#define REG_RXDMA_MODE_8822B 0x0290
#define REG_C2H_PKT_8822B 0x0294
#define REG_FWFF_C2H_8822B 0x0298
#define REG_FWFF_CTRL_8822B 0x029C
#define REG_FWFF_PKT_INFO_8822B 0x02A0
#define REG_DDMA_CH0SA_8822B 0x1200
#define REG_DDMA_CH0DA_8822B 0x1204
#define REG_DDMA_CH0CTRL_8822B 0x1208
#define REG_DDMA_CH1SA_8822B 0x1210
#define REG_DDMA_CH1DA_8822B 0x1214
#define REG_DDMA_CH1CTRL_8822B 0x1218
#define REG_DDMA_CH2SA_8822B 0x1220
#define REG_DDMA_CH2DA_8822B 0x1224
#define REG_DDMA_CH2CTRL_8822B 0x1228
#define REG_DDMA_CH3SA_8822B 0x1230
#define REG_DDMA_CH3DA_8822B 0x1234
#define REG_DDMA_CH3CTRL_8822B 0x1238
#define REG_DDMA_CH4SA_8822B 0x1240
#define REG_DDMA_CH4DA_8822B 0x1244
#define REG_DDMA_CH4CTRL_8822B 0x1248
#define REG_DDMA_CH5SA_8822B 0x1250
#define REG_DDMA_CH5DA_8822B 0x1254
#define REG_REG_DDMA_CH5CTRL_8822B 0x1258
#define REG_DDMA_INT_MSK_8822B 0x12E0
#define REG_DDMA_CHSTATUS_8822B 0x12E8
#define REG_DDMA_CHKSUM_8822B 0x12F0
#define REG_DDMA_MONITOR_8822B 0x12FC
#define REG_PCIE_CTRL_8822B 0x0300
#define REG_INT_MIG_8822B 0x0304
#define REG_BCNQ_TXBD_DESA_8822B 0x0308
#define REG_MGQ_TXBD_DESA_8822B 0x0310
#define REG_VOQ_TXBD_DESA_8822B 0x0318
#define REG_VIQ_TXBD_DESA_8822B 0x0320
#define REG_BEQ_TXBD_DESA_8822B 0x0328
#define REG_BKQ_TXBD_DESA_8822B 0x0330
#define REG_RXQ_RXBD_DESA_8822B 0x0338
#define REG_HI0Q_TXBD_DESA_8822B 0x0340
#define REG_HI1Q_TXBD_DESA_8822B 0x0348
#define REG_HI2Q_TXBD_DESA_8822B 0x0350
#define REG_HI3Q_TXBD_DESA_8822B 0x0358
#define REG_HI4Q_TXBD_DESA_8822B 0x0360
#define REG_HI5Q_TXBD_DESA_8822B 0x0368
#define REG_HI6Q_TXBD_DESA_8822B 0x0370
#define REG_HI7Q_TXBD_DESA_8822B 0x0378
#define REG_MGQ_TXBD_NUM_8822B 0x0380
#define REG_RX_RXBD_NUM_8822B 0x0382
#define REG_VOQ_TXBD_NUM_8822B 0x0384
#define REG_VIQ_TXBD_NUM_8822B 0x0386
#define REG_BEQ_TXBD_NUM_8822B 0x0388
#define REG_BKQ_TXBD_NUM_8822B 0x038A
#define REG_HI0Q_TXBD_NUM_8822B 0x038C
#define REG_HI1Q_TXBD_NUM_8822B 0x038E
#define REG_HI2Q_TXBD_NUM_8822B 0x0390
#define REG_HI3Q_TXBD_NUM_8822B 0x0392
#define REG_HI4Q_TXBD_NUM_8822B 0x0394
#define REG_HI5Q_TXBD_NUM_8822B 0x0396
#define REG_HI6Q_TXBD_NUM_8822B 0x0398
#define REG_HI7Q_TXBD_NUM_8822B 0x039A
#define REG_TSFTIMER_HCI_8822B 0x039C
#define REG_BD_RWPTR_CLR_8822B 0x039C
#define REG_VOQ_TXBD_IDX_8822B 0x03A0
#define REG_VIQ_TXBD_IDX_8822B 0x03A4
#define REG_BEQ_TXBD_IDX_8822B 0x03A8
#define REG_BKQ_TXBD_IDX_8822B 0x03AC
#define REG_MGQ_TXBD_IDX_8822B 0x03B0
#define REG_RXQ_RXBD_IDX_8822B 0x03B4
#define REG_HI0Q_TXBD_IDX_8822B 0x03B8
#define REG_HI1Q_TXBD_IDX_8822B 0x03BC
#define REG_HI2Q_TXBD_IDX_8822B 0x03C0
#define REG_HI3Q_TXBD_IDX_8822B 0x03C4
#define REG_HI4Q_TXBD_IDX_8822B 0x03C8
#define REG_HI5Q_TXBD_IDX_8822B 0x03CC
#define REG_HI6Q_TXBD_IDX_8822B 0x03D0
#define REG_HI7Q_TXBD_IDX_8822B 0x03D4
#define REG_DBG_SEL_V1_8822B 0x03D8
#define REG_PCIE_HRPWM1_V1_8822B 0x03D9
#define REG_PCIE_HCPWM1_V1_8822B 0x03DA
#define REG_PCIE_CTRL2_8822B 0x03DB
#define REG_PCIE_HRPWM2_V1_8822B 0x03DC
#define REG_PCIE_HCPWM2_V1_8822B 0x03DE
#define REG_PCIE_H2C_MSG_V1_8822B 0x03E0
#define REG_PCIE_C2H_MSG_V1_8822B 0x03E4
#define REG_DBI_WDATA_V1_8822B 0x03E8
#define REG_DBI_RDATA_V1_8822B 0x03EC
#define REG_DBI_FLAG_V1_8822B 0x03F0
#define REG_MDIO_V1_8822B 0x03F4
#define REG_PCIE_MIX_CFG_8822B 0x03F8
#define REG_HCI_MIX_CFG_8822B 0x03FC
#define REG_STC_INT_CS_8822B 0x1300
#define REG_ST_INT_CFG_8822B 0x1304
#define REG_CMU_DLY_CTRL_8822B 0x1310
#define REG_CMU_DLY_CFG_8822B 0x1314
#define REG_H2CQ_TXBD_DESA_8822B 0x1320
#define REG_H2CQ_TXBD_NUM_8822B 0x1328
#define REG_H2CQ_TXBD_IDX_8822B 0x132C
#define REG_H2CQ_CSR_8822B 0x1330
#define REG_CHANGE_PCIE_SPEED_8822B 0x1350
#define REG_OLD_DEHANG_8822B 0x13F4
#define REG_Q0_INFO_8822B 0x0400
#define REG_Q1_INFO_8822B 0x0404
#define REG_Q2_INFO_8822B 0x0408
#define REG_Q3_INFO_8822B 0x040C
#define REG_MGQ_INFO_8822B 0x0410
#define REG_HIQ_INFO_8822B 0x0414
#define REG_BCNQ_INFO_8822B 0x0418
#define REG_TXPKT_EMPTY_8822B 0x041A
#define REG_CPU_MGQ_INFO_8822B 0x041C
#define REG_FWHW_TXQ_CTRL_8822B 0x0420
#define REG_DATAFB_SEL_8822B 0x0423
#define REG_BCNQ_BDNY_V1_8822B 0x0424
#define REG_LIFETIME_EN_8822B 0x0426
#define REG_SPEC_SIFS_8822B 0x0428
#define REG_RETRY_LIMIT_8822B 0x042A
#define REG_TXBF_CTRL_8822B 0x042C
#define REG_DARFRC_8822B 0x0430
#define REG_RARFRC_8822B 0x0438
#define REG_RRSR_8822B 0x0440
#define REG_ARFR0_8822B 0x0444
#define REG_ARFR1_V1_8822B 0x044C
#define REG_CCK_CHECK_8822B 0x0454
#define REG_AMPDU_MAX_TIME_V1_8822B 0x0455
#define REG_BCNQ1_BDNY_V1_8822B 0x0456
#define REG_AMPDU_MAX_LENGTH_8822B 0x0458
#define REG_ACQ_STOP_8822B 0x045C
#define REG_NDPA_RATE_8822B 0x045D
#define REG_TX_HANG_CTRL_8822B 0x045E
#define REG_NDPA_OPT_CTRL_8822B 0x045F
#define REG_RD_RESP_PKT_TH_8822B 0x0463
#define REG_CMDQ_INFO_8822B 0x0464
#define REG_Q4_INFO_8822B 0x0468
#define REG_Q5_INFO_8822B 0x046C
#define REG_Q6_INFO_8822B 0x0470
#define REG_Q7_INFO_8822B 0x0474
#define REG_WMAC_LBK_BUF_HD_V1_8822B 0x0478
#define REG_MGQ_BDNY_V1_8822B 0x047A
#define REG_TXRPT_CTRL_8822B 0x047C
#define REG_INIRTS_RATE_SEL_8822B 0x0480
#define REG_BASIC_CFEND_RATE_8822B 0x0481
#define REG_STBC_CFEND_RATE_8822B 0x0482
#define REG_DATA_SC_8822B 0x0483
#define REG_MACID_SLEEP3_8822B 0x0484
#define REG_MACID_SLEEP1_8822B 0x0488
#define REG_ARFR2_V1_8822B 0x048C
#define REG_ARFR3_V1_8822B 0x0494
#define REG_ARFR4_8822B 0x049C
#define REG_ARFR5_8822B 0x04A4
#define REG_TXRPT_START_OFFSET_8822B 0x04AC
#define REG_POWER_STAGE1_8822B 0x04B4
#define REG_POWER_STAGE2_8822B 0x04B8
#define REG_SW_AMPDU_BURST_MODE_CTRL_8822B 0x04BC
#define REG_PKT_LIFE_TIME_8822B 0x04C0
#define REG_STBC_SETTING_8822B 0x04C4
#define REG_STBC_SETTING2_8822B 0x04C5
#define REG_QUEUE_CTRL_8822B 0x04C6
#define REG_SINGLE_AMPDU_CTRL_8822B 0x04C7
#define REG_PROT_MODE_CTRL_8822B 0x04C8
#define REG_BAR_MODE_CTRL_8822B 0x04CC
#define REG_RA_TRY_RATE_AGG_LMT_8822B 0x04CF
#define REG_MACID_SLEEP2_8822B 0x04D0
#define REG_MACID_SLEEP_8822B 0x04D4
#define REG_HW_SEQ0_8822B 0x04D8
#define REG_HW_SEQ1_8822B 0x04DA
#define REG_HW_SEQ2_8822B 0x04DC
#define REG_HW_SEQ3_8822B 0x04DE
#define REG_NULL_PKT_STATUS_V1_8822B 0x04E0
#define REG_PTCL_ERR_STATUS_8822B 0x04E2
#define REG_NULL_PKT_STATUS_EXTEND_8822B 0x04E3
#define REG_VIDEO_ENHANCEMENT_FUN_8822B 0x04E4
#define REG_BT_POLLUTE_PKT_CNT_8822B 0x04E8
#define REG_PTCL_DBG_8822B 0x04EC
#define REG_CPUMGQ_TIMER_CTRL2_8822B 0x04F4
#define REG_DUMMY_PAGE4_V1_8822B 0x04FC
#define REG_MOREDATA_8822B 0x04FE
#define REG_Q0_Q1_INFO_8822B 0x1400
#define REG_Q2_Q3_INFO_8822B 0x1404
#define REG_Q4_Q5_INFO_8822B 0x1408
#define REG_Q6_Q7_INFO_8822B 0x140C
#define REG_MGQ_HIQ_INFO_8822B 0x1410
#define REG_CMDQ_BCNQ_INFO_8822B 0x1414
#define REG_USEREG_SETTING_8822B 0x1420
#define REG_AESIV_SETTING_8822B 0x1424
#define REG_BF0_TIME_SETTING_8822B 0x1428
#define REG_BF1_TIME_SETTING_8822B 0x142C
#define REG_BF_TIMEOUT_EN_8822B 0x1430
#define REG_MACID_RELEASE0_8822B 0x1434
#define REG_MACID_RELEASE1_8822B 0x1438
#define REG_MACID_RELEASE2_8822B 0x143C
#define REG_MACID_RELEASE3_8822B 0x1440
#define REG_MACID_RELEASE_SETTING_8822B 0x1444
#define REG_FAST_EDCA_VOVI_SETTING_8822B 0x1448
#define REG_FAST_EDCA_BEBK_SETTING_8822B 0x144C
#define REG_MACID_DROP0_8822B 0x1450
#define REG_MACID_DROP1_8822B 0x1454
#define REG_MACID_DROP2_8822B 0x1458
#define REG_MACID_DROP3_8822B 0x145C
#define REG_R_MACID_RELEASE_SUCCESS_0_8822B 0x1460
#define REG_R_MACID_RELEASE_SUCCESS_1_8822B 0x1464
#define REG_R_MACID_RELEASE_SUCCESS_2_8822B 0x1468
#define REG_R_MACID_RELEASE_SUCCESS_3_8822B 0x146C
#define REG_MGG_FIFO_CRTL_8822B 0x1470
#define REG_MGG_FIFO_INT_8822B 0x1474
#define REG_MGG_FIFO_LIFETIME_8822B 0x1478
#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x147C
#define REG_MACID_SHCUT_OFFSET_8822B 0x1480
#define REG_MU_TX_CTL_8822B 0x14C0
#define REG_MU_STA_GID_VLD_8822B 0x14C4
#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8
#define REG_MU_TRX_DBG_CNT_8822B 0x14D0
#define REG_EDCA_VO_PARAM_8822B 0x0500
#define REG_EDCA_VI_PARAM_8822B 0x0504
#define REG_EDCA_BE_PARAM_8822B 0x0508
#define REG_EDCA_BK_PARAM_8822B 0x050C
#define REG_BCNTCFG_8822B 0x0510
#define REG_PIFS_8822B 0x0512
#define REG_RDG_PIFS_8822B 0x0513
#define REG_SIFS_8822B 0x0514
#define REG_TSFTR_SYN_OFFSET_8822B 0x0518
#define REG_AGGR_BREAK_TIME_8822B 0x051A
#define REG_SLOT_8822B 0x051B
#define REG_TX_PTCL_CTRL_8822B 0x0520
#define REG_TXPAUSE_8822B 0x0522
#define REG_DIS_TXREQ_CLR_8822B 0x0523
#define REG_RD_CTRL_8822B 0x0524
#define REG_MBSSID_CTRL_8822B 0x0526
#define REG_P2PPS_CTRL_8822B 0x0527
#define REG_PKT_LIFETIME_CTRL_8822B 0x0528
#define REG_P2PPS_SPEC_STATE_8822B 0x052B
#define REG_BAR_TX_CTRL_8822B 0x0530
#define REG_QUEUE_INCOL_THR_8822B 0x0538
#define REG_QUEUE_INCOL_EN_8822B 0x053C
#define REG_TBTT_PROHIBIT_8822B 0x0540
#define REG_P2PPS_STATE_8822B 0x0543
#define REG_RD_NAV_NXT_8822B 0x0544
#define REG_NAV_PROT_LEN_8822B 0x0546
#define REG_BCN_CTRL_8822B 0x0550
#define REG_BCN_CTRL_CLINT0_8822B 0x0551
#define REG_MBID_NUM_8822B 0x0552
#define REG_DUAL_TSF_RST_8822B 0x0553
#define REG_MBSSID_BCN_SPACE_8822B 0x0554
#define REG_DRVERLYINT_8822B 0x0558
#define REG_BCNDMATIM_8822B 0x0559
#define REG_ATIMWND_8822B 0x055A
#define REG_USTIME_TSF_8822B 0x055C
#define REG_BCN_MAX_ERR_8822B 0x055D
#define REG_RXTSF_OFFSET_CCK_8822B 0x055E
#define REG_RXTSF_OFFSET_OFDM_8822B 0x055F
#define REG_TSFTR_8822B 0x0560
#define REG_FREERUN_CNT_8822B 0x0568
#define REG_ATIMWND1_V1_8822B 0x0570
#define REG_TBTT_PROHIBIT_INFRA_8822B 0x0571
#define REG_CTWND_8822B 0x0572
#define REG_BCNIVLCUNT_8822B 0x0573
#define REG_BCNDROPCTRL_8822B 0x0574
#define REG_HGQ_TIMEOUT_PERIOD_8822B 0x0575
#define REG_TXCMD_TIMEOUT_PERIOD_8822B 0x0576
#define REG_MISC_CTRL_8822B 0x0577
#define REG_BCN_CTRL_CLINT1_8822B 0x0578
#define REG_BCN_CTRL_CLINT2_8822B 0x0579
#define REG_BCN_CTRL_CLINT3_8822B 0x057A
#define REG_EXTEND_CTRL_8822B 0x057B
#define REG_P2PPS1_SPEC_STATE_8822B 0x057C
#define REG_P2PPS1_STATE_8822B 0x057D
#define REG_P2PPS2_SPEC_STATE_8822B 0x057E
#define REG_P2PPS2_STATE_8822B 0x057F
#define REG_PS_TIMER0_8822B 0x0580
#define REG_PS_TIMER1_8822B 0x0584
#define REG_PS_TIMER2_8822B 0x0588
#define REG_TBTT_CTN_AREA_8822B 0x058C
#define REG_FORCE_BCN_IFS_8822B 0x058E
#define REG_TXOP_MIN_8822B 0x0590
#define REG_PRE_BKF_TIME_8822B 0x0592
#define REG_CROSS_TXOP_CTRL_8822B 0x0593
#define REG_ATIMWND2_8822B 0x05A0
#define REG_ATIMWND3_8822B 0x05A1
#define REG_ATIMWND4_8822B 0x05A2
#define REG_ATIMWND5_8822B 0x05A3
#define REG_ATIMWND6_8822B 0x05A4
#define REG_ATIMWND7_8822B 0x05A5
#define REG_ATIMUGT_8822B 0x05A6
#define REG_HIQ_NO_LMT_EN_8822B 0x05A7
#define REG_DTIM_COUNTER_ROOT_8822B 0x05A8
#define REG_DTIM_COUNTER_VAP1_8822B 0x05A9
#define REG_DTIM_COUNTER_VAP2_8822B 0x05AA
#define REG_DTIM_COUNTER_VAP3_8822B 0x05AB
#define REG_DTIM_COUNTER_VAP4_8822B 0x05AC
#define REG_DTIM_COUNTER_VAP5_8822B 0x05AD
#define REG_DTIM_COUNTER_VAP6_8822B 0x05AE
#define REG_DTIM_COUNTER_VAP7_8822B 0x05AF
#define REG_DIS_ATIM_8822B 0x05B0
#define REG_EARLY_128US_8822B 0x05B1
#define REG_P2PPS1_CTRL_8822B 0x05B2
#define REG_P2PPS2_CTRL_8822B 0x05B3
#define REG_TIMER0_SRC_SEL_8822B 0x05B4
#define REG_NOA_UNIT_SEL_8822B 0x05B5
#define REG_P2POFF_DIS_TXTIME_8822B 0x05B7
#define REG_MBSSID_BCN_SPACE2_8822B 0x05B8
#define REG_MBSSID_BCN_SPACE3_8822B 0x05BC
#define REG_ACMHWCTRL_8822B 0x05C0
#define REG_ACMRSTCTRL_8822B 0x05C1
#define REG_ACMAVG_8822B 0x05C2
#define REG_VO_ADMTIME_8822B 0x05C4
#define REG_VI_ADMTIME_8822B 0x05C6
#define REG_BE_ADMTIME_8822B 0x05C8
#define REG_EDCA_RANDOM_GEN_8822B 0x05CC
#define REG_TXCMD_NOA_SEL_8822B 0x05CF
#define REG_NOA_PARAM_8822B 0x05E0
#define REG_P2P_RST_8822B 0x05F0
#define REG_SCHEDULER_RST_8822B 0x05F1
#define REG_SCH_TXCMD_8822B 0x05F8
#define REG_PAGE5_DUMMY_8822B 0x05FC
#define REG_CPUMGQ_TX_TIMER_8822B 0x1500
#define REG_PS_TIMER_A_8822B 0x1504
#define REG_PS_TIMER_B_8822B 0x1508
#define REG_PS_TIMER_C_8822B 0x150C
#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B 0x1510
#define REG_CPUMGQ_TX_TIMER_EARLY_8822B 0x1514
#define REG_PS_TIMER_A_EARLY_8822B 0x1515
#define REG_PS_TIMER_B_EARLY_8822B 0x1516
#define REG_PS_TIMER_C_EARLY_8822B 0x1517
#define REG_WMAC_CR_8822B 0x0600
#define REG_WMAC_FWPKT_CR_8822B 0x0601
#define REG_BWOPMODE_8822B 0x0603
#define REG_TCR_8822B 0x0604
#define REG_RCR_8822B 0x0608
#define REG_RX_PKT_LIMIT_8822B 0x060C
#define REG_RX_DLK_TIME_8822B 0x060D
#define REG_RX_DRVINFO_SZ_8822B 0x060F
#define REG_MACID_8822B 0x0610
#define REG_BSSID_8822B 0x0618
#define REG_MAR_8822B 0x0620
#define REG_MBIDCAMCFG_1_8822B 0x0628
#define REG_MBIDCAMCFG_2_8822B 0x062C
#define REG_WMAC_TCR_TSFT_OFS_8822B 0x0630
#define REG_UDF_THSD_8822B 0x0632
#define REG_ZLD_NUM_8822B 0x0633
#define REG_STMP_THSD_8822B 0x0634
#define REG_WMAC_TXTIMEOUT_8822B 0x0635
#define REG_MCU_TEST_2_V1_8822B 0x0636
#define REG_USTIME_EDCA_8822B 0x0638
#define REG_MAC_SPEC_SIFS_8822B 0x063A
#define REG_RESP_SIFS_CCK_8822B 0x063C
#define REG_RESP_SIFS_OFDM_8822B 0x063E
#define REG_ACKTO_8822B 0x0640
#define REG_CTS2TO_8822B 0x0641
#define REG_EIFS_8822B 0x0642
#define REG_NAV_CTRL_8822B 0x0650
#define REG_BACAMCMD_8822B 0x0654
#define REG_BACAMCONTENT_8822B 0x0658
#define REG_LBDLY_8822B 0x0660
#define REG_WMAC_BACAM_RPMEN_8822B 0x0661
#define REG_TX_RX_8822B 0x0662
#define REG_WMAC_BITMAP_CTL_8822B 0x0663
#define REG_RXERR_RPT_8822B 0x0664
#define REG_WMAC_TRXPTCL_CTL_8822B 0x0668
#define REG_CAMCMD_8822B 0x0670
#define REG_CAMWRITE_8822B 0x0674
#define REG_CAMREAD_8822B 0x0678
#define REG_CAMDBG_8822B 0x067C
#define REG_SECCFG_8822B 0x0680
#define REG_RXFILTER_CATEGORY_1_8822B 0x0682
#define REG_RXFILTER_ACTION_1_8822B 0x0683
#define REG_RXFILTER_CATEGORY_2_8822B 0x0684
#define REG_RXFILTER_ACTION_2_8822B 0x0685
#define REG_RXFILTER_CATEGORY_3_8822B 0x0686
#define REG_RXFILTER_ACTION_3_8822B 0x0687
#define REG_RXFLTMAP3_8822B 0x0688
#define REG_RXFLTMAP4_8822B 0x068A
#define REG_RXFLTMAP5_8822B 0x068C
#define REG_RXFLTMAP6_8822B 0x068E
#define REG_WOW_CTRL_8822B 0x0690
#define REG_NAN_RX_TSF_FILTER_8822B 0x0691
#define REG_PS_RX_INFO_8822B 0x0692
#define REG_WMMPS_UAPSD_TID_8822B 0x0693
#define REG_LPNAV_CTRL_8822B 0x0694
#define REG_WKFMCAM_CMD_8822B 0x0698
#define REG_WKFMCAM_RWD_8822B 0x069C
#define REG_RXFLTMAP0_8822B 0x06A0
#define REG_RXFLTMAP1_8822B 0x06A2
#define REG_RXFLTMAP_8822B 0x06A4
#define REG_BCN_PSR_RPT_8822B 0x06A8
#define REG_FLC_RPC_8822B 0x06AC
#define REG_FLC_RPCT_8822B 0x06AD
#define REG_FLC_PTS_8822B 0x06AE
#define REG_FLC_TRPC_8822B 0x06AF
#define REG_RXPKTMON_CTRL_8822B 0x06B0
#define REG_STATE_MON_8822B 0x06B4
#define REG_ERROR_MON_8822B 0x06B8
#define REG_SEARCH_MACID_8822B 0x06BC
#define REG_BT_COEX_TABLE_8822B 0x06C0
#define REG_RXCMD_0_8822B 0x06D0
#define REG_RXCMD_1_8822B 0x06D4
#define REG_WMAC_RESP_TXINFO_8822B 0x06D8
#define REG_BBPSF_CTRL_8822B 0x06DC
#define REG_P2P_RX_BCN_NOA_8822B 0x06E0
#define REG_ASSOCIATED_BFMER0_INFO_8822B 0x06E4
#define REG_ASSOCIATED_BFMER1_INFO_8822B 0x06EC
#define REG_TX_CSI_RPT_PARAM_BW20_8822B 0x06F4
#define REG_TX_CSI_RPT_PARAM_BW40_8822B 0x06F8
#define REG_TX_CSI_RPT_PARAM_BW80_8822B 0x06FC
#define REG_BCN_PSR_RPT2_8822B 0x1600
#define REG_BCN_PSR_RPT3_8822B 0x1604
#define REG_BCN_PSR_RPT4_8822B 0x1608
#define REG_A1_ADDR_MASK_8822B 0x160C
#define REG_MACID2_8822B 0x1620
#define REG_BSSID2_8822B 0x1628
#define REG_MACID3_8822B 0x1630
#define REG_BSSID3_8822B 0x1638
#define REG_MACID4_8822B 0x1640
#define REG_BSSID4_8822B 0x1648
#define REG_NOA_REPORT_8822B 0x1650
#define REG_PWRBIT_SETTING_8822B 0x1660
#define REG_WMAC_MU_BF_OPTION_8822B 0x167C
#define REG_WMAC_MU_ARB_8822B 0x167E
#define REG_WMAC_MU_OPTION_8822B 0x167F
#define REG_WMAC_MU_BF_CTL_8822B 0x1680
#define REG_WMAC_MU_BFRPT_PARA_8822B 0x1682
#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B 0x1684
#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B 0x1686
#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B 0x1688
#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B 0x168A
#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B 0x168C
#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B 0x168E
#define REG_TRANSMIT_ADDRSS_0_8822B 0x16A0
#define REG_TRANSMIT_ADDRSS_1_8822B 0x16A8
#define REG_TRANSMIT_ADDRSS_2_8822B 0x16B0
#define REG_TRANSMIT_ADDRSS_3_8822B 0x16B8
#define REG_TRANSMIT_ADDRSS_4_8822B 0x16C0
#define REG_MACID1_8822B 0x0700
#define REG_BSSID1_8822B 0x0708
#define REG_BCN_PSR_RPT1_8822B 0x0710
#define REG_ASSOCIATED_BFMEE_SEL_8822B 0x0714
#define REG_SND_PTCL_CTRL_8822B 0x0718
#define REG_RX_CSI_RPT_INFO_8822B 0x071C
#define REG_NS_ARP_CTRL_8822B 0x0720
#define REG_NS_ARP_INFO_8822B 0x0724
#define REG_BEAMFORMING_INFO_NSARP_V1_8822B 0x0728
#define REG_BEAMFORMING_INFO_NSARP_8822B 0x072C
#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822B 0x0750
#define REG_WMAC_SWAES_CFG_8822B 0x0760
#define REG_BT_COEX_V2_8822B 0x0762
#define REG_BT_COEX_8822B 0x0764
#define REG_WLAN_ACT_MASK_CTRL_8822B 0x0768
#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822B 0x076E
#define REG_BT_ACT_STATISTICS_8822B 0x0770
#define REG_BT_STATISTICS_CONTROL_REGISTER_8822B 0x0778
#define REG_BT_STATUS_REPORT_REGISTER_8822B 0x077C
#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822B 0x0780
#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B 0x0784
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B 0x0785
#define REG_BT_INTERRUPT_STATUS_REGISTER_8822B 0x078F
#define REG_BT_TDMA_TIME_REGISTER_8822B 0x0790
#define REG_BT_ACT_REGISTER_8822B 0x0794
#define REG_OBFF_CTRL_BASIC_8822B 0x0798
#define REG_OBFF_CTRL2_TIMER_8822B 0x079C
#define REG_LTR_CTRL_BASIC_8822B 0x07A0
#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822B 0x07A4
#define REG_LTR_IDLE_LATENCY_V1_8822B 0x07A8
#define REG_LTR_ACTIVE_LATENCY_V1_8822B 0x07AC
#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B 0x07B0
#define REG_WMAC_PKTCNT_RWD_8822B 0x07B8
#define REG_WMAC_PKTCNT_CTRL_8822B 0x07BC
#define REG_IQ_DUMP_8822B 0x07C0
#define REG_WMAC_FTM_CTL_8822B 0x07CC
#define REG_WMAC_IQ_MDPK_FUNC_8822B 0x07CE
#define REG_WMAC_OPTION_FUNCTION_8822B 0x07D0
#define REG_RX_FILTER_FUNCTION_8822B 0x07DA
#define REG_NDP_SIG_8822B 0x07E0
#define REG_TXCMD_INFO_FOR_RSP_PKT_8822B 0x07E4
#define REG_RTS_ADDRESS_0_8822B 0x07F0
#define REG_RTS_ADDRESS_1_8822B 0x07F8
#define REG__RPFM_MAP1_8822B 0x07FE
#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822B 0x1700
#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B 0x1704
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B 0x1708
#define REG_SDIO_TX_CTRL_8822B 0x10250000
#define REG_SDIO_HIMR_8822B 0x10250014
#define REG_SDIO_HISR_8822B 0x10250018
#define REG_SDIO_RX_REQ_LEN_8822B 0x1025001C
#define REG_SDIO_FREE_TXPG_SEQ_V1_8822B 0x1025001F
#define REG_SDIO_FREE_TXPG_8822B 0x10250020
#define REG_SDIO_FREE_TXPG2_8822B 0x10250024
#define REG_SDIO_OQT_FREE_TXPG_V1_8822B 0x10250028
#define REG_SDIO_HTSFR_INFO_8822B 0x10250030
#define REG_SDIO_HCPWM1_V2_8822B 0x10250038
#define REG_SDIO_HCPWM2_V2_8822B 0x1025003A
#define REG_SDIO_INDIRECT_REG_CFG_8822B 0x10250040
#define REG_SDIO_INDIRECT_REG_DATA_8822B 0x10250044
#define REG_SDIO_H2C_8822B 0x10250060
#define REG_SDIO_C2H_8822B 0x10250064
#define REG_SDIO_HRPWM1_8822B 0x10250080
#define REG_SDIO_HRPWM2_8822B 0x10250082
#define REG_SDIO_HPS_CLKR_8822B 0x10250084
#define REG_SDIO_BUS_CTRL_8822B 0x10250085
#define REG_SDIO_HSUS_CTRL_8822B 0x10250086
#define REG_SDIO_RESPONSE_TIMER_8822B 0x10250088
#define REG_SDIO_CMD_CRC_8822B 0x1025008A
#define REG_SDIO_HSISR_8822B 0x10250090
#define REG_SDIO_HSIMR_8822B 0x10250091
#define REG_SDIO_ERR_RPT_8822B 0x102500C0
#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C1
#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C2
#define REG_SDIO_CMD_ERR_CONTENT_8822B 0x102500C4
#define REG_SDIO_CRC_ERR_IDX_8822B 0x102500C9
#define REG_SDIO_DATA_CRC_8822B 0x102500CA
#define REG_SDIO_DATA_REPLY_TIME_8822B 0x102500CB
#endif
drivers/staging/rtlwifi/halmac/halmac_rx_bd_chip.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_RX_BD_CHIP_H_
#define _HALMAC_RX_BD_CHIP_H_
/*TXBD_DW0*/
#define GET_RX_BD_RXFAIL_8822B(__rx_bd) GET_RX_BD_RXFAIL(__rx_bd)
#define GET_RX_BD_TOTALRXPKTSIZE_8822B(__rx_bd) \
GET_RX_BD_TOTALRXPKTSIZE(__rx_bd)
#define GET_RX_BD_RXTAG_8822B(__rx_bd) GET_RX_BD_RXTAG(__rx_bd)
#define GET_RX_BD_FS_8822B(__rx_bd) GET_RX_BD_FS(__rx_bd)
#define GET_RX_BD_LS_8822B(__rx_bd) GET_RX_BD_LS(__rx_bd)
#define GET_RX_BD_RXBUFFSIZE_8822B(__rx_bd) GET_RX_BD_RXBUFFSIZE(__rx_bd)
/*TXBD_DW1*/
#define GET_RX_BD_PHYSICAL_ADDR_LOW_8822B(__rx_bd) \
GET_RX_BD_PHYSICAL_ADDR_LOW(__rx_bd)
/*TXBD_DW2*/
#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8822B(__rx_bd) \
GET_RX_BD_PHYSICAL_ADDR_HIGH(__rx_bd)
#endif
drivers/staging/rtlwifi/halmac/halmac_rx_bd_nic.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_RX_BD_NIC_H_
#define _HALMAC_RX_BD_NIC_H_
/*TXBD_DW0*/
#define GET_RX_BD_RXFAIL(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 31, 1)
#define GET_RX_BD_TOTALRXPKTSIZE(__rx_bd) \
LE_BITS_TO_4BYTE(__rx_bd + 0x00, 16, 13)
#define GET_RX_BD_RXTAG(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 16, 13)
#define GET_RX_BD_FS(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 15, 1)
#define GET_RX_BD_LS(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 14, 1)
#define GET_RX_BD_RXBUFFSIZE(__rx_bd) LE_BITS_TO_4BYTE(__rx_bd + 0x00, 0, 14)
/*TXBD_DW1*/
#define GET_RX_BD_PHYSICAL_ADDR_LOW(__rx_bd) \
LE_BITS_TO_4BYTE(__rx_bd + 0x04, 0, 32)
/*TXBD_DW2*/
#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__rx_bd) \
LE_BITS_TO_4BYTE(__rx_bd + 0x08, 0, 32)
#endif
drivers/staging/rtlwifi/halmac/halmac_rx_desc_chip.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_RX_DESC_CHIP_H_
#define _HALMAC_RX_DESC_CHIP_H_
/*RXDESC_WORD0*/
#define GET_RX_DESC_EOR_8822B(__rx_desc) GET_RX_DESC_EOR(__rx_desc)
#define GET_RX_DESC_PHYPKTIDC_8822B(__rx_desc) GET_RX_DESC_PHYPKTIDC(__rx_desc)
#define GET_RX_DESC_SWDEC_8822B(__rx_desc) GET_RX_DESC_SWDEC(__rx_desc)
#define GET_RX_DESC_PHYST_8822B(__rx_desc) GET_RX_DESC_PHYST(__rx_desc)
#define GET_RX_DESC_SHIFT_8822B(__rx_desc) GET_RX_DESC_SHIFT(__rx_desc)
#define GET_RX_DESC_QOS_8822B(__rx_desc) GET_RX_DESC_QOS(__rx_desc)
#define GET_RX_DESC_SECURITY_8822B(__rx_desc) GET_RX_DESC_SECURITY(__rx_desc)
#define GET_RX_DESC_DRV_INFO_SIZE_8822B(__rx_desc) \
GET_RX_DESC_DRV_INFO_SIZE(__rx_desc)
#define GET_RX_DESC_ICV_ERR_8822B(__rx_desc) GET_RX_DESC_ICV_ERR(__rx_desc)
#define GET_RX_DESC_CRC32_8822B(__rx_desc) GET_RX_DESC_CRC32(__rx_desc)
#define GET_RX_DESC_PKT_LEN_8822B(__rx_desc) GET_RX_DESC_PKT_LEN(__rx_desc)
/*RXDESC_WORD1*/
#define GET_RX_DESC_BC_8822B(__rx_desc) GET_RX_DESC_BC(__rx_desc)
#define GET_RX_DESC_MC_8822B(__rx_desc) GET_RX_DESC_MC(__rx_desc)
#define GET_RX_DESC_TY_PE_8822B(__rx_desc) GET_RX_DESC_TY_PE(__rx_desc)
#define GET_RX_DESC_MF_8822B(__rx_desc) GET_RX_DESC_MF(__rx_desc)
#define GET_RX_DESC_MD_8822B(__rx_desc) GET_RX_DESC_MD(__rx_desc)
#define GET_RX_DESC_PWR_8822B(__rx_desc) GET_RX_DESC_PWR(__rx_desc)
#define GET_RX_DESC_PAM_8822B(__rx_desc) GET_RX_DESC_PAM(__rx_desc)
#define GET_RX_DESC_CHK_VLD_8822B(__rx_desc) GET_RX_DESC_CHK_VLD(__rx_desc)
#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(__rx_desc) \
GET_RX_DESC_RX_IS_TCP_UDP(__rx_desc)
#define GET_RX_DESC_RX_IPV_8822B(__rx_desc) GET_RX_DESC_RX_IPV(__rx_desc)
#define GET_RX_DESC_CHKERR_8822B(__rx_desc) GET_RX_DESC_CHKERR(__rx_desc)
#define GET_RX_DESC_PAGGR_8822B(__rx_desc) GET_RX_DESC_PAGGR(__rx_desc)
#define GET_RX_DESC_RXID_MATCH_8822B(__rx_desc) \
GET_RX_DESC_RXID_MATCH(__rx_desc)
#define GET_RX_DESC_AMSDU_8822B(__rx_desc) GET_RX_DESC_AMSDU(__rx_desc)
#define GET_RX_DESC_MACID_VLD_8822B(__rx_desc) GET_RX_DESC_MACID_VLD(__rx_desc)
#define GET_RX_DESC_TID_8822B(__rx_desc) GET_RX_DESC_TID(__rx_desc)
#define GET_RX_DESC_EXT_SECTYPE_8822B(__rx_desc) \
GET_RX_DESC_EXT_SECTYPE(__rx_desc)
#define GET_RX_DESC_MACID_8822B(__rx_desc) GET_RX_DESC_MACID(__rx_desc)
/*RXDESC_WORD2*/
#define GET_RX_DESC_FCS_OK_8822B(__rx_desc) GET_RX_DESC_FCS_OK(__rx_desc)
#define GET_RX_DESC_PPDU_CNT_8822B(__rx_desc) GET_RX_DESC_PPDU_CNT(__rx_desc)
#define GET_RX_DESC_C2H_8822B(__rx_desc) GET_RX_DESC_C2H(__rx_desc)
#define GET_RX_DESC_HWRSVD_8822B(__rx_desc) GET_RX_DESC_HWRSVD(__rx_desc)
#define GET_RX_DESC_WLANHD_IV_LEN_8822B(__rx_desc) \
GET_RX_DESC_WLANHD_IV_LEN(__rx_desc)
#define GET_RX_DESC_RX_IS_QOS_8822B(__rx_desc) GET_RX_DESC_RX_IS_QOS(__rx_desc)
#define GET_RX_DESC_FRAG_8822B(__rx_desc) GET_RX_DESC_FRAG(__rx_desc)
#define GET_RX_DESC_SEQ_8822B(__rx_desc) GET_RX_DESC_SEQ(__rx_desc)
/*RXDESC_WORD3*/
#define GET_RX_DESC_MAGIC_WAKE_8822B(__rx_desc) \
GET_RX_DESC_MAGIC_WAKE(__rx_desc)
#define GET_RX_DESC_UNICAST_WAKE_8822B(__rx_desc) \
GET_RX_DESC_UNICAST_WAKE(__rx_desc)
#define GET_RX_DESC_PATTERN_MATCH_8822B(__rx_desc) \
GET_RX_DESC_PATTERN_MATCH(__rx_desc)
#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(__rx_desc) \
GET_RX_DESC_RXPAYLOAD_MATCH(__rx_desc)
#define GET_RX_DESC_RXPAYLOAD_ID_8822B(__rx_desc) \
GET_RX_DESC_RXPAYLOAD_ID(__rx_desc)
#define GET_RX_DESC_DMA_AGG_NUM_8822B(__rx_desc) \
GET_RX_DESC_DMA_AGG_NUM(__rx_desc)
#define GET_RX_DESC_BSSID_FIT_1_0_8822B(__rx_desc) \
GET_RX_DESC_BSSID_FIT_1_0(__rx_desc)
#define GET_RX_DESC_EOSP_8822B(__rx_desc) GET_RX_DESC_EOSP(__rx_desc)
#define GET_RX_DESC_HTC_8822B(__rx_desc) GET_RX_DESC_HTC(__rx_desc)
#define GET_RX_DESC_BSSID_FIT_4_2_8822B(__rx_desc) \
GET_RX_DESC_BSSID_FIT_4_2(__rx_desc)
#define GET_RX_DESC_RX_RATE_8822B(__rx_desc) GET_RX_DESC_RX_RATE(__rx_desc)
/*RXDESC_WORD4*/
#define GET_RX_DESC_A1_FIT_8822B(__rx_desc) GET_RX_DESC_A1_FIT(__rx_desc)
#define GET_RX_DESC_MACID_RPT_BUFF_8822B(__rx_desc) \
GET_RX_DESC_MACID_RPT_BUFF(__rx_desc)
#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(__rx_desc) \
GET_RX_DESC_RX_PRE_NDP_VLD(__rx_desc)
#define GET_RX_DESC_RX_SCRAMBLER_8822B(__rx_desc) \
GET_RX_DESC_RX_SCRAMBLER(__rx_desc)
#define GET_RX_DESC_RX_EOF_8822B(__rx_desc) GET_RX_DESC_RX_EOF(__rx_desc)
#define GET_RX_DESC_PATTERN_IDX_8822B(__rx_desc) \
GET_RX_DESC_PATTERN_IDX(__rx_desc)
/*RXDESC_WORD5*/
#define GET_RX_DESC_TSFL_8822B(__rx_desc) GET_RX_DESC_TSFL(__rx_desc)
#endif
drivers/staging/rtlwifi/halmac/halmac_rx_desc_nic.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_RX_DESC_NIC_H_
#define _HALMAC_RX_DESC_NIC_H_
/*RXDESC_WORD0*/
#define GET_RX_DESC_EOR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 30, 1)
#define GET_RX_DESC_PHYPKTIDC(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x00, 28, 1)
#define GET_RX_DESC_SWDEC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 27, 1)
#define GET_RX_DESC_PHYST(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 26, 1)
#define GET_RX_DESC_SHIFT(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 24, 2)
#define GET_RX_DESC_QOS(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 23, 1)
#define GET_RX_DESC_SECURITY(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x00, 20, 3)
#define GET_RX_DESC_DRV_INFO_SIZE(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x00, 16, 4)
#define GET_RX_DESC_ICV_ERR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 15, 1)
#define GET_RX_DESC_CRC32(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 14, 1)
#define GET_RX_DESC_PKT_LEN(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x00, 0, 14)
/*RXDESC_WORD1*/
#define GET_RX_DESC_BC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 31, 1)
#define GET_RX_DESC_MC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 30, 1)
#define GET_RX_DESC_TY_PE(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 28, 2)
#define GET_RX_DESC_MF(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 27, 1)
#define GET_RX_DESC_MD(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 26, 1)
#define GET_RX_DESC_PWR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 25, 1)
#define GET_RX_DESC_PAM(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 24, 1)
#define GET_RX_DESC_CHK_VLD(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 23, 1)
#define GET_RX_DESC_RX_IS_TCP_UDP(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x04, 22, 1)
#define GET_RX_DESC_RX_IPV(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 21, 1)
#define GET_RX_DESC_CHKERR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 20, 1)
#define GET_RX_DESC_PAGGR(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 15, 1)
#define GET_RX_DESC_RXID_MATCH(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x04, 14, 1)
#define GET_RX_DESC_AMSDU(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 13, 1)
#define GET_RX_DESC_MACID_VLD(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x04, 12, 1)
#define GET_RX_DESC_TID(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 8, 4)
#define GET_RX_DESC_EXT_SECTYPE(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x04, 7, 1)
#define GET_RX_DESC_MACID(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x04, 0, 7)
/*RXDESC_WORD2*/
#define GET_RX_DESC_FCS_OK(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 31, 1)
#define GET_RX_DESC_PPDU_CNT(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x08, 29, 2)
#define GET_RX_DESC_C2H(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 28, 1)
#define GET_RX_DESC_HWRSVD(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 24, 4)
#define GET_RX_DESC_WLANHD_IV_LEN(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x08, 18, 6)
#define GET_RX_DESC_RX_IS_QOS(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x08, 16, 1)
#define GET_RX_DESC_FRAG(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 12, 4)
#define GET_RX_DESC_SEQ(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x08, 0, 12)
/*RXDESC_WORD3*/
#define GET_RX_DESC_MAGIC_WAKE(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 31, 1)
#define GET_RX_DESC_UNICAST_WAKE(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 30, 1)
#define GET_RX_DESC_PATTERN_MATCH(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 29, 1)
#define GET_RX_DESC_RXPAYLOAD_MATCH(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 28, 1)
#define GET_RX_DESC_RXPAYLOAD_ID(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 24, 4)
#define GET_RX_DESC_DMA_AGG_NUM(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 16, 8)
#define GET_RX_DESC_BSSID_FIT_1_0(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 12, 2)
#define GET_RX_DESC_EOSP(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 11, 1)
#define GET_RX_DESC_HTC(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 10, 1)
#define GET_RX_DESC_BSSID_FIT_4_2(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 7, 3)
#define GET_RX_DESC_RX_RATE(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x0C, 0, 7)
/*RXDESC_WORD4*/
#define GET_RX_DESC_A1_FIT(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x10, 24, 5)
#define GET_RX_DESC_MACID_RPT_BUFF(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x10, 17, 7)
#define GET_RX_DESC_RX_PRE_NDP_VLD(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x10, 16, 1)
#define GET_RX_DESC_RX_SCRAMBLER(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x10, 9, 7)
#define GET_RX_DESC_RX_EOF(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x10, 8, 1)
#define GET_RX_DESC_PATTERN_IDX(__rx_desc) \
LE_BITS_TO_4BYTE(__rx_desc + 0x10, 0, 8)
/*RXDESC_WORD5*/
#define GET_RX_DESC_TSFL(__rx_desc) LE_BITS_TO_4BYTE(__rx_desc + 0x14, 0, 32)
#endif
drivers/staging/rtlwifi/halmac/halmac_sdio_reg.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALMAC_SDIO_REG_H__
#define __HALMAC_SDIO_REG_H__
/* SDIO CMD address mapping */
#define HALMAC_SDIO_4BYTE_LEN_MASK 0x1FFF
#define HALMAC_SDIO_LOCAL_MSK 0x0FFF
#define HALMAC_WLAN_MAC_REG_MSK 0xFFFF
#define HALMAC_WLAN_IOREG_MSK 0xFFFF
/* Sdio address for SDIO Local Reg, TRX FIFO, MAC Reg */
enum halmac_sdio_cmd_addr {
HALMAC_SDIO_CMD_ADDR_SDIO_REG = 0,
HALMAC_SDIO_CMD_ADDR_MAC_REG = 8,
HALMAC_SDIO_CMD_ADDR_TXFF_HIGH = 4,
HALMAC_SDIO_CMD_ADDR_TXFF_LOW = 6,
HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL = 5,
HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA = 7,
HALMAC_SDIO_CMD_ADDR_RXFF = 7,
};
/* IO Bus domain address mapping */
#define SDIO_LOCAL_OFFSET 0x10250000
#define WLAN_IOREG_OFFSET 0x10260000
#define FW_FIFO_OFFSET 0x10270000
#define TX_HIQ_OFFSET 0x10310000
#define TX_MIQ_OFFSET 0x10320000
#define TX_LOQ_OFFSET 0x10330000
#define TX_EXQ_OFFSET 0x10350000
#define RX_RXOFF_OFFSET 0x10340000
/* Get TX WLAN FIFO information in CMD53 addr */
#define GET_WLAN_TXFF_DEVICE_ID(__cmd53_addr) \
LE_BITS_TO_4BYTE((u32 *)__cmd53_addr, 13, 4)
#define GET_WLAN_TXFF_PKT_SIZE(__cmd53_addr) \
(LE_BITS_TO_4BYTE((u32 *)__cmd53_addr, 0, 13) << 2)
#endif /* __HALMAC_SDIO_REG_H__ */
drivers/staging/rtlwifi/halmac/halmac_tx_bd_chip.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_TX_BD_CHIP_H_
#define _HALMAC_TX_BD_CHIP_H_
/*TXBD_DW0*/
#define SET_TX_BD_OWN_8822B(__tx_bd, __value) SET_TX_BD_OWN(__tx_bd, __value)
#define GET_TX_BD_OWN_8822B(__tx_bd) GET_TX_BD_OWN(__tx_bd)
#define SET_TX_BD_PSB_8822B(__tx_bd, __value) SET_TX_BD_PSB(__tx_bd, __value)
#define GET_TX_BD_PSB_8822B(__tx_bd) GET_TX_BD_PSB(__tx_bd)
#define SET_TX_BD_TX_BUFF_SIZE0_8822B(__tx_bd, __value) \
SET_TX_BD_TX_BUFF_SIZE0(__tx_bd, __value)
#define GET_TX_BD_TX_BUFF_SIZE0_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE0(__tx_bd)
/*TXBD_DW1*/
#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd)
/*TXBD_DW2*/
#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd)
/*TXBD_DW4*/
#define SET_TX_BD_A1_8822B(__tx_bd, __value) SET_TX_BD_A1(__tx_bd, __value)
#define GET_TX_BD_A1_8822B(__tx_bd) GET_TX_BD_A1(__tx_bd)
#define SET_TX_BD_TX_BUFF_SIZE1_8822B(__tx_bd, __value) \
SET_TX_BD_TX_BUFF_SIZE1(__tx_bd, __value)
#define GET_TX_BD_TX_BUFF_SIZE1_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE1(__tx_bd)
/*TXBD_DW5*/
#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd)
/*TXBD_DW6*/
#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd)
/*TXBD_DW8*/
#define SET_TX_BD_A2_8822B(__tx_bd, __value) SET_TX_BD_A2(__tx_bd, __value)
#define GET_TX_BD_A2_8822B(__tx_bd) GET_TX_BD_A2(__tx_bd)
#define SET_TX_BD_TX_BUFF_SIZE2_8822B(__tx_bd, __value) \
SET_TX_BD_TX_BUFF_SIZE2(__tx_bd, __value)
#define GET_TX_BD_TX_BUFF_SIZE2_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE2(__tx_bd)
/*TXBD_DW9*/
#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd)
/*TXBD_DW10*/
#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd)
/*TXBD_DW12*/
#define SET_TX_BD_A3_8822B(__tx_bd, __value) SET_TX_BD_A3(__tx_bd, __value)
#define GET_TX_BD_A3_8822B(__tx_bd) GET_TX_BD_A3(__tx_bd)
#define SET_TX_BD_TX_BUFF_SIZE3_8822B(__tx_bd, __value) \
SET_TX_BD_TX_BUFF_SIZE3(__tx_bd, __value)
#define GET_TX_BD_TX_BUFF_SIZE3_8822B(__tx_bd) GET_TX_BD_TX_BUFF_SIZE3(__tx_bd)
/*TXBD_DW13*/
#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd)
/*TXBD_DW14*/
#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__tx_bd, __value) \
SET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd, __value)
#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__tx_bd) \
GET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd)
#endif
drivers/staging/rtlwifi/halmac/halmac_tx_bd_nic.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_TX_BD_NIC_H_
#define _HALMAC_TX_BD_NIC_H_
/*TXBD_DW0*/
#define SET_TX_BD_OWN(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x00, 31, 1, __value)
#define GET_TX_BD_OWN(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x00, 31, 1)
#define SET_TX_BD_PSB(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x00, 16, 8, __value)
#define GET_TX_BD_PSB(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x00, 16, 8)
#define SET_TX_BD_TX_BUFF_SIZE0(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x00, 0, 16, __value)
#define GET_TX_BD_TX_BUFF_SIZE0(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x00, 0, 16)
/*TXBD_DW1*/
#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x04, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x04, 0, 32)
/*TXBD_DW2*/
#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x08, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x08, 0, 32)
/*TXBD_DW4*/
#define SET_TX_BD_A1(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x10, 31, 1, __value)
#define GET_TX_BD_A1(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x10, 31, 1)
#define SET_TX_BD_TX_BUFF_SIZE1(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x10, 0, 16, __value)
#define GET_TX_BD_TX_BUFF_SIZE1(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x10, 0, 16)
/*TXBD_DW5*/
#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x14, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x14, 0, 32)
/*TXBD_DW6*/
#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x18, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x18, 0, 32)
/*TXBD_DW8*/
#define SET_TX_BD_A2(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x20, 31, 1, __value)
#define GET_TX_BD_A2(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x20, 31, 1)
#define SET_TX_BD_TX_BUFF_SIZE2(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x20, 0, 16, __value)
#define GET_TX_BD_TX_BUFF_SIZE2(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x20, 0, 16)
/*TXBD_DW9*/
#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x24, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x24, 0, 32)
/*TXBD_DW10*/
#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x28, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x28, 0, 32)
/*TXBD_DW12*/
#define SET_TX_BD_A3(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x30, 31, 1, __value)
#define GET_TX_BD_A3(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x30, 31, 1)
#define SET_TX_BD_TX_BUFF_SIZE3(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x30, 0, 16, __value)
#define GET_TX_BD_TX_BUFF_SIZE3(__tx_bd) LE_BITS_TO_4BYTE(__tx_bd + 0x30, 0, 16)
/*TXBD_DW13*/
#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x34, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x34, 0, 32)
/*TXBD_DW14*/
#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd, __value) \
SET_BITS_TO_LE_4BYTE(__tx_bd + 0x38, 0, 32, __value)
#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__tx_bd) \
LE_BITS_TO_4BYTE(__tx_bd + 0x38, 0, 32)
#endif
drivers/staging/rtlwifi/halmac/halmac_tx_desc_chip.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_TX_DESC_CHIP_H_
#define _HALMAC_TX_DESC_CHIP_H_
/*TXDESC_WORD0*/
#define SET_TX_DESC_DISQSELSEQ_8822B(__tx_desc, __value) \
SET_TX_DESC_DISQSELSEQ(__tx_desc, __value)
#define GET_TX_DESC_DISQSELSEQ_8822B(__tx_desc) \
GET_TX_DESC_DISQSELSEQ(__tx_desc)
#define SET_TX_DESC_GF_8822B(__tx_desc, __value) \
SET_TX_DESC_GF(__tx_desc, __value)
#define GET_TX_DESC_GF_8822B(__tx_desc) GET_TX_DESC_GF(__tx_desc)
#define SET_TX_DESC_NO_ACM_8822B(__tx_desc, __value) \
SET_TX_DESC_NO_ACM(__tx_desc, __value)
#define GET_TX_DESC_NO_ACM_8822B(__tx_desc) GET_TX_DESC_NO_ACM(__tx_desc)
#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__tx_desc, __value) \
SET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc, __value)
#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__tx_desc) \
GET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc)
#define SET_TX_DESC_AMSDU_PAD_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_AMSDU_PAD_EN(__tx_desc, __value)
#define GET_TX_DESC_AMSDU_PAD_EN_8822B(__tx_desc) \
GET_TX_DESC_AMSDU_PAD_EN(__tx_desc)
#define SET_TX_DESC_LS_8822B(__tx_desc, __value) \
SET_TX_DESC_LS(__tx_desc, __value)
#define GET_TX_DESC_LS_8822B(__tx_desc) GET_TX_DESC_LS(__tx_desc)
#define SET_TX_DESC_HTC_8822B(__tx_desc, __value) \
SET_TX_DESC_HTC(__tx_desc, __value)
#define GET_TX_DESC_HTC_8822B(__tx_desc) GET_TX_DESC_HTC(__tx_desc)
#define SET_TX_DESC_BMC_8822B(__tx_desc, __value) \
SET_TX_DESC_BMC(__tx_desc, __value)
#define GET_TX_DESC_BMC_8822B(__tx_desc) GET_TX_DESC_BMC(__tx_desc)
#define SET_TX_DESC_OFFSET_8822B(__tx_desc, __value) \
SET_TX_DESC_OFFSET(__tx_desc, __value)
#define GET_TX_DESC_OFFSET_8822B(__tx_desc) GET_TX_DESC_OFFSET(__tx_desc)
#define SET_TX_DESC_TXPKTSIZE_8822B(__tx_desc, __value) \
SET_TX_DESC_TXPKTSIZE(__tx_desc, __value)
#define GET_TX_DESC_TXPKTSIZE_8822B(__tx_desc) GET_TX_DESC_TXPKTSIZE(__tx_desc)
/*TXDESC_WORD1*/
#define SET_TX_DESC_MOREDATA_8822B(__tx_desc, __value) \
SET_TX_DESC_MOREDATA(__tx_desc, __value)
#define GET_TX_DESC_MOREDATA_8822B(__tx_desc) GET_TX_DESC_MOREDATA(__tx_desc)
#define SET_TX_DESC_PKT_OFFSET_8822B(__tx_desc, __value) \
SET_TX_DESC_PKT_OFFSET(__tx_desc, __value)
#define GET_TX_DESC_PKT_OFFSET_8822B(__tx_desc) \
GET_TX_DESC_PKT_OFFSET(__tx_desc)
#define SET_TX_DESC_SEC_TYPE_8822B(__tx_desc, __value) \
SET_TX_DESC_SEC_TYPE(__tx_desc, __value)
#define GET_TX_DESC_SEC_TYPE_8822B(__tx_desc) GET_TX_DESC_SEC_TYPE(__tx_desc)
#define SET_TX_DESC_EN_DESC_ID_8822B(__tx_desc, __value) \
SET_TX_DESC_EN_DESC_ID(__tx_desc, __value)
#define GET_TX_DESC_EN_DESC_ID_8822B(__tx_desc) \
GET_TX_DESC_EN_DESC_ID(__tx_desc)
#define SET_TX_DESC_RATE_ID_8822B(__tx_desc, __value) \
SET_TX_DESC_RATE_ID(__tx_desc, __value)
#define GET_TX_DESC_RATE_ID_8822B(__tx_desc) GET_TX_DESC_RATE_ID(__tx_desc)
#define SET_TX_DESC_PIFS_8822B(__tx_desc, __value) \
SET_TX_DESC_PIFS(__tx_desc, __value)
#define GET_TX_DESC_PIFS_8822B(__tx_desc) GET_TX_DESC_PIFS(__tx_desc)
#define SET_TX_DESC_LSIG_TXOP_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_LSIG_TXOP_EN(__tx_desc, __value)
#define GET_TX_DESC_LSIG_TXOP_EN_8822B(__tx_desc) \
GET_TX_DESC_LSIG_TXOP_EN(__tx_desc)
#define SET_TX_DESC_RD_NAV_EXT_8822B(__tx_desc, __value) \
SET_TX_DESC_RD_NAV_EXT(__tx_desc, __value)
#define GET_TX_DESC_RD_NAV_EXT_8822B(__tx_desc) \
GET_TX_DESC_RD_NAV_EXT(__tx_desc)
#define SET_TX_DESC_QSEL_8822B(__tx_desc, __value) \
SET_TX_DESC_QSEL(__tx_desc, __value)
#define GET_TX_DESC_QSEL_8822B(__tx_desc) GET_TX_DESC_QSEL(__tx_desc)
#define SET_TX_DESC_MACID_8822B(__tx_desc, __value) \
SET_TX_DESC_MACID(__tx_desc, __value)
#define GET_TX_DESC_MACID_8822B(__tx_desc) GET_TX_DESC_MACID(__tx_desc)
/*TXDESC_WORD2*/
#define SET_TX_DESC_HW_AES_IV_8822B(__tx_desc, __value) \
SET_TX_DESC_HW_AES_IV(__tx_desc, __value)
#define GET_TX_DESC_HW_AES_IV_8822B(__tx_desc) GET_TX_DESC_HW_AES_IV(__tx_desc)
#define SET_TX_DESC_FTM_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_FTM_EN(__tx_desc, __value)
#define GET_TX_DESC_FTM_EN_8822B(__tx_desc) GET_TX_DESC_FTM_EN(__tx_desc)
#define SET_TX_DESC_G_ID_8822B(__tx_desc, __value) \
SET_TX_DESC_G_ID(__tx_desc, __value)
#define GET_TX_DESC_G_ID_8822B(__tx_desc) GET_TX_DESC_G_ID(__tx_desc)
#define SET_TX_DESC_BT_NULL_8822B(__tx_desc, __value) \
SET_TX_DESC_BT_NULL(__tx_desc, __value)
#define GET_TX_DESC_BT_NULL_8822B(__tx_desc) GET_TX_DESC_BT_NULL(__tx_desc)
#define SET_TX_DESC_AMPDU_DENSITY_8822B(__tx_desc, __value) \
SET_TX_DESC_AMPDU_DENSITY(__tx_desc, __value)
#define GET_TX_DESC_AMPDU_DENSITY_8822B(__tx_desc) \
GET_TX_DESC_AMPDU_DENSITY(__tx_desc)
#define SET_TX_DESC_SPE_RPT_8822B(__tx_desc, __value) \
SET_TX_DESC_SPE_RPT(__tx_desc, __value)
#define GET_TX_DESC_SPE_RPT_8822B(__tx_desc) GET_TX_DESC_SPE_RPT(__tx_desc)
#define SET_TX_DESC_RAW_8822B(__tx_desc, __value) \
SET_TX_DESC_RAW(__tx_desc, __value)
#define GET_TX_DESC_RAW_8822B(__tx_desc) GET_TX_DESC_RAW(__tx_desc)
#define SET_TX_DESC_MOREFRAG_8822B(__tx_desc, __value) \
SET_TX_DESC_MOREFRAG(__tx_desc, __value)
#define GET_TX_DESC_MOREFRAG_8822B(__tx_desc) GET_TX_DESC_MOREFRAG(__tx_desc)
#define SET_TX_DESC_BK_8822B(__tx_desc, __value) \
SET_TX_DESC_BK(__tx_desc, __value)
#define GET_TX_DESC_BK_8822B(__tx_desc) GET_TX_DESC_BK(__tx_desc)
#define SET_TX_DESC_NULL_1_8822B(__tx_desc, __value) \
SET_TX_DESC_NULL_1(__tx_desc, __value)
#define GET_TX_DESC_NULL_1_8822B(__tx_desc) GET_TX_DESC_NULL_1(__tx_desc)
#define SET_TX_DESC_NULL_0_8822B(__tx_desc, __value) \
SET_TX_DESC_NULL_0(__tx_desc, __value)
#define GET_TX_DESC_NULL_0_8822B(__tx_desc) GET_TX_DESC_NULL_0(__tx_desc)
#define SET_TX_DESC_RDG_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_RDG_EN(__tx_desc, __value)
#define GET_TX_DESC_RDG_EN_8822B(__tx_desc) GET_TX_DESC_RDG_EN(__tx_desc)
#define SET_TX_DESC_AGG_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_AGG_EN(__tx_desc, __value)
#define GET_TX_DESC_AGG_EN_8822B(__tx_desc) GET_TX_DESC_AGG_EN(__tx_desc)
#define SET_TX_DESC_CCA_RTS_8822B(__tx_desc, __value) \
SET_TX_DESC_CCA_RTS(__tx_desc, __value)
#define GET_TX_DESC_CCA_RTS_8822B(__tx_desc) GET_TX_DESC_CCA_RTS(__tx_desc)
#define SET_TX_DESC_TRI_FRAME_8822B(__tx_desc, __value) \
SET_TX_DESC_TRI_FRAME(__tx_desc, __value)
#define GET_TX_DESC_TRI_FRAME_8822B(__tx_desc) GET_TX_DESC_TRI_FRAME(__tx_desc)
#define SET_TX_DESC_P_AID_8822B(__tx_desc, __value) \
SET_TX_DESC_P_AID(__tx_desc, __value)
#define GET_TX_DESC_P_AID_8822B(__tx_desc) GET_TX_DESC_P_AID(__tx_desc)
/*TXDESC_WORD3*/
#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(__tx_desc, __value) \
SET_TX_DESC_AMPDU_MAX_TIME(__tx_desc, __value)
#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(__tx_desc) \
GET_TX_DESC_AMPDU_MAX_TIME(__tx_desc)
#define SET_TX_DESC_NDPA_8822B(__tx_desc, __value) \
SET_TX_DESC_NDPA(__tx_desc, __value)
#define GET_TX_DESC_NDPA_8822B(__tx_desc) GET_TX_DESC_NDPA(__tx_desc)
#define SET_TX_DESC_MAX_AGG_NUM_8822B(__tx_desc, __value) \
SET_TX_DESC_MAX_AGG_NUM(__tx_desc, __value)
#define GET_TX_DESC_MAX_AGG_NUM_8822B(__tx_desc) \
GET_TX_DESC_MAX_AGG_NUM(__tx_desc)
#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_USE_MAX_TIME_EN(__tx_desc, __value)
#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(__tx_desc) \
GET_TX_DESC_USE_MAX_TIME_EN(__tx_desc)
#define SET_TX_DESC_NAVUSEHDR_8822B(__tx_desc, __value) \
SET_TX_DESC_NAVUSEHDR(__tx_desc, __value)
#define GET_TX_DESC_NAVUSEHDR_8822B(__tx_desc) GET_TX_DESC_NAVUSEHDR(__tx_desc)
#define SET_TX_DESC_CHK_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_CHK_EN(__tx_desc, __value)
#define GET_TX_DESC_CHK_EN_8822B(__tx_desc) GET_TX_DESC_CHK_EN(__tx_desc)
#define SET_TX_DESC_HW_RTS_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_HW_RTS_EN(__tx_desc, __value)
#define GET_TX_DESC_HW_RTS_EN_8822B(__tx_desc) GET_TX_DESC_HW_RTS_EN(__tx_desc)
#define SET_TX_DESC_RTSEN_8822B(__tx_desc, __value) \
SET_TX_DESC_RTSEN(__tx_desc, __value)
#define GET_TX_DESC_RTSEN_8822B(__tx_desc) GET_TX_DESC_RTSEN(__tx_desc)
#define SET_TX_DESC_CTS2SELF_8822B(__tx_desc, __value) \
SET_TX_DESC_CTS2SELF(__tx_desc, __value)
#define GET_TX_DESC_CTS2SELF_8822B(__tx_desc) GET_TX_DESC_CTS2SELF(__tx_desc)
#define SET_TX_DESC_DISDATAFB_8822B(__tx_desc, __value) \
SET_TX_DESC_DISDATAFB(__tx_desc, __value)
#define GET_TX_DESC_DISDATAFB_8822B(__tx_desc) GET_TX_DESC_DISDATAFB(__tx_desc)
#define SET_TX_DESC_DISRTSFB_8822B(__tx_desc, __value) \
SET_TX_DESC_DISRTSFB(__tx_desc, __value)
#define GET_TX_DESC_DISRTSFB_8822B(__tx_desc) GET_TX_DESC_DISRTSFB(__tx_desc)
#define SET_TX_DESC_USE_RATE_8822B(__tx_desc, __value) \
SET_TX_DESC_USE_RATE(__tx_desc, __value)
#define GET_TX_DESC_USE_RATE_8822B(__tx_desc) GET_TX_DESC_USE_RATE(__tx_desc)
#define SET_TX_DESC_HW_SSN_SEL_8822B(__tx_desc, __value) \
SET_TX_DESC_HW_SSN_SEL(__tx_desc, __value)
#define GET_TX_DESC_HW_SSN_SEL_8822B(__tx_desc) \
GET_TX_DESC_HW_SSN_SEL(__tx_desc)
#define SET_TX_DESC_WHEADER_LEN_8822B(__tx_desc, __value) \
SET_TX_DESC_WHEADER_LEN(__tx_desc, __value)
#define GET_TX_DESC_WHEADER_LEN_8822B(__tx_desc) \
GET_TX_DESC_WHEADER_LEN(__tx_desc)
/*TXDESC_WORD4*/
#define SET_TX_DESC_PCTS_MASK_IDX_8822B(__tx_desc, __value) \
SET_TX_DESC_PCTS_MASK_IDX(__tx_desc, __value)
#define GET_TX_DESC_PCTS_MASK_IDX_8822B(__tx_desc) \
GET_TX_DESC_PCTS_MASK_IDX(__tx_desc)
#define SET_TX_DESC_PCTS_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_PCTS_EN(__tx_desc, __value)
#define GET_TX_DESC_PCTS_EN_8822B(__tx_desc) GET_TX_DESC_PCTS_EN(__tx_desc)
#define SET_TX_DESC_RTSRATE_8822B(__tx_desc, __value) \
SET_TX_DESC_RTSRATE(__tx_desc, __value)
#define GET_TX_DESC_RTSRATE_8822B(__tx_desc) GET_TX_DESC_RTSRATE(__tx_desc)
#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__tx_desc, __value) \
SET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc, __value)
#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__tx_desc) \
GET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc)
#define SET_TX_DESC_RTY_LMT_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_RTY_LMT_EN(__tx_desc, __value)
#define GET_TX_DESC_RTY_LMT_EN_8822B(__tx_desc) \
GET_TX_DESC_RTY_LMT_EN(__tx_desc)
#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__tx_desc, __value) \
SET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc, __value)
#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__tx_desc) \
GET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc)
#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc, __value)
#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__tx_desc) \
GET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc)
#define SET_TX_DESC_TRY_RATE_8822B(__tx_desc, __value) \
SET_TX_DESC_TRY_RATE(__tx_desc, __value)
#define GET_TX_DESC_TRY_RATE_8822B(__tx_desc) GET_TX_DESC_TRY_RATE(__tx_desc)
#define SET_TX_DESC_DATARATE_8822B(__tx_desc, __value) \
SET_TX_DESC_DATARATE(__tx_desc, __value)
#define GET_TX_DESC_DATARATE_8822B(__tx_desc) GET_TX_DESC_DATARATE(__tx_desc)
/*TXDESC_WORD5*/
#define SET_TX_DESC_POLLUTED_8822B(__tx_desc, __value) \
SET_TX_DESC_POLLUTED(__tx_desc, __value)
#define GET_TX_DESC_POLLUTED_8822B(__tx_desc) GET_TX_DESC_POLLUTED(__tx_desc)
#define SET_TX_DESC_TXPWR_OFSET_8822B(__tx_desc, __value) \
SET_TX_DESC_TXPWR_OFSET(__tx_desc, __value)
#define GET_TX_DESC_TXPWR_OFSET_8822B(__tx_desc) \
GET_TX_DESC_TXPWR_OFSET(__tx_desc)
#define SET_TX_DESC_TX_ANT_8822B(__tx_desc, __value) \
SET_TX_DESC_TX_ANT(__tx_desc, __value)
#define GET_TX_DESC_TX_ANT_8822B(__tx_desc) GET_TX_DESC_TX_ANT(__tx_desc)
#define SET_TX_DESC_PORT_ID_8822B(__tx_desc, __value) \
SET_TX_DESC_PORT_ID(__tx_desc, __value)
#define GET_TX_DESC_PORT_ID_8822B(__tx_desc) GET_TX_DESC_PORT_ID(__tx_desc)
#define SET_TX_DESC_MULTIPLE_PORT_8822B(__tx_desc, __value) \
SET_TX_DESC_MULTIPLE_PORT(__tx_desc, __value)
#define GET_TX_DESC_MULTIPLE_PORT_8822B(__tx_desc) \
GET_TX_DESC_MULTIPLE_PORT(__tx_desc)
#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc, __value)
#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__tx_desc) \
GET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc)
#define SET_TX_DESC_RTS_SC_8822B(__tx_desc, __value) \
SET_TX_DESC_RTS_SC(__tx_desc, __value)
#define GET_TX_DESC_RTS_SC_8822B(__tx_desc) GET_TX_DESC_RTS_SC(__tx_desc)
#define SET_TX_DESC_RTS_SHORT_8822B(__tx_desc, __value) \
SET_TX_DESC_RTS_SHORT(__tx_desc, __value)
#define GET_TX_DESC_RTS_SHORT_8822B(__tx_desc) GET_TX_DESC_RTS_SHORT(__tx_desc)
#define SET_TX_DESC_VCS_STBC_8822B(__tx_desc, __value) \
SET_TX_DESC_VCS_STBC(__tx_desc, __value)
#define GET_TX_DESC_VCS_STBC_8822B(__tx_desc) GET_TX_DESC_VCS_STBC(__tx_desc)
#define SET_TX_DESC_DATA_STBC_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_STBC(__tx_desc, __value)
#define GET_TX_DESC_DATA_STBC_8822B(__tx_desc) GET_TX_DESC_DATA_STBC(__tx_desc)
#define SET_TX_DESC_DATA_LDPC_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_LDPC(__tx_desc, __value)
#define GET_TX_DESC_DATA_LDPC_8822B(__tx_desc) GET_TX_DESC_DATA_LDPC(__tx_desc)
#define SET_TX_DESC_DATA_BW_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_BW(__tx_desc, __value)
#define GET_TX_DESC_DATA_BW_8822B(__tx_desc) GET_TX_DESC_DATA_BW(__tx_desc)
#define SET_TX_DESC_DATA_SHORT_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_SHORT(__tx_desc, __value)
#define GET_TX_DESC_DATA_SHORT_8822B(__tx_desc) \
GET_TX_DESC_DATA_SHORT(__tx_desc)
#define SET_TX_DESC_DATA_SC_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_SC(__tx_desc, __value)
#define GET_TX_DESC_DATA_SC_8822B(__tx_desc) GET_TX_DESC_DATA_SC(__tx_desc)
/*TXDESC_WORD6*/
#define SET_TX_DESC_ANTSEL_D_8822B(__tx_desc, __value) \
SET_TX_DESC_ANTSEL_D(__tx_desc, __value)
#define GET_TX_DESC_ANTSEL_D_8822B(__tx_desc) GET_TX_DESC_ANTSEL_D(__tx_desc)
#define SET_TX_DESC_ANT_MAPD_8822B(__tx_desc, __value) \
SET_TX_DESC_ANT_MAPD(__tx_desc, __value)
#define GET_TX_DESC_ANT_MAPD_8822B(__tx_desc) GET_TX_DESC_ANT_MAPD(__tx_desc)
#define SET_TX_DESC_ANT_MAPC_8822B(__tx_desc, __value) \
SET_TX_DESC_ANT_MAPC(__tx_desc, __value)
#define GET_TX_DESC_ANT_MAPC_8822B(__tx_desc) GET_TX_DESC_ANT_MAPC(__tx_desc)
#define SET_TX_DESC_ANT_MAPB_8822B(__tx_desc, __value) \
SET_TX_DESC_ANT_MAPB(__tx_desc, __value)
#define GET_TX_DESC_ANT_MAPB_8822B(__tx_desc) GET_TX_DESC_ANT_MAPB(__tx_desc)
#define SET_TX_DESC_ANT_MAPA_8822B(__tx_desc, __value) \
SET_TX_DESC_ANT_MAPA(__tx_desc, __value)
#define GET_TX_DESC_ANT_MAPA_8822B(__tx_desc) GET_TX_DESC_ANT_MAPA(__tx_desc)
#define SET_TX_DESC_ANTSEL_C_8822B(__tx_desc, __value) \
SET_TX_DESC_ANTSEL_C(__tx_desc, __value)
#define GET_TX_DESC_ANTSEL_C_8822B(__tx_desc) GET_TX_DESC_ANTSEL_C(__tx_desc)
#define SET_TX_DESC_ANTSEL_B_8822B(__tx_desc, __value) \
SET_TX_DESC_ANTSEL_B(__tx_desc, __value)
#define GET_TX_DESC_ANTSEL_B_8822B(__tx_desc) GET_TX_DESC_ANTSEL_B(__tx_desc)
#define SET_TX_DESC_ANTSEL_A_8822B(__tx_desc, __value) \
SET_TX_DESC_ANTSEL_A(__tx_desc, __value)
#define GET_TX_DESC_ANTSEL_A_8822B(__tx_desc) GET_TX_DESC_ANTSEL_A(__tx_desc)
#define SET_TX_DESC_MBSSID_8822B(__tx_desc, __value) \
SET_TX_DESC_MBSSID(__tx_desc, __value)
#define GET_TX_DESC_MBSSID_8822B(__tx_desc) GET_TX_DESC_MBSSID(__tx_desc)
#define SET_TX_DESC_SW_DEFINE_8822B(__tx_desc, __value) \
SET_TX_DESC_SW_DEFINE(__tx_desc, __value)
#define GET_TX_DESC_SW_DEFINE_8822B(__tx_desc) GET_TX_DESC_SW_DEFINE(__tx_desc)
/*TXDESC_WORD7*/
#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(__tx_desc, __value) \
SET_TX_DESC_DMA_TXAGG_NUM(__tx_desc, __value)
#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(__tx_desc) \
GET_TX_DESC_DMA_TXAGG_NUM(__tx_desc)
#define SET_TX_DESC_FINAL_DATA_RATE_8822B(__tx_desc, __value) \
SET_TX_DESC_FINAL_DATA_RATE(__tx_desc, __value)
#define GET_TX_DESC_FINAL_DATA_RATE_8822B(__tx_desc) \
GET_TX_DESC_FINAL_DATA_RATE(__tx_desc)
#define SET_TX_DESC_NTX_MAP_8822B(__tx_desc, __value) \
SET_TX_DESC_NTX_MAP(__tx_desc, __value)
#define GET_TX_DESC_NTX_MAP_8822B(__tx_desc) GET_TX_DESC_NTX_MAP(__tx_desc)
#define SET_TX_DESC_TX_BUFF_SIZE_8822B(__tx_desc, __value) \
SET_TX_DESC_TX_BUFF_SIZE(__tx_desc, __value)
#define GET_TX_DESC_TX_BUFF_SIZE_8822B(__tx_desc) \
GET_TX_DESC_TX_BUFF_SIZE(__tx_desc)
#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(__tx_desc, __value) \
SET_TX_DESC_TXDESC_CHECKSUM(__tx_desc, __value)
#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(__tx_desc) \
GET_TX_DESC_TXDESC_CHECKSUM(__tx_desc)
#define SET_TX_DESC_TIMESTAMP_8822B(__tx_desc, __value) \
SET_TX_DESC_TIMESTAMP(__tx_desc, __value)
#define GET_TX_DESC_TIMESTAMP_8822B(__tx_desc) GET_TX_DESC_TIMESTAMP(__tx_desc)
/*TXDESC_WORD8*/
#define SET_TX_DESC_TXWIFI_CP_8822B(__tx_desc, __value) \
SET_TX_DESC_TXWIFI_CP(__tx_desc, __value)
#define GET_TX_DESC_TXWIFI_CP_8822B(__tx_desc) GET_TX_DESC_TXWIFI_CP(__tx_desc)
#define SET_TX_DESC_MAC_CP_8822B(__tx_desc, __value) \
SET_TX_DESC_MAC_CP(__tx_desc, __value)
#define GET_TX_DESC_MAC_CP_8822B(__tx_desc) GET_TX_DESC_MAC_CP(__tx_desc)
#define SET_TX_DESC_STW_PKTRE_DIS_8822B(__tx_desc, __value) \
SET_TX_DESC_STW_PKTRE_DIS(__tx_desc, __value)
#define GET_TX_DESC_STW_PKTRE_DIS_8822B(__tx_desc) \
GET_TX_DESC_STW_PKTRE_DIS(__tx_desc)
#define SET_TX_DESC_STW_RB_DIS_8822B(__tx_desc, __value) \
SET_TX_DESC_STW_RB_DIS(__tx_desc, __value)
#define GET_TX_DESC_STW_RB_DIS_8822B(__tx_desc) \
GET_TX_DESC_STW_RB_DIS(__tx_desc)
#define SET_TX_DESC_STW_RATE_DIS_8822B(__tx_desc, __value) \
SET_TX_DESC_STW_RATE_DIS(__tx_desc, __value)
#define GET_TX_DESC_STW_RATE_DIS_8822B(__tx_desc) \
GET_TX_DESC_STW_RATE_DIS(__tx_desc)
#define SET_TX_DESC_STW_ANT_DIS_8822B(__tx_desc, __value) \
SET_TX_DESC_STW_ANT_DIS(__tx_desc, __value)
#define GET_TX_DESC_STW_ANT_DIS_8822B(__tx_desc) \
GET_TX_DESC_STW_ANT_DIS(__tx_desc)
#define SET_TX_DESC_STW_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_STW_EN(__tx_desc, __value)
#define GET_TX_DESC_STW_EN_8822B(__tx_desc) GET_TX_DESC_STW_EN(__tx_desc)
#define SET_TX_DESC_SMH_EN_8822B(__tx_desc, __value) \
SET_TX_DESC_SMH_EN(__tx_desc, __value)
#define GET_TX_DESC_SMH_EN_8822B(__tx_desc) GET_TX_DESC_SMH_EN(__tx_desc)
#define SET_TX_DESC_TAILPAGE_L_8822B(__tx_desc, __value) \
SET_TX_DESC_TAILPAGE_L(__tx_desc, __value)
#define GET_TX_DESC_TAILPAGE_L_8822B(__tx_desc) \
GET_TX_DESC_TAILPAGE_L(__tx_desc)
#define SET_TX_DESC_SDIO_DMASEQ_8822B(__tx_desc, __value) \
SET_TX_DESC_SDIO_DMASEQ(__tx_desc, __value)
#define GET_TX_DESC_SDIO_DMASEQ_8822B(__tx_desc) \
GET_TX_DESC_SDIO_DMASEQ(__tx_desc)
#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(__tx_desc, __value) \
SET_TX_DESC_NEXTHEADPAGE_L(__tx_desc, __value)
#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(__tx_desc) \
GET_TX_DESC_NEXTHEADPAGE_L(__tx_desc)
#define SET_TX_DESC_EN_HWSEQ_8822B(__tx_desc, __value) \
SET_TX_DESC_EN_HWSEQ(__tx_desc, __value)
#define GET_TX_DESC_EN_HWSEQ_8822B(__tx_desc) GET_TX_DESC_EN_HWSEQ(__tx_desc)
#define SET_TX_DESC_EN_HWEXSEQ_8822B(__tx_desc, __value) \
SET_TX_DESC_EN_HWEXSEQ(__tx_desc, __value)
#define GET_TX_DESC_EN_HWEXSEQ_8822B(__tx_desc) \
GET_TX_DESC_EN_HWEXSEQ(__tx_desc)
#define SET_TX_DESC_DATA_RC_8822B(__tx_desc, __value) \
SET_TX_DESC_DATA_RC(__tx_desc, __value)
#define GET_TX_DESC_DATA_RC_8822B(__tx_desc) GET_TX_DESC_DATA_RC(__tx_desc)
#define SET_TX_DESC_BAR_RTY_TH_8822B(__tx_desc, __value) \
SET_TX_DESC_BAR_RTY_TH(__tx_desc, __value)
#define GET_TX_DESC_BAR_RTY_TH_8822B(__tx_desc) \
GET_TX_DESC_BAR_RTY_TH(__tx_desc)
#define SET_TX_DESC_RTS_RC_8822B(__tx_desc, __value) \
SET_TX_DESC_RTS_RC(__tx_desc, __value)
#define GET_TX_DESC_RTS_RC_8822B(__tx_desc) GET_TX_DESC_RTS_RC(__tx_desc)
/*TXDESC_WORD9*/
#define SET_TX_DESC_TAILPAGE_H_8822B(__tx_desc, __value) \
SET_TX_DESC_TAILPAGE_H(__tx_desc, __value)
#define GET_TX_DESC_TAILPAGE_H_8822B(__tx_desc) \
GET_TX_DESC_TAILPAGE_H(__tx_desc)
#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(__tx_desc, __value) \
SET_TX_DESC_NEXTHEADPAGE_H(__tx_desc, __value)
#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(__tx_desc) \
GET_TX_DESC_NEXTHEADPAGE_H(__tx_desc)
#define SET_TX_DESC_SW_SEQ_8822B(__tx_desc, __value) \
SET_TX_DESC_SW_SEQ(__tx_desc, __value)
#define GET_TX_DESC_SW_SEQ_8822B(__tx_desc) GET_TX_DESC_SW_SEQ(__tx_desc)
#define SET_TX_DESC_TXBF_PATH_8822B(__tx_desc, __value) \
SET_TX_DESC_TXBF_PATH(__tx_desc, __value)
#define GET_TX_DESC_TXBF_PATH_8822B(__tx_desc) GET_TX_DESC_TXBF_PATH(__tx_desc)
#define SET_TX_DESC_PADDING_LEN_8822B(__tx_desc, __value) \
SET_TX_DESC_PADDING_LEN(__tx_desc, __value)
#define GET_TX_DESC_PADDING_LEN_8822B(__tx_desc) \
GET_TX_DESC_PADDING_LEN(__tx_desc)
#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__tx_desc, __value) \
SET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc, __value)
#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__tx_desc) \
GET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc)
/*WORD10*/
#define SET_TX_DESC_MU_DATARATE_8822B(__tx_desc, __value) \
SET_TX_DESC_MU_DATARATE(__tx_desc, __value)
#define GET_TX_DESC_MU_DATARATE_8822B(__tx_desc) \
GET_TX_DESC_MU_DATARATE(__tx_desc)
#define SET_TX_DESC_MU_RC_8822B(__tx_desc, __value) \
SET_TX_DESC_MU_RC(__tx_desc, __value)
#define GET_TX_DESC_MU_RC_8822B(__tx_desc) GET_TX_DESC_MU_RC(__tx_desc)
#define SET_TX_DESC_SND_PKT_SEL_8822B(__tx_desc, __value) \
SET_TX_DESC_SND_PKT_SEL(__tx_desc, __value)
#define GET_TX_DESC_SND_PKT_SEL_8822B(__tx_desc) \
GET_TX_DESC_SND_PKT_SEL(__tx_desc)
#endif
drivers/staging/rtlwifi/halmac/halmac_tx_desc_nic.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_TX_DESC_NIC_H_
#define _HALMAC_TX_DESC_NIC_H_
/*TXDESC_WORD0*/
#define SET_TX_DESC_DISQSELSEQ(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 31, 1, __value)
#define GET_TX_DESC_DISQSELSEQ(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x00, 31, 1)
#define SET_TX_DESC_GF(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 30, 1, __value)
#define GET_TX_DESC_GF(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 30, 1)
#define SET_TX_DESC_NO_ACM(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 29, 1, __value)
#define GET_TX_DESC_NO_ACM(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 29, 1)
#define SET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 28, 1, __value)
#define GET_TX_DESC_BCNPKT_TSF_CTRL(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x00, 28, 1)
#define SET_TX_DESC_AMSDU_PAD_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 27, 1, __value)
#define GET_TX_DESC_AMSDU_PAD_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x00, 27, 1)
#define SET_TX_DESC_LS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 26, 1, __value)
#define GET_TX_DESC_LS(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 26, 1)
#define SET_TX_DESC_HTC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 25, 1, __value)
#define GET_TX_DESC_HTC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 25, 1)
#define SET_TX_DESC_BMC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 24, 1, __value)
#define GET_TX_DESC_BMC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 24, 1)
#define SET_TX_DESC_OFFSET(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 16, 8, __value)
#define GET_TX_DESC_OFFSET(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x00, 16, 8)
#define SET_TX_DESC_TXPKTSIZE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x00, 0, 16, __value)
#define GET_TX_DESC_TXPKTSIZE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x00, 0, 16)
/*TXDESC_WORD1*/
#define SET_TX_DESC_MOREDATA(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 29, 1, __value)
#define GET_TX_DESC_MOREDATA(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 29, 1)
#define SET_TX_DESC_PKT_OFFSET(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 24, 5, __value)
#define GET_TX_DESC_PKT_OFFSET(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 24, 5)
#define SET_TX_DESC_SEC_TYPE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 22, 2, __value)
#define GET_TX_DESC_SEC_TYPE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 22, 2)
#define SET_TX_DESC_EN_DESC_ID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 21, 1, __value)
#define GET_TX_DESC_EN_DESC_ID(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 21, 1)
#define SET_TX_DESC_RATE_ID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 16, 5, __value)
#define GET_TX_DESC_RATE_ID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 16, 5)
#define SET_TX_DESC_PIFS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 15, 1, __value)
#define GET_TX_DESC_PIFS(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 15, 1)
#define SET_TX_DESC_LSIG_TXOP_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 14, 1, __value)
#define GET_TX_DESC_LSIG_TXOP_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 14, 1)
#define SET_TX_DESC_RD_NAV_EXT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 13, 1, __value)
#define GET_TX_DESC_RD_NAV_EXT(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x04, 13, 1)
#define SET_TX_DESC_QSEL(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 8, 5, __value)
#define GET_TX_DESC_QSEL(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 8, 5)
#define SET_TX_DESC_MACID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x04, 0, 7, __value)
#define GET_TX_DESC_MACID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x04, 0, 7)
/*TXDESC_WORD2*/
#define SET_TX_DESC_HW_AES_IV(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 31, 1, __value)
#define GET_TX_DESC_HW_AES_IV(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x08, 31, 1)
#define SET_TX_DESC_FTM_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 30, 1, __value)
#define GET_TX_DESC_FTM_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 30, 1)
#define SET_TX_DESC_G_ID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 24, 6, __value)
#define GET_TX_DESC_G_ID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 24, 6)
#define SET_TX_DESC_BT_NULL(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 23, 1, __value)
#define GET_TX_DESC_BT_NULL(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 23, 1)
#define SET_TX_DESC_AMPDU_DENSITY(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 20, 3, __value)
#define GET_TX_DESC_AMPDU_DENSITY(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x08, 20, 3)
#ifdef SET_TX_DESC_SPE_RPT
#undef SET_TX_DESC_SPE_RPT
#endif
#define SET_TX_DESC_SPE_RPT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 19, 1, __value)
#define GET_TX_DESC_SPE_RPT(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 19, 1)
#define SET_TX_DESC_RAW(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 18, 1, __value)
#define GET_TX_DESC_RAW(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 18, 1)
#define SET_TX_DESC_MOREFRAG(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 17, 1, __value)
#define GET_TX_DESC_MOREFRAG(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x08, 17, 1)
#define SET_TX_DESC_BK(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 16, 1, __value)
#define GET_TX_DESC_BK(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 16, 1)
#define SET_TX_DESC_NULL_1(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 15, 1, __value)
#define GET_TX_DESC_NULL_1(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 15, 1)
#define SET_TX_DESC_NULL_0(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 14, 1, __value)
#define GET_TX_DESC_NULL_0(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 14, 1)
#define SET_TX_DESC_RDG_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 13, 1, __value)
#define GET_TX_DESC_RDG_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 13, 1)
#define SET_TX_DESC_AGG_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 12, 1, __value)
#define GET_TX_DESC_AGG_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 12, 1)
#define SET_TX_DESC_CCA_RTS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 10, 2, __value)
#define GET_TX_DESC_CCA_RTS(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 10, 2)
#define SET_TX_DESC_TRI_FRAME(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 9, 1, __value)
#define GET_TX_DESC_TRI_FRAME(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x08, 9, 1)
#define SET_TX_DESC_P_AID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x08, 0, 9, __value)
#define GET_TX_DESC_P_AID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x08, 0, 9)
/*TXDESC_WORD3*/
#define SET_TX_DESC_AMPDU_MAX_TIME(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 24, 8, __value)
#define GET_TX_DESC_AMPDU_MAX_TIME(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 24, 8)
#define SET_TX_DESC_NDPA(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 22, 2, __value)
#define GET_TX_DESC_NDPA(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 22, 2)
#define SET_TX_DESC_MAX_AGG_NUM(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 17, 5, __value)
#define GET_TX_DESC_MAX_AGG_NUM(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 17, 5)
#define SET_TX_DESC_USE_MAX_TIME_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 16, 1, __value)
#define GET_TX_DESC_USE_MAX_TIME_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 16, 1)
#define SET_TX_DESC_NAVUSEHDR(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 15, 1, __value)
#define GET_TX_DESC_NAVUSEHDR(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 15, 1)
#define SET_TX_DESC_CHK_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 14, 1, __value)
#define GET_TX_DESC_CHK_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 14, 1)
#define SET_TX_DESC_HW_RTS_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 13, 1, __value)
#define GET_TX_DESC_HW_RTS_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 13, 1)
#define SET_TX_DESC_RTSEN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 12, 1, __value)
#define GET_TX_DESC_RTSEN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 12, 1)
#define SET_TX_DESC_CTS2SELF(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 11, 1, __value)
#define GET_TX_DESC_CTS2SELF(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 11, 1)
#define SET_TX_DESC_DISDATAFB(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 10, 1, __value)
#define GET_TX_DESC_DISDATAFB(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 10, 1)
#define SET_TX_DESC_DISRTSFB(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 9, 1, __value)
#define GET_TX_DESC_DISRTSFB(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 9, 1)
#define SET_TX_DESC_USE_RATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 8, 1, __value)
#define GET_TX_DESC_USE_RATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 8, 1)
#define SET_TX_DESC_HW_SSN_SEL(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 6, 2, __value)
#define GET_TX_DESC_HW_SSN_SEL(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 6, 2)
#define SET_TX_DESC_WHEADER_LEN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x0C, 0, 5, __value)
#define GET_TX_DESC_WHEADER_LEN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x0C, 0, 5)
/*TXDESC_WORD4*/
#define SET_TX_DESC_PCTS_MASK_IDX(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 30, 2, __value)
#define GET_TX_DESC_PCTS_MASK_IDX(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x10, 30, 2)
#define SET_TX_DESC_PCTS_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 29, 1, __value)
#define GET_TX_DESC_PCTS_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 29, 1)
#define SET_TX_DESC_RTSRATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 24, 5, __value)
#define GET_TX_DESC_RTSRATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 24, 5)
#define SET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 18, 6, __value)
#define GET_TX_DESC_RTS_DATA_RTY_LMT(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x10, 18, 6)
#define SET_TX_DESC_RTY_LMT_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 17, 1, __value)
#define GET_TX_DESC_RTY_LMT_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x10, 17, 1)
#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 13, 4, __value)
#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x10, 13, 4)
#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 8, 5, __value)
#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x10, 8, 5)
#define SET_TX_DESC_TRY_RATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 7, 1, __value)
#define GET_TX_DESC_TRY_RATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 7, 1)
#define SET_TX_DESC_DATARATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x10, 0, 7, __value)
#define GET_TX_DESC_DATARATE(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x10, 0, 7)
/*TXDESC_WORD5*/
#define SET_TX_DESC_POLLUTED(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 31, 1, __value)
#define GET_TX_DESC_POLLUTED(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 31, 1)
#define SET_TX_DESC_TXPWR_OFSET(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 28, 3, __value)
#define GET_TX_DESC_TXPWR_OFSET(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 28, 3)
#define SET_TX_DESC_TX_ANT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 24, 4, __value)
#define GET_TX_DESC_TX_ANT(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 24, 4)
#define SET_TX_DESC_PORT_ID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 21, 3, __value)
#define GET_TX_DESC_PORT_ID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 21, 3)
#define SET_TX_DESC_MULTIPLE_PORT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 18, 3, __value)
#define GET_TX_DESC_MULTIPLE_PORT(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 18, 3)
#define SET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 17, 1, __value)
#define GET_TX_DESC_SIGNALING_TAPKT_EN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 17, 1)
#define SET_TX_DESC_RTS_SC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 13, 4, __value)
#define GET_TX_DESC_RTS_SC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 13, 4)
#define SET_TX_DESC_RTS_SHORT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 12, 1, __value)
#define GET_TX_DESC_RTS_SHORT(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 12, 1)
#define SET_TX_DESC_VCS_STBC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 10, 2, __value)
#define GET_TX_DESC_VCS_STBC(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 10, 2)
#define SET_TX_DESC_DATA_STBC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 8, 2, __value)
#define GET_TX_DESC_DATA_STBC(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 8, 2)
#define SET_TX_DESC_DATA_LDPC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 7, 1, __value)
#define GET_TX_DESC_DATA_LDPC(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 7, 1)
#define SET_TX_DESC_DATA_BW(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 5, 2, __value)
#define GET_TX_DESC_DATA_BW(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 5, 2)
#define SET_TX_DESC_DATA_SHORT(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 4, 1, __value)
#define GET_TX_DESC_DATA_SHORT(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x14, 4, 1)
#define SET_TX_DESC_DATA_SC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x14, 0, 4, __value)
#define GET_TX_DESC_DATA_SC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x14, 0, 4)
/*TXDESC_WORD6*/
#define SET_TX_DESC_ANTSEL_D(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 30, 2, __value)
#define GET_TX_DESC_ANTSEL_D(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 30, 2)
#define SET_TX_DESC_ANT_MAPD(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 28, 2, __value)
#define GET_TX_DESC_ANT_MAPD(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 28, 2)
#define SET_TX_DESC_ANT_MAPC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 26, 2, __value)
#define GET_TX_DESC_ANT_MAPC(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 26, 2)
#define SET_TX_DESC_ANT_MAPB(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 24, 2, __value)
#define GET_TX_DESC_ANT_MAPB(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 24, 2)
#define SET_TX_DESC_ANT_MAPA(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 22, 2, __value)
#define GET_TX_DESC_ANT_MAPA(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 22, 2)
#define SET_TX_DESC_ANTSEL_C(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 20, 2, __value)
#define GET_TX_DESC_ANTSEL_C(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 20, 2)
#define SET_TX_DESC_ANTSEL_B(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 18, 2, __value)
#define GET_TX_DESC_ANTSEL_B(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 18, 2)
#define SET_TX_DESC_ANTSEL_A(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 16, 2, __value)
#define GET_TX_DESC_ANTSEL_A(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 16, 2)
#define SET_TX_DESC_MBSSID(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 12, 4, __value)
#define GET_TX_DESC_MBSSID(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x18, 12, 4)
#ifdef SET_TX_DESC_SW_DEFINE
#undef SET_TX_DESC_SW_DEFINE
#endif
#define SET_TX_DESC_SW_DEFINE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x18, 0, 12, __value)
#define GET_TX_DESC_SW_DEFINE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x18, 0, 12)
/*TXDESC_WORD7*/
#define SET_TX_DESC_DMA_TXAGG_NUM(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 24, 8, __value)
#define GET_TX_DESC_DMA_TXAGG_NUM(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 24, 8)
#define SET_TX_DESC_FINAL_DATA_RATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 24, 8, __value)
#define GET_TX_DESC_FINAL_DATA_RATE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 24, 8)
#define SET_TX_DESC_NTX_MAP(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 20, 4, __value)
#define GET_TX_DESC_NTX_MAP(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 20, 4)
#define SET_TX_DESC_TX_BUFF_SIZE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 0, 16, __value)
#define GET_TX_DESC_TX_BUFF_SIZE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 0, 16)
#define SET_TX_DESC_TXDESC_CHECKSUM(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 0, 16, __value)
#define GET_TX_DESC_TXDESC_CHECKSUM(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 0, 16)
#define SET_TX_DESC_TIMESTAMP(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x1C, 0, 16, __value)
#define GET_TX_DESC_TIMESTAMP(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x1C, 0, 16)
/*TXDESC_WORD8*/
#define SET_TX_DESC_TXWIFI_CP(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 31, 1, __value)
#define GET_TX_DESC_TXWIFI_CP(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 31, 1)
#define SET_TX_DESC_MAC_CP(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 30, 1, __value)
#define GET_TX_DESC_MAC_CP(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 30, 1)
#define SET_TX_DESC_STW_PKTRE_DIS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 29, 1, __value)
#define GET_TX_DESC_STW_PKTRE_DIS(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 29, 1)
#define SET_TX_DESC_STW_RB_DIS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 28, 1, __value)
#define GET_TX_DESC_STW_RB_DIS(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 28, 1)
#define SET_TX_DESC_STW_RATE_DIS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 27, 1, __value)
#define GET_TX_DESC_STW_RATE_DIS(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 27, 1)
#define SET_TX_DESC_STW_ANT_DIS(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 26, 1, __value)
#define GET_TX_DESC_STW_ANT_DIS(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 26, 1)
#define SET_TX_DESC_STW_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 25, 1, __value)
#define GET_TX_DESC_STW_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 25, 1)
#define SET_TX_DESC_SMH_EN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 24, 1, __value)
#define GET_TX_DESC_SMH_EN(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 24, 1)
#define SET_TX_DESC_TAILPAGE_L(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 24, 8, __value)
#define GET_TX_DESC_TAILPAGE_L(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 24, 8)
#define SET_TX_DESC_SDIO_DMASEQ(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 16, 8, __value)
#define GET_TX_DESC_SDIO_DMASEQ(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 16, 8)
#define SET_TX_DESC_NEXTHEADPAGE_L(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 16, 8, __value)
#define GET_TX_DESC_NEXTHEADPAGE_L(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 16, 8)
#define SET_TX_DESC_EN_HWSEQ(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 15, 1, __value)
#define GET_TX_DESC_EN_HWSEQ(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 15, 1)
#define SET_TX_DESC_EN_HWEXSEQ(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 14, 1, __value)
#define GET_TX_DESC_EN_HWEXSEQ(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 14, 1)
#define SET_TX_DESC_DATA_RC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 8, 6, __value)
#define GET_TX_DESC_DATA_RC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 8, 6)
#define SET_TX_DESC_BAR_RTY_TH(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 6, 2, __value)
#define GET_TX_DESC_BAR_RTY_TH(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x20, 6, 2)
#define SET_TX_DESC_RTS_RC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x20, 0, 6, __value)
#define GET_TX_DESC_RTS_RC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x20, 0, 6)
/*TXDESC_WORD9*/
#define SET_TX_DESC_TAILPAGE_H(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 28, 4, __value)
#define GET_TX_DESC_TAILPAGE_H(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x24, 28, 4)
#define SET_TX_DESC_NEXTHEADPAGE_H(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 24, 4, __value)
#define GET_TX_DESC_NEXTHEADPAGE_H(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x24, 24, 4)
#define SET_TX_DESC_SW_SEQ(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 12, 12, __value)
#define GET_TX_DESC_SW_SEQ(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x24, 12, 12)
#define SET_TX_DESC_TXBF_PATH(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 11, 1, __value)
#define GET_TX_DESC_TXBF_PATH(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x24, 11, 1)
#define SET_TX_DESC_PADDING_LEN(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 0, 11, __value)
#define GET_TX_DESC_PADDING_LEN(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x24, 0, 11)
#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x24, 0, 8, __value)
#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x24, 0, 8)
/*WORD10*/
#define SET_TX_DESC_MU_DATARATE(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x28, 8, 8, __value)
#define GET_TX_DESC_MU_DATARATE(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x28, 8, 8)
#define SET_TX_DESC_MU_RC(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x28, 4, 4, __value)
#define GET_TX_DESC_MU_RC(__tx_desc) LE_BITS_TO_4BYTE(__tx_desc + 0x28, 4, 4)
#define SET_TX_DESC_SND_PKT_SEL(__tx_desc, __value) \
SET_BITS_TO_LE_4BYTE(__tx_desc + 0x28, 0, 2, __value)
#define GET_TX_DESC_SND_PKT_SEL(__tx_desc) \
LE_BITS_TO_4BYTE(__tx_desc + 0x28, 0, 2)
#endif
drivers/staging/rtlwifi/halmac/halmac_type.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _HALMAC_TYPE_H_
#define _HALMAC_TYPE_H_
#include "halmac_2_platform.h"
#include "halmac_fw_info.h"
#include "halmac_intf_phy_cmd.h"
#define HALMAC_SCAN_CH_NUM_MAX 28
#define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */
#define HALMAC_PHY_PARAMETER_SIZE 12
#define HALMAC_PHY_PARAMETER_MAX_NUM 128
#define HALMAC_MAX_SSID_LEN 32
#define HALMAC_SUPPORT_NLO_NUM 16
#define HALMAC_SUPPORT_PROBE_REQ_NUM 8
#define HALMC_DDMA_POLLING_COUNT 1000
#define API_ARRAY_SIZE 32
/* platform api */
#define PLATFORM_SDIO_CMD52_READ \
halmac_adapter->halmac_platform_api->SDIO_CMD52_READ
#define PLATFORM_SDIO_CMD53_READ_8 \
halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_8
#define PLATFORM_SDIO_CMD53_READ_16 \
halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_16
#define PLATFORM_SDIO_CMD53_READ_32 \
halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_32
#define PLATFORM_SDIO_CMD53_READ_N \
halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_N
#define PLATFORM_SDIO_CMD52_WRITE \
halmac_adapter->halmac_platform_api->SDIO_CMD52_WRITE
#define PLATFORM_SDIO_CMD53_WRITE_8 \
halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_8
#define PLATFORM_SDIO_CMD53_WRITE_16 \
halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_16
#define PLATFORM_SDIO_CMD53_WRITE_32 \
halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_32
#define PLATFORM_REG_READ_8 halmac_adapter->halmac_platform_api->REG_READ_8
#define PLATFORM_REG_READ_16 halmac_adapter->halmac_platform_api->REG_READ_16
#define PLATFORM_REG_READ_32 halmac_adapter->halmac_platform_api->REG_READ_32
#define PLATFORM_REG_WRITE_8 halmac_adapter->halmac_platform_api->REG_WRITE_8
#define PLATFORM_REG_WRITE_16 halmac_adapter->halmac_platform_api->REG_WRITE_16
#define PLATFORM_REG_WRITE_32 halmac_adapter->halmac_platform_api->REG_WRITE_32
#define PLATFORM_SEND_RSVD_PAGE \
halmac_adapter->halmac_platform_api->SEND_RSVD_PAGE
#define PLATFORM_SEND_H2C_PKT halmac_adapter->halmac_platform_api->SEND_H2C_PKT
#define PLATFORM_EVENT_INDICATION \
halmac_adapter->halmac_platform_api->EVENT_INDICATION
#define HALMAC_RT_TRACE(drv_adapter, comp, level, fmt, ...) \
RT_TRACE(drv_adapter, COMP_HALMAC, level, fmt, ##__VA_ARGS__)
#define HALMAC_REG_READ_8 halmac_api->halmac_reg_read_8
#define HALMAC_REG_READ_16 halmac_api->halmac_reg_read_16
#define HALMAC_REG_READ_32 halmac_api->halmac_reg_read_32
#define HALMAC_REG_WRITE_8 halmac_api->halmac_reg_write_8
#define HALMAC_REG_WRITE_16 halmac_api->halmac_reg_write_16
#define HALMAC_REG_WRITE_32 halmac_api->halmac_reg_write_32
#define HALMAC_REG_SDIO_CMD53_READ_N halmac_api->halmac_reg_sdio_cmd53_read_n
/* Swap Little-endian <-> Big-endia*/
/*1->Little endian 0->Big endian*/
#if HALMAC_SYSTEM_ENDIAN
#else
#endif
#define HALMAC_ALIGN(x, a) HALMAC_ALIGN_MASK(x, (a) - 1)
#define HALMAC_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
/* HALMAC API return status*/
enum halmac_ret_status {
HALMAC_RET_SUCCESS = 0x00,
HALMAC_RET_SUCCESS_ENQUEUE = 0x01,
HALMAC_RET_PLATFORM_API_NULL = 0x02,
HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03,
HALMAC_RET_MALLOC_FAIL = 0x04,
HALMAC_RET_ADAPTER_INVALID = 0x05,
HALMAC_RET_ITF_INCORRECT = 0x06,
HALMAC_RET_DLFW_FAIL = 0x07,
HALMAC_RET_PORT_NOT_SUPPORT = 0x08,
HALMAC_RET_TRXMODE_NOT_SUPPORT = 0x09,
HALMAC_RET_INIT_LLT_FAIL = 0x0A,
HALMAC_RET_POWER_STATE_INVALID = 0x0B,
HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C,
HALMAC_RET_DL_RSVD_PAGE_FAIL = 0x0D,
HALMAC_RET_EFUSE_R_FAIL = 0x0E,
HALMAC_RET_EFUSE_W_FAIL = 0x0F,
HALMAC_RET_H2C_SW_RES_FAIL = 0x10,
HALMAC_RET_SEND_H2C_FAIL = 0x11,
HALMAC_RET_PARA_NOT_SUPPORT = 0x12,
HALMAC_RET_PLATFORM_API_INCORRECT = 0x13,
HALMAC_RET_ENDIAN_ERR = 0x14,
HALMAC_RET_FW_SIZE_ERR = 0x15,
HALMAC_RET_TRX_MODE_NOT_SUPPORT = 0x16,
HALMAC_RET_FAIL = 0x17,
HALMAC_RET_CHANGE_PS_FAIL = 0x18,
HALMAC_RET_CFG_PARA_FAIL = 0x19,
HALMAC_RET_UPDATE_PROBE_FAIL = 0x1A,
HALMAC_RET_SCAN_FAIL = 0x1B,
HALMAC_RET_STOP_SCAN_FAIL = 0x1C,
HALMAC_RET_BCN_PARSER_CMD_FAIL = 0x1D,
HALMAC_RET_POWER_ON_FAIL = 0x1E,
HALMAC_RET_POWER_OFF_FAIL = 0x1F,
HALMAC_RET_RX_AGG_MODE_FAIL = 0x20,
HALMAC_RET_DATA_BUF_NULL = 0x21,
HALMAC_RET_DATA_SIZE_INCORRECT = 0x22,
HALMAC_RET_QSEL_INCORRECT = 0x23,
HALMAC_RET_DMA_MAP_INCORRECT = 0x24,
HALMAC_RET_SEND_ORIGINAL_H2C_FAIL = 0x25,
HALMAC_RET_DDMA_FAIL = 0x26,
HALMAC_RET_FW_CHECKSUM_FAIL = 0x27,
HALMAC_RET_PWRSEQ_POLLING_FAIL = 0x28,
HALMAC_RET_PWRSEQ_CMD_INCORRECT = 0x29,
HALMAC_RET_WRITE_DATA_FAIL = 0x2A,
HALMAC_RET_DUMP_FIFOSIZE_INCORRECT = 0x2B,
HALMAC_RET_NULL_POINTER = 0x2C,
HALMAC_RET_PROBE_NOT_FOUND = 0x2D,
HALMAC_RET_FW_NO_MEMORY = 0x2E,
HALMAC_RET_H2C_STATUS_ERR = 0x2F,
HALMAC_RET_GET_H2C_SPACE_ERR = 0x30,
HALMAC_RET_H2C_SPACE_FULL = 0x31,
HALMAC_RET_DATAPACK_NO_FOUND = 0x32,
HALMAC_RET_CANNOT_FIND_H2C_RESOURCE = 0x33,
HALMAC_RET_TX_DMA_ERR = 0x34,
HALMAC_RET_RX_DMA_ERR = 0x35,
HALMAC_RET_CHIP_NOT_SUPPORT = 0x36,
HALMAC_RET_FREE_SPACE_NOT_ENOUGH = 0x37,
HALMAC_RET_CH_SW_SEQ_WRONG = 0x38,
HALMAC_RET_CH_SW_NO_BUF = 0x39,
HALMAC_RET_SW_CASE_NOT_SUPPORT = 0x3A,
HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL = 0x3B,
HALMAC_RET_INVALID_SOUNDING_SETTING = 0x3C,
HALMAC_RET_GEN_INFO_NOT_SENT = 0x3D,
HALMAC_RET_STATE_INCORRECT = 0x3E,
HALMAC_RET_H2C_BUSY = 0x3F,
HALMAC_RET_INVALID_FEATURE_ID = 0x40,
HALMAC_RET_BUFFER_TOO_SMALL = 0x41,
HALMAC_RET_ZERO_LEN_RSVD_PACKET = 0x42,
HALMAC_RET_BUSY_STATE = 0x43,
HALMAC_RET_ERROR_STATE = 0x44,
HALMAC_RET_API_INVALID = 0x45,
HALMAC_RET_POLLING_BCN_VALID_FAIL = 0x46,
HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL = 0x47,
HALMAC_RET_EEPROM_PARSING_FAIL = 0x48,
HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49,
HALMAC_RET_WRONG_ARGUMENT = 0x4A,
HALMAC_RET_NOT_SUPPORT = 0x4B,
HALMAC_RET_C2H_NOT_HANDLED = 0x4C,
HALMAC_RET_PARA_SENDING = 0x4D,
HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E,
HALMAC_RET_CFG_TXFIFO_PAGE_FAIL = 0x4F,
HALMAC_RET_SWITCH_CASE_ERROR = 0x50,
HALMAC_RET_EFUSE_BANK_INCORRECT = 0x51,
HALMAC_RET_SWITCH_EFUSE_BANK_FAIL = 0x52,
HALMAC_RET_USB_MODE_UNCHANGE = 0x53,
HALMAC_RET_NO_DLFW = 0x54,
HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55,
HALMAC_RET_BIP_NO_SUPPORT = 0x56,
HALMAC_RET_ENTRY_INDEX_ERROR = 0x57,
HALMAC_RET_ENTRY_KEY_ID_ERROR = 0x58,
HALMAC_RET_DRV_DL_ERR = 0x59,
HALMAC_RET_OQT_NOT_ENOUGH = 0x5A,
HALMAC_RET_PWR_UNCHANGE = 0x5B,
HALMAC_RET_FW_NO_SUPPORT = 0x60,
HALMAC_RET_TXFIFO_NO_EMPTY = 0x61,
};
enum halmac_mac_clock_hw_def {
HALMAC_MAC_CLOCK_HW_DEF_80M = 0,
HALMAC_MAC_CLOCK_HW_DEF_40M = 1,
HALMAC_MAC_CLOCK_HW_DEF_20M = 2,
};
/* Rx aggregation parameters */
enum halmac_normal_rxagg_th_to {
HALMAC_NORMAL_RXAGG_THRESHOLD = 0xFF,
HALMAC_NORMAL_RXAGG_TIMEOUT = 0x01,
};
enum halmac_loopback_rxagg_th_to {
HALMAC_LOOPBACK_RXAGG_THRESHOLD = 0xFF,
HALMAC_LOOPBACK_RXAGG_TIMEOUT = 0x01,
};
/* Chip ID*/
enum halmac_chip_id {
HALMAC_CHIP_ID_8822B = 0,
HALMAC_CHIP_ID_8821C = 1,
HALMAC_CHIP_ID_8814B = 2,
HALMAC_CHIP_ID_8197F = 3,
HALMAC_CHIP_ID_UNDEFINE = 0x7F,
};
enum halmac_chip_id_hw_def {
HALMAC_CHIP_ID_HW_DEF_8723A = 0x01,
HALMAC_CHIP_ID_HW_DEF_8188E = 0x02,
HALMAC_CHIP_ID_HW_DEF_8881A = 0x03,
HALMAC_CHIP_ID_HW_DEF_8812A = 0x04,
HALMAC_CHIP_ID_HW_DEF_8821A = 0x05,
HALMAC_CHIP_ID_HW_DEF_8723B = 0x06,
HALMAC_CHIP_ID_HW_DEF_8192E = 0x07,
HALMAC_CHIP_ID_HW_DEF_8814A = 0x08,
HALMAC_CHIP_ID_HW_DEF_8821C = 0x09,
HALMAC_CHIP_ID_HW_DEF_8822B = 0x0A,
HALMAC_CHIP_ID_HW_DEF_8703B = 0x0B,
HALMAC_CHIP_ID_HW_DEF_8188F = 0x0C,
HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D,
HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E,
HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F,
HALMAC_CHIP_ID_HW_DEF_8814B = 0x10,
HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
HALMAC_CHIP_ID_HW_DEF_PS = 0xEA,
};
/* Chip Version*/
enum halmac_chip_ver {
HALMAC_CHIP_VER_A_CUT = 0x00,
HALMAC_CHIP_VER_B_CUT = 0x01,
HALMAC_CHIP_VER_C_CUT = 0x02,
HALMAC_CHIP_VER_D_CUT = 0x03,
HALMAC_CHIP_VER_E_CUT = 0x04,
HALMAC_CHIP_VER_F_CUT = 0x05,
HALMAC_CHIP_VER_TEST = 0xFF,
HALMAC_CHIP_VER_UNDEFINE = 0x7FFF,
};
/* Network type select */
enum halmac_network_type_select {
HALMAC_NETWORK_NO_LINK = 0,
HALMAC_NETWORK_ADHOC = 1,
HALMAC_NETWORK_INFRASTRUCTURE = 2,
HALMAC_NETWORK_AP = 3,
HALMAC_NETWORK_UNDEFINE = 0x7F,
};
/* Transfer mode select */
enum halmac_trnsfer_mode_select {
HALMAC_TRNSFER_NORMAL = 0x0,
HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB,
HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3,
HALMAC_TRNSFER_UNDEFINE = 0x7F,
};
/* Queue select */
enum halmac_dma_mapping {
HALMAC_DMA_MAPPING_EXTRA = 0,
HALMAC_DMA_MAPPING_LOW = 1,
HALMAC_DMA_MAPPING_NORMAL = 2,
HALMAC_DMA_MAPPING_HIGH = 3,
HALMAC_DMA_MAPPING_UNDEFINE = 0x7F,
};
#define HALMAC_MAP2_HQ HALMAC_DMA_MAPPING_HIGH
#define HALMAC_MAP2_NQ HALMAC_DMA_MAPPING_NORMAL
#define HALMAC_MAP2_LQ HALMAC_DMA_MAPPING_LOW
#define HALMAC_MAP2_EXQ HALMAC_DMA_MAPPING_EXTRA
#define HALMAC_MAP2_UNDEF HALMAC_DMA_MAPPING_UNDEFINE
/* TXDESC queue select TID */
enum halmac_txdesc_queue_tid {
HALMAC_TXDESC_QSEL_TID0 = 0,
HALMAC_TXDESC_QSEL_TID1 = 1,
HALMAC_TXDESC_QSEL_TID2 = 2,
HALMAC_TXDESC_QSEL_TID3 = 3,
HALMAC_TXDESC_QSEL_TID4 = 4,
HALMAC_TXDESC_QSEL_TID5 = 5,
HALMAC_TXDESC_QSEL_TID6 = 6,
HALMAC_TXDESC_QSEL_TID7 = 7,
HALMAC_TXDESC_QSEL_TID8 = 8,
HALMAC_TXDESC_QSEL_TID9 = 9,
HALMAC_TXDESC_QSEL_TIDA = 10,
HALMAC_TXDESC_QSEL_TIDB = 11,
HALMAC_TXDESC_QSEL_TIDC = 12,
HALMAC_TXDESC_QSEL_TIDD = 13,
HALMAC_TXDESC_QSEL_TIDE = 14,
HALMAC_TXDESC_QSEL_TIDF = 15,
HALMAC_TXDESC_QSEL_BEACON = 0x10,
HALMAC_TXDESC_QSEL_HIGH = 0x11,
HALMAC_TXDESC_QSEL_MGT = 0x12,
HALMAC_TXDESC_QSEL_H2C_CMD = 0x13,
HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F,
};
enum halmac_ptcl_queue {
HALMAC_PTCL_QUEUE_VO = 0x0,
HALMAC_PTCL_QUEUE_VI = 0x1,
HALMAC_PTCL_QUEUE_BE = 0x2,
HALMAC_PTCL_QUEUE_BK = 0x3,
HALMAC_PTCL_QUEUE_MG = 0x4,
HALMAC_PTCL_QUEUE_HI = 0x5,
HALMAC_PTCL_QUEUE_NUM = 0x6,
HALMAC_PTCL_QUEUE_UNDEFINE = 0x7F,
};
enum halmac_queue_select {
HALMAC_QUEUE_SELECT_VO = HALMAC_TXDESC_QSEL_TID6,
HALMAC_QUEUE_SELECT_VI = HALMAC_TXDESC_QSEL_TID4,
HALMAC_QUEUE_SELECT_BE = HALMAC_TXDESC_QSEL_TID0,
HALMAC_QUEUE_SELECT_BK = HALMAC_TXDESC_QSEL_TID1,
HALMAC_QUEUE_SELECT_VO_V2 = HALMAC_TXDESC_QSEL_TID7,
HALMAC_QUEUE_SELECT_VI_V2 = HALMAC_TXDESC_QSEL_TID5,
HALMAC_QUEUE_SELECT_BE_V2 = HALMAC_TXDESC_QSEL_TID3,
HALMAC_QUEUE_SELECT_BK_V2 = HALMAC_TXDESC_QSEL_TID2,
HALMAC_QUEUE_SELECT_BCN = HALMAC_TXDESC_QSEL_BEACON,
HALMAC_QUEUE_SELECT_HIGH = HALMAC_TXDESC_QSEL_HIGH,
HALMAC_QUEUE_SELECT_MGNT = HALMAC_TXDESC_QSEL_MGT,
HALMAC_QUEUE_SELECT_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,
HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F,
};
/* USB burst size */
enum halmac_usb_burst_size {
HALMAC_USB_BURST_SIZE_3_0 = 0x0,
HALMAC_USB_BURST_SIZE_2_0_HSPEED = 0x1,
HALMAC_USB_BURST_SIZE_2_0_FSPEED = 0x2,
HALMAC_USB_BURST_SIZE_2_0_OTHERS = 0x3,
HALMAC_USB_BURST_SIZE_UNDEFINE = 0x7F,
};
/* HAL API function parameters*/
enum halmac_interface {
HALMAC_INTERFACE_PCIE = 0x0,
HALMAC_INTERFACE_USB = 0x1,
HALMAC_INTERFACE_SDIO = 0x2,
HALMAC_INTERFACE_AXI = 0x3,
HALMAC_INTERFACE_UNDEFINE = 0x7F,
};
enum halmac_rx_agg_mode {
HALMAC_RX_AGG_MODE_NONE = 0x0,
HALMAC_RX_AGG_MODE_DMA = 0x1,
HALMAC_RX_AGG_MODE_USB = 0x2,
HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F,
};
struct halmac_rxagg_th {
u8 drv_define;
u8 timeout;
u8 size;
};
struct halmac_rxagg_cfg {
enum halmac_rx_agg_mode mode;
struct halmac_rxagg_th threshold;
};
enum halmac_mac_power {
HALMAC_MAC_POWER_OFF = 0x0,
HALMAC_MAC_POWER_ON = 0x1,
HALMAC_MAC_POWER_UNDEFINE = 0x7F,
};
enum halmac_ps_state {
HALMAC_PS_STATE_ACT = 0x0,
HALMAC_PS_STATE_LPS = 0x1,
HALMAC_PS_STATE_IPS = 0x2,
HALMAC_PS_STATE_UNDEFINE = 0x7F,
};
enum halmac_trx_mode {
HALMAC_TRX_MODE_NORMAL = 0x0,
HALMAC_TRX_MODE_TRXSHARE = 0x1,
HALMAC_TRX_MODE_WMM = 0x2,
HALMAC_TRX_MODE_P2P = 0x3,
HALMAC_TRX_MODE_LOOPBACK = 0x4,
HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5,
HALMAC_TRX_MODE_MAX = 0x6,
HALMAC_TRX_MODE_WMM_LINUX = 0x7E,
HALMAC_TRX_MODE_UNDEFINE = 0x7F,
};
enum halmac_wireless_mode {
HALMAC_WIRELESS_MODE_B = 0x0,
HALMAC_WIRELESS_MODE_G = 0x1,
HALMAC_WIRELESS_MODE_N = 0x2,
HALMAC_WIRELESS_MODE_AC = 0x3,
HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F,
};
enum halmac_bw {
HALMAC_BW_20 = 0x00,
HALMAC_BW_40 = 0x01,
HALMAC_BW_80 = 0x02,
HALMAC_BW_160 = 0x03,
HALMAC_BW_5 = 0x04,
HALMAC_BW_10 = 0x05,
HALMAC_BW_MAX = 0x06,
HALMAC_BW_UNDEFINE = 0x7F,
};
enum halmac_efuse_read_cfg {
HALMAC_EFUSE_R_AUTO = 0x00,
HALMAC_EFUSE_R_DRV = 0x01,
HALMAC_EFUSE_R_FW = 0x02,
HALMAC_EFUSE_R_UNDEFINE = 0x7F,
};
enum halmac_dlfw_mem {
HALMAC_DLFW_MEM_EMEM = 0x00,
HALMAC_DLFW_MEM_UNDEFINE = 0x7F,
};
struct halmac_tx_desc {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
u32 dword6;
u32 dword7;
u32 dword8;
u32 dword9;
u32 dword10;
u32 dword11;
};
struct halmac_rx_desc {
u32 dword0;
u32 dword1;
u32 dword2;
u32 dword3;
u32 dword4;
u32 dword5;
};
struct halmac_fwlps_option {
u8 mode;
u8 clk_request;
u8 rlbm;
u8 smart_ps;
u8 awake_interval;
u8 all_queue_uapsd;
u8 pwr_state;
u8 low_pwr_rx_beacon;
u8 ant_auto_switch;
u8 ps_allow_bt_high_priority;
u8 protect_bcn;
u8 silence_period;
u8 fast_bt_connect;
u8 two_antenna_en;
u8 adopt_user_setting;
u8 drv_bcn_early_shift;
bool enter_32K;
};
struct halmac_fwips_option {
u8 adopt_user_setting;
};
struct halmac_wowlan_option {
u8 adopt_user_setting;
};
struct halmac_bcn_ie_info {
u8 func_en;
u8 size_th;
u8 timeout;
u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE];
};
enum halmac_reg_type {
HALMAC_REG_TYPE_MAC = 0x0,
HALMAC_REG_TYPE_BB = 0x1,
HALMAC_REG_TYPE_RF = 0x2,
HALMAC_REG_TYPE_UNDEFINE = 0x7F,
};
enum halmac_parameter_cmd {
/* HALMAC_PARAMETER_CMD_LLT = 0x1, */
/* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */
/* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */
HALMAC_PARAMETER_CMD_MAC_W8 = 0x4,
HALMAC_PARAMETER_CMD_MAC_W16 = 0x5,
HALMAC_PARAMETER_CMD_MAC_W32 = 0x6,
HALMAC_PARAMETER_CMD_RF_W = 0x7,
HALMAC_PARAMETER_CMD_BB_W8 = 0x8,
HALMAC_PARAMETER_CMD_BB_W16 = 0x9,
HALMAC_PARAMETER_CMD_BB_W32 = 0XA,
HALMAC_PARAMETER_CMD_DELAY_US = 0X10,
HALMAC_PARAMETER_CMD_DELAY_MS = 0X11,
HALMAC_PARAMETER_CMD_END = 0XFF,
};
union halmac_parameter_content {
struct _MAC_REG_W {
u32 value;
u32 msk;
u16 offset;
u8 msk_en;
} MAC_REG_W;
struct _BB_REG_W {
u32 value;
u32 msk;
u16 offset;
u8 msk_en;
} BB_REG_W;
struct _RF_REG_W {
u32 value;
u32 msk;
u8 offset;
u8 msk_en;
u8 rf_path;
} RF_REG_W;
struct _DELAY_TIME {
u32 rsvd1;
u32 rsvd2;
u16 delay_time;
u8 rsvd3;
} DELAY_TIME;
};
struct halmac_phy_parameter_info {
enum halmac_parameter_cmd cmd_id;
union halmac_parameter_content content;
};
struct halmac_h2c_info {
u16 h2c_seq_num; /* H2C sequence number */
u8 in_use; /* 0 : empty 1 : used */
enum halmac_h2c_return_code status;
};
struct halmac_pg_efuse_info {
u8 *efuse_map;
u32 efuse_map_size;
u8 *efuse_mask;
u32 efuse_mask_size;
};
struct halmac_txagg_buff_info {
u8 *tx_agg_buf;
u8 *curr_pkt_buf;
u32 avai_buf_size;
u32 total_pkt_size;
u8 agg_num;
};
struct halmac_config_para_info {
u32 para_buf_size; /* Parameter buffer size */
u8 *cfg_para_buf; /* Buffer for config parameter */
u8 *para_buf_w; /* Write pointer of the parameter buffer */
u32 para_num; /* Parameter numbers in parameter buffer */
u32 avai_para_buf_size; /* Free size of parameter buffer */
u32 offset_accumulation;
u32 value_accumulation;
enum halmac_data_type data_type; /*DataType which is passed to FW*/
u8 datapack_segment; /*DataPack Segment, from segment0...*/
bool full_fifo_mode; /* Used full tx fifo to save cfg parameter */
};
struct halmac_hw_config_info {
u32 efuse_size; /* Record efuse size */
u32 eeprom_size; /* Record eeprom size */
u32 bt_efuse_size; /* Record BT efuse size */
u32 tx_fifo_size; /* Record tx fifo size */
u32 rx_fifo_size; /* Record rx fifo size */
u8 txdesc_size; /* Record tx desc size */
u8 rxdesc_size; /* Record rx desc size */
u32 page_size; /* Record page size */
u16 tx_align_size;
u8 page_size_2_power;
u8 cam_entry_num; /* Record CAM entry number */
};
struct halmac_sdio_free_space {
u16 high_queue_number; /* Free space of HIQ */
u16 normal_queue_number; /* Free space of MIDQ */
u16 low_queue_number; /* Free space of LOWQ */
u16 public_queue_number; /* Free space of PUBQ */
u16 extra_queue_number; /* Free space of EXBQ */
u8 ac_oqt_number;
u8 non_ac_oqt_number;
u8 ac_empty;
};
enum hal_fifo_sel {
HAL_FIFO_SEL_TX,
HAL_FIFO_SEL_RX,
HAL_FIFO_SEL_RSVD_PAGE,
HAL_FIFO_SEL_REPORT,
HAL_FIFO_SEL_LLT,
};
enum halmac_drv_info {
HALMAC_DRV_INFO_NONE, /* No information is appended in rx_pkt */
HALMAC_DRV_INFO_PHY_STATUS, /* PHY status is appended after rx_desc */
HALMAC_DRV_INFO_PHY_SNIFFER, /* PHY status and sniffer info appended */
HALMAC_DRV_INFO_PHY_PLCP, /* PHY status and plcp header are appended */
HALMAC_DRV_INFO_UNDEFINE,
};
struct halmac_bt_coex_cmd {
u8 element_id;
u8 op_code;
u8 op_code_ver;
u8 req_num;
u8 data0;
u8 data1;
u8 data2;
u8 data3;
u8 data4;
};
enum halmac_pri_ch_idx {
HALMAC_CH_IDX_UNDEFINE = 0,
HALMAC_CH_IDX_1 = 1,
HALMAC_CH_IDX_2 = 2,
HALMAC_CH_IDX_3 = 3,
HALMAC_CH_IDX_4 = 4,
HALMAC_CH_IDX_MAX = 5,
};
struct halmac_ch_info {
enum halmac_cs_action_id action_id;
enum halmac_bw bw;
enum halmac_pri_ch_idx pri_ch_idx;
u8 channel;
u8 timeout;
u8 extra_info;
};
struct halmac_ch_extra_info {
u8 extra_info;
enum halmac_cs_extra_action_id extra_action_id;
u8 extra_info_size;
u8 *extra_info_data;
};
enum halmac_cs_periodic_option {
HALMAC_CS_PERIODIC_NONE,
HALMAC_CS_PERIODIC_NORMAL,
HALMAC_CS_PERIODIC_2_PHASE,
HALMAC_CS_PERIODIC_SEAMLESS,
};
struct halmac_ch_switch_option {
enum halmac_bw dest_bw;
enum halmac_cs_periodic_option periodic_option;
enum halmac_pri_ch_idx dest_pri_ch_idx;
/* u32 tsf_high; */
u32 tsf_low;
bool switch_en;
u8 dest_ch_en;
u8 absolute_time_en;
u8 dest_ch;
u8 normal_period;
u8 normal_cycle;
u8 phase_2_period;
};
struct halmac_fw_version {
u16 version;
u8 sub_version;
u8 sub_index;
u16 h2c_version;
};
enum halmac_rf_type {
HALMAC_RF_1T2R = 0,
HALMAC_RF_2T4R = 1,
HALMAC_RF_2T2R = 2,
HALMAC_RF_2T3R = 3,
HALMAC_RF_1T1R = 4,
HALMAC_RF_2T2R_GREEN = 5,
HALMAC_RF_3T3R = 6,
HALMAC_RF_3T4R = 7,
HALMAC_RF_4T4R = 8,
HALMAC_RF_MAX_TYPE = 0xF,
};
struct halmac_general_info {
u8 rfe_type;
enum halmac_rf_type rf_type;
};
struct halmac_pwr_tracking_para {
u8 enable;
u8 tx_pwr_index;
u8 pwr_tracking_offset_value;
u8 tssi_value;
};
struct halmac_pwr_tracking_option {
u8 type;
u8 bbswing_index;
struct halmac_pwr_tracking_para
pwr_tracking_para[4]; /* pathA, pathB, pathC, pathD */
};
struct halmac_nlo_cfg {
u8 num_of_ssid;
u8 num_of_hidden_ap;
u8 rsvd[2];
u32 pattern_check;
u32 rsvd1;
u32 rsvd2;
u8 ssid_len[HALMAC_SUPPORT_NLO_NUM];
u8 chiper_type[HALMAC_SUPPORT_NLO_NUM];
u8 rsvd3[HALMAC_SUPPORT_NLO_NUM];
u8 loc_probe_req[HALMAC_SUPPORT_PROBE_REQ_NUM];
u8 rsvd4[56];
u8 ssid[HALMAC_SUPPORT_NLO_NUM][HALMAC_MAX_SSID_LEN];
};
enum halmac_data_rate {
HALMAC_CCK1,
HALMAC_CCK2,
HALMAC_CCK5_5,
HALMAC_CCK11,
HALMAC_OFDM6,
HALMAC_OFDM9,
HALMAC_OFDM12,
HALMAC_OFDM18,
HALMAC_OFDM24,
HALMAC_OFDM36,
HALMAC_OFDM48,
HALMAC_OFDM54,
HALMAC_MCS0,
HALMAC_MCS1,
HALMAC_MCS2,
HALMAC_MCS3,
HALMAC_MCS4,
HALMAC_MCS5,
HALMAC_MCS6,
HALMAC_MCS7,
HALMAC_MCS8,
HALMAC_MCS9,
HALMAC_MCS10,
HALMAC_MCS11,
HALMAC_MCS12,
HALMAC_MCS13,
HALMAC_MCS14,
HALMAC_MCS15,
HALMAC_MCS16,
HALMAC_MCS17,
HALMAC_MCS18,
HALMAC_MCS19,
HALMAC_MCS20,
HALMAC_MCS21,
HALMAC_MCS22,
HALMAC_MCS23,
HALMAC_MCS24,
HALMAC_MCS25,
HALMAC_MCS26,
HALMAC_MCS27,
HALMAC_MCS28,
HALMAC_MCS29,
HALMAC_MCS30,
HALMAC_MCS31,
HALMAC_VHT_NSS1_MCS0,
HALMAC_VHT_NSS1_MCS1,
HALMAC_VHT_NSS1_MCS2,
HALMAC_VHT_NSS1_MCS3,
HALMAC_VHT_NSS1_MCS4,
HALMAC_VHT_NSS1_MCS5,
HALMAC_VHT_NSS1_MCS6,
HALMAC_VHT_NSS1_MCS7,
HALMAC_VHT_NSS1_MCS8,
HALMAC_VHT_NSS1_MCS9,
HALMAC_VHT_NSS2_MCS0,
HALMAC_VHT_NSS2_MCS1,
HALMAC_VHT_NSS2_MCS2,
HALMAC_VHT_NSS2_MCS3,
HALMAC_VHT_NSS2_MCS4,
HALMAC_VHT_NSS2_MCS5,
HALMAC_VHT_NSS2_MCS6,
HALMAC_VHT_NSS2_MCS7,
HALMAC_VHT_NSS2_MCS8,
HALMAC_VHT_NSS2_MCS9,
HALMAC_VHT_NSS3_MCS0,
HALMAC_VHT_NSS3_MCS1,
HALMAC_VHT_NSS3_MCS2,
HALMAC_VHT_NSS3_MCS3,
HALMAC_VHT_NSS3_MCS4,
HALMAC_VHT_NSS3_MCS5,
HALMAC_VHT_NSS3_MCS6,
HALMAC_VHT_NSS3_MCS7,
HALMAC_VHT_NSS3_MCS8,
HALMAC_VHT_NSS3_MCS9,
HALMAC_VHT_NSS4_MCS0,
HALMAC_VHT_NSS4_MCS1,
HALMAC_VHT_NSS4_MCS2,
HALMAC_VHT_NSS4_MCS3,
HALMAC_VHT_NSS4_MCS4,
HALMAC_VHT_NSS4_MCS5,
HALMAC_VHT_NSS4_MCS6,
HALMAC_VHT_NSS4_MCS7,
HALMAC_VHT_NSS4_MCS8,
HALMAC_VHT_NSS4_MCS9
};
enum halmac_rf_path {
HALMAC_RF_PATH_A,
HALMAC_RF_PATH_B,
HALMAC_RF_PATH_C,
HALMAC_RF_PATH_D
};
enum halmac_snd_pkt_sel {
HALMAC_UNI_NDPA,
HALMAC_BMC_NDPA,
HALMAC_NON_FINAL_BFRPRPOLL,
HALMAC_FINAL_BFRPTPOLL,
};
enum hal_security_type {
HAL_SECURITY_TYPE_NONE = 0,
HAL_SECURITY_TYPE_WEP40 = 1,
HAL_SECURITY_TYPE_WEP104 = 2,
HAL_SECURITY_TYPE_TKIP = 3,
HAL_SECURITY_TYPE_AES128 = 4,
HAL_SECURITY_TYPE_WAPI = 5,
HAL_SECURITY_TYPE_AES256 = 6,
HAL_SECURITY_TYPE_GCMP128 = 7,
HAL_SECURITY_TYPE_GCMP256 = 8,
HAL_SECURITY_TYPE_GCMSMS4 = 9,
HAL_SECURITY_TYPE_BIP = 10,
HAL_SECURITY_TYPE_UNDEFINE = 0x7F,
};
enum hal_intf_phy {
HAL_INTF_PHY_USB2 = 0,
HAL_INTF_PHY_USB3 = 1,
HAL_INTF_PHY_PCIE_GEN1 = 2,
HAL_INTF_PHY_PCIE_GEN2 = 3,
HAL_INTF_PHY_UNDEFINE = 0x7F,
};
enum halmac_dbg_msg_info {
HALMAC_DBG_ERR,
HALMAC_DBG_WARN,
HALMAC_DBG_TRACE,
};
enum halmac_dbg_msg_type {
HALMAC_MSG_INIT,
HALMAC_MSG_EFUSE,
HALMAC_MSG_FW,
HALMAC_MSG_H2C,
HALMAC_MSG_PWR,
HALMAC_MSG_SND,
HALMAC_MSG_COMMON,
HALMAC_MSG_DBI,
HALMAC_MSG_MDIO,
HALMAC_MSG_USB
};
enum halmac_cmd_process_status {
HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */
HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */
HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */
HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */
HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */
HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
};
enum halmac_feature_id {
HALMAC_FEATURE_CFG_PARA, /* Support */
HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, /* Support */
HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, /* Support */
HALMAC_FEATURE_UPDATE_PACKET, /* Support */
HALMAC_FEATURE_UPDATE_DATAPACK,
HALMAC_FEATURE_RUN_DATAPACK,
HALMAC_FEATURE_CHANNEL_SWITCH, /* Support */
HALMAC_FEATURE_IQK, /* Support */
HALMAC_FEATURE_POWER_TRACKING, /* Support */
HALMAC_FEATURE_PSD, /* Support */
HALMAC_FEATURE_ALL, /* Support, only for reset */
};
enum halmac_drv_rsvd_pg_num {
HALMAC_RSVD_PG_NUM16, /* 2K */
HALMAC_RSVD_PG_NUM24, /* 3K */
HALMAC_RSVD_PG_NUM32, /* 4K */
};
enum halmac_pcie_cfg {
HALMAC_PCIE_GEN1,
HALMAC_PCIE_GEN2,
HALMAC_PCIE_CFG_UNDEFINE,
};
enum halmac_portid {
HALMAC_PORTID0 = 0,
HALMAC_PORTID1 = 1,
HALMAC_PORTID2 = 2,
HALMAC_PORTID3 = 3,
HALMAC_PORTID4 = 4,
HALMAC_PORTIDMAX
};
struct halmac_p2pps {
/*DW0*/
u8 offload_en : 1;
u8 role : 1;
u8 ctwindow_en : 1;
u8 noa_en : 1;
u8 noa_sel : 1;
u8 all_sta_sleep : 1;
u8 discovery : 1;
u8 rsvd2 : 1;
u8 p2p_port_id;
u8 p2p_group;
u8 p2p_macid;
/*DW1*/
u8 ctwindow_length;
u8 rsvd3;
u8 rsvd4;
u8 rsvd5;
/*DW2*/
u32 noa_duration_para;
/*DW3*/
u32 noa_interval_para;
/*DW4*/
u32 noa_start_time_para;
/*DW5*/
u32 noa_count_para;
};
/* Platform API setting */
struct halmac_platform_api {
/* R/W register */
u8 (*SDIO_CMD52_READ)(void *driver_adapter, u32 offset);
u8 (*SDIO_CMD53_READ_8)(void *driver_adapter, u32 offset);
u16 (*SDIO_CMD53_READ_16)(void *driver_adapter, u32 offset);
u32 (*SDIO_CMD53_READ_32)(void *driver_adapter, u32 offset);
u8 (*SDIO_CMD53_READ_N)(void *driver_adapter, u32 offset, u32 size,
u8 *data);
void (*SDIO_CMD52_WRITE)(void *driver_adapter, u32 offset, u8 value);
void (*SDIO_CMD53_WRITE_8)(void *driver_adapter, u32 offset, u8 value);
void (*SDIO_CMD53_WRITE_16)(void *driver_adapter, u32 offset,
u16 value);
void (*SDIO_CMD53_WRITE_32)(void *driver_adapter, u32 offset,
u32 value);
u8 (*REG_READ_8)(void *driver_adapter, u32 offset);
u16 (*REG_READ_16)(void *driver_adapter, u32 offset);
u32 (*REG_READ_32)(void *driver_adapter, u32 offset);
void (*REG_WRITE_8)(void *driver_adapter, u32 offset, u8 value);
void (*REG_WRITE_16)(void *driver_adapter, u32 offset, u16 value);
void (*REG_WRITE_32)(void *driver_adapter, u32 offset, u32 value);
/* send buf to reserved page, the tx_desc is not included in buf,
* driver need to fill tx_desc with qsel = bcn
*/
bool (*SEND_RSVD_PAGE)(void *driver_adapter, u8 *buf, u32 size);
/* send buf to h2c queue, the tx_desc is not included in buf,
* driver need to fill tx_desc with qsel = h2c
*/
bool (*SEND_H2C_PKT)(void *driver_adapter, u8 *buf, u32 size);
bool (*EVENT_INDICATION)(void *driver_adapter,
enum halmac_feature_id feature_id,
enum halmac_cmd_process_status process_status,
u8 *buf, u32 size);
};
/*1->Little endian 0->Big endian*/
#if HALMAC_SYSTEM_ENDIAN
#else
#endif
/* User can not use members in address_l_h, use address[6] is mandatory */
union halmac_wlan_addr {
u8 address[6]; /* WLAN address (MACID, BSSID, Brodcast ID).
* address[0] is lowest, address[5] is highest
*/
struct {
union {
u32 address_low;
__le32 le_address_low;
u8 address_low_b[4];
};
union {
u16 address_high;
__le16 le_address_high;
u8 address_high_b[2];
};
} address_l_h;
};
enum halmac_snd_role {
HAL_BFER = 0,
HAL_BFEE = 1,
};
enum halmac_csi_seg_len {
HAL_CSI_SEG_4K = 0,
HAL_CSI_SEG_8K = 1,
HAL_CSI_SEG_11K = 2,
};
struct halmac_cfg_mumimo_para {
enum halmac_snd_role role;
bool sounding_sts[6];
u16 grouping_bitmap;
bool mu_tx_en;
u32 given_gid_tab[2];
u32 given_user_pos[4];
};
struct halmac_su_bfer_init_para {
u8 userid;
u16 paid;
u16 csi_para;
union halmac_wlan_addr bfer_address;
};
struct halmac_mu_bfee_init_para {
u8 userid;
u16 paid;
u32 user_position_l;
u32 user_position_h;
};
struct halmac_mu_bfer_init_para {
u16 paid;
u16 csi_para;
u16 my_aid;
enum halmac_csi_seg_len csi_length_sel;
union halmac_wlan_addr bfer_address;
};
struct halmac_snd_info {
u16 paid;
u8 userid;
enum halmac_data_rate ndpa_rate;
u16 csi_para;
u16 my_aid;
enum halmac_data_rate csi_rate;
enum halmac_csi_seg_len csi_length_sel;
enum halmac_snd_role role;
union halmac_wlan_addr bfer_address;
enum halmac_bw bw;
u8 txbf_en;
struct halmac_su_bfer_init_para *su_bfer_init;
struct halmac_mu_bfer_init_para *mu_bfer_init;
struct halmac_mu_bfee_init_para *mu_bfee_init;
};
struct halmac_cs_info {
u8 *ch_info_buf;
u8 *ch_info_buf_w;
u8 extra_info_en;
u32 buf_size; /* buffer size */
u32 avai_buf_size; /* buffer size */
u32 total_size;
u32 accu_timeout;
u32 ch_num;
};
struct halmac_restore_info {
u32 mac_register;
u32 value;
u8 length;
};
struct halmac_event_trigger {
u32 physical_efuse_map : 1;
u32 logical_efuse_map : 1;
u32 rsvd1 : 28;
};
struct halmac_h2c_header_info {
u16 sub_cmd_id;
u16 content_size;
bool ack;
};
enum halmac_dlfw_state {
HALMAC_DLFW_NONE = 0,
HALMAC_DLFW_DONE = 1,
HALMAC_GEN_INFO_SENT = 2,
HALMAC_DLFW_UNDEFINED = 0x7F,
};
enum halmac_efuse_cmd_construct_state {
HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0,
HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1,
HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT = 2,
HALMAC_EFUSE_CMD_CONSTRUCT_STATE_NUM = 3,
HALMAC_EFUSE_CMD_CONSTRUCT_UNDEFINED = 0x7F,
};
enum halmac_cfg_para_cmd_construct_state {
HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE = 0,
HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING = 1,
HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT = 2,
HALMAC_CFG_PARA_CMD_CONSTRUCT_NUM = 3,
HALMAC_CFG_PARA_CMD_CONSTRUCT_UNDEFINED = 0x7F,
};
enum halmac_scan_cmd_construct_state {
HALMAC_SCAN_CMD_CONSTRUCT_IDLE = 0,
HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED = 1,
HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING = 2,
HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT = 3,
HALMAC_SCAN_CMD_CONSTRUCT_STATE_NUM = 4,
HALMAC_SCAN_CMD_CONSTRUCT_UNDEFINED = 0x7F,
};
enum halmac_api_state {
HALMAC_API_STATE_INIT = 0,
HALMAC_API_STATE_HALT = 1,
HALMAC_API_STATE_UNDEFINED = 0x7F,
};
struct halmac_efuse_state_set {
enum halmac_efuse_cmd_construct_state efuse_cmd_construct_state;
enum halmac_cmd_process_status process_status;
u8 fw_return_code;
u16 seq_num;
};
struct halmac_cfg_para_state_set {
enum halmac_cfg_para_cmd_construct_state cfg_para_cmd_construct_state;
enum halmac_cmd_process_status process_status;
u8 fw_return_code;
u16 seq_num;
};
struct halmac_scan_state_set {
enum halmac_scan_cmd_construct_state scan_cmd_construct_state;
enum halmac_cmd_process_status process_status;
u8 fw_return_code;
u16 seq_num;
};
struct halmac_update_packet_state_set {
enum halmac_cmd_process_status process_status;
u8 fw_return_code;
u16 seq_num;
};
struct halmac_iqk_state_set {
enum halmac_cmd_process_status process_status;
u8 fw_return_code;
u16 seq_num;
};
struct halmac_power_tracking_state_set {
enum halmac_cmd_process_status process_status;
u8 fw_return_code;
u16 seq_num;
};
struct halmac_psd_state_set {
enum halmac_cmd_process_status process_status;
u16 data_size;
u16 segment_size;
u8 *data;
u8 fw_return_code;
u16 seq_num;
};
struct halmac_state {
struct halmac_efuse_state_set
efuse_state_set; /* State machine + cmd process status */
struct halmac_cfg_para_state_set
cfg_para_state_set; /* State machine + cmd process status */
struct halmac_scan_state_set
scan_state_set; /* State machine + cmd process status */
struct halmac_update_packet_state_set
update_packet_set; /* cmd process status */
struct halmac_iqk_state_set iqk_set; /* cmd process status */
struct halmac_power_tracking_state_set
power_tracking_set; /* cmd process status */
struct halmac_psd_state_set psd_set; /* cmd process status */
enum halmac_api_state api_state; /* Halmac api state */
enum halmac_mac_power mac_power; /* 0 : power off, 1 : power on*/
enum halmac_ps_state ps_state; /* power saving state */
enum halmac_dlfw_state dlfw_state; /* download FW state */
};
struct halmac_ver {
u8 major_ver;
u8 prototype_ver;
u8 minor_ver;
};
enum halmac_api_id {
/*stuff, need to be the 1st*/
HALMAC_API_STUFF = 0x0,
/*stuff, need to be the 1st*/
HALMAC_API_MAC_POWER_SWITCH = 0x1,
HALMAC_API_DOWNLOAD_FIRMWARE = 0x2,
HALMAC_API_CFG_MAC_ADDR = 0x3,
HALMAC_API_CFG_BSSID = 0x4,
HALMAC_API_CFG_MULTICAST_ADDR = 0x5,
HALMAC_API_PRE_INIT_SYSTEM_CFG = 0x6,
HALMAC_API_INIT_SYSTEM_CFG = 0x7,
HALMAC_API_INIT_TRX_CFG = 0x8,
HALMAC_API_CFG_RX_AGGREGATION = 0x9,
HALMAC_API_INIT_PROTOCOL_CFG = 0xA,
HALMAC_API_INIT_EDCA_CFG = 0xB,
HALMAC_API_CFG_OPERATION_MODE = 0xC,
HALMAC_API_CFG_CH_BW = 0xD,
HALMAC_API_CFG_BW = 0xE,
HALMAC_API_INIT_WMAC_CFG = 0xF,
HALMAC_API_INIT_MAC_CFG = 0x10,
HALMAC_API_INIT_SDIO_CFG = 0x11,
HALMAC_API_INIT_USB_CFG = 0x12,
HALMAC_API_INIT_PCIE_CFG = 0x13,
HALMAC_API_INIT_INTERFACE_CFG = 0x14,
HALMAC_API_DEINIT_SDIO_CFG = 0x15,
HALMAC_API_DEINIT_USB_CFG = 0x16,
HALMAC_API_DEINIT_PCIE_CFG = 0x17,
HALMAC_API_DEINIT_INTERFACE_CFG = 0x18,
HALMAC_API_GET_EFUSE_SIZE = 0x19,
HALMAC_API_DUMP_EFUSE_MAP = 0x1A,
HALMAC_API_WRITE_EFUSE = 0x1B,
HALMAC_API_READ_EFUSE = 0x1C,
HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D,
HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E,
HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F,
HALMAC_API_READ_LOGICAL_EFUSE = 0x20,
HALMAC_API_PG_EFUSE_BY_MAP = 0x21,
HALMAC_API_GET_C2H_INFO = 0x22,
HALMAC_API_CFG_FWLPS_OPTION = 0x23,
HALMAC_API_CFG_FWIPS_OPTION = 0x24,
HALMAC_API_ENTER_WOWLAN = 0x25,
HALMAC_API_LEAVE_WOWLAN = 0x26,
HALMAC_API_ENTER_PS = 0x27,
HALMAC_API_LEAVE_PS = 0x28,
HALMAC_API_H2C_LB = 0x29,
HALMAC_API_DEBUG = 0x2A,
HALMAC_API_CFG_PARAMETER = 0x2B,
HALMAC_API_UPDATE_PACKET = 0x2C,
HALMAC_API_BCN_IE_FILTER = 0x2D,
HALMAC_API_REG_READ_8 = 0x2E,
HALMAC_API_REG_WRITE_8 = 0x2F,
HALMAC_API_REG_READ_16 = 0x30,
HALMAC_API_REG_WRITE_16 = 0x31,
HALMAC_API_REG_READ_32 = 0x32,
HALMAC_API_REG_WRITE_32 = 0x33,
HALMAC_API_TX_ALLOWED_SDIO = 0x34,
HALMAC_API_SET_BULKOUT_NUM = 0x35,
HALMAC_API_GET_SDIO_TX_ADDR = 0x36,
HALMAC_API_GET_USB_BULKOUT_ID = 0x37,
HALMAC_API_TIMER_2S = 0x38,
HALMAC_API_FILL_TXDESC_CHECKSUM = 0x39,
HALMAC_API_SEND_ORIGINAL_H2C = 0x3A,
HALMAC_API_UPDATE_DATAPACK = 0x3B,
HALMAC_API_RUN_DATAPACK = 0x3C,
HALMAC_API_CFG_DRV_INFO = 0x3D,
HALMAC_API_SEND_BT_COEX = 0x3E,
HALMAC_API_VERIFY_PLATFORM_API = 0x3F,
HALMAC_API_GET_FIFO_SIZE = 0x40,
HALMAC_API_DUMP_FIFO = 0x41,
HALMAC_API_CFG_TXBF = 0x42,
HALMAC_API_CFG_MUMIMO = 0x43,
HALMAC_API_CFG_SOUNDING = 0x44,
HALMAC_API_DEL_SOUNDING = 0x45,
HALMAC_API_SU_BFER_ENTRY_INIT = 0x46,
HALMAC_API_SU_BFEE_ENTRY_INIT = 0x47,
HALMAC_API_MU_BFER_ENTRY_INIT = 0x48,
HALMAC_API_MU_BFEE_ENTRY_INIT = 0x49,
HALMAC_API_SU_BFER_ENTRY_DEL = 0x4A,
HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B,
HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C,
HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D,
HALMAC_API_ADD_CH_INFO = 0x4E,
HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F,
HALMAC_API_CTRL_CH_SWITCH = 0x50,
HALMAC_API_CLEAR_CH_INFO = 0x51,
HALMAC_API_SEND_GENERAL_INFO = 0x52,
HALMAC_API_START_IQK = 0x53,
HALMAC_API_CTRL_PWR_TRACKING = 0x54,
HALMAC_API_PSD = 0x55,
HALMAC_API_CFG_TX_AGG_ALIGN = 0x56,
HALMAC_API_QUERY_STATE = 0x57,
HALMAC_API_RESET_FEATURE = 0x58,
HALMAC_API_CHECK_FW_STATUS = 0x59,
HALMAC_API_DUMP_FW_DMEM = 0x5A,
HALMAC_API_CFG_MAX_DL_SIZE = 0x5B,
HALMAC_API_INIT_OBJ = 0x5C,
HALMAC_API_DEINIT_OBJ = 0x5D,
HALMAC_API_CFG_LA_MODE = 0x5E,
HALMAC_API_GET_HW_VALUE = 0x5F,
HALMAC_API_SET_HW_VALUE = 0x60,
HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61,
HALMAC_API_SWITCH_EFUSE_BANK = 0x62,
HALMAC_API_WRITE_EFUSE_BT = 0x63,
HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64,
HALMAC_API_DL_DRV_RSVD_PG = 0x65,
HALMAC_API_PCIE_SWITCH = 0x66,
HALMAC_API_PHY_CFG = 0x67,
HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE = 0x68,
HALMAC_API_CFG_CSI_RATE = 0x69,
HALMAC_API_MAX
};
struct halmac_api_record {
enum halmac_api_id api_array[API_ARRAY_SIZE];
u8 array_wptr;
};
enum halmac_la_mode {
HALMAC_LA_MODE_DISABLE = 0,
HALMAC_LA_MODE_PARTIAL = 1,
HALMAC_LA_MODE_FULL = 2,
HALMAC_LA_MODE_UNDEFINE = 0x7F,
};
enum halmac_rx_fifo_expanding_mode {
HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0,
HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1,
HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2,
HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3,
HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F,
};
enum halmac_sdio_cmd53_4byte_mode {
HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0,
HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1,
HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2,
HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3,
HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F,
};
enum halmac_usb_mode {
HALMAC_USB_MODE_U2 = 1,
HALMAC_USB_MODE_U3 = 2,
};
enum halmac_hw_id {
/* Get HW value */
HALMAC_HW_RQPN_MAPPING = 0x00,
HALMAC_HW_EFUSE_SIZE = 0x01,
HALMAC_HW_EEPROM_SIZE = 0x02,
HALMAC_HW_BT_BANK_EFUSE_SIZE = 0x03,
HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04,
HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05,
HALMAC_HW_TXFIFO_SIZE = 0x06,
HALMAC_HW_RSVD_PG_BNDY = 0x07,
HALMAC_HW_CAM_ENTRY_NUM = 0x08,
HALMAC_HW_IC_VERSION = 0x09,
HALMAC_HW_PAGE_SIZE = 0x0A,
HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0B,
HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0C,
HALMAC_HW_DRV_INFO_SIZE = 0x0D,
HALMAC_HW_TXFF_ALLOCATION = 0x0E,
HALMAC_HW_RSVD_EFUSE_SIZE = 0x0F,
HALMAC_HW_FW_HDR_SIZE = 0x10,
HALMAC_HW_TX_DESC_SIZE = 0x11,
HALMAC_HW_RX_DESC_SIZE = 0x12,
HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x13,
/* Set HW value */
HALMAC_HW_USB_MODE = 0x60,
HALMAC_HW_SEQ_EN = 0x61,
HALMAC_HW_BANDWIDTH = 0x62,
HALMAC_HW_CHANNEL = 0x63,
HALMAC_HW_PRI_CHANNEL_IDX = 0x64,
HALMAC_HW_EN_BB_RF = 0x65,
HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66,
HALMAC_HW_AMPDU_CONFIG = 0x67,
HALMAC_HW_ID_UNDEFINE = 0x7F,
};
enum halmac_efuse_bank {
HALMAC_EFUSE_BANK_WIFI = 0,
HALMAC_EFUSE_BANK_BT = 1,
HALMAC_EFUSE_BANK_BT_1 = 2,
HALMAC_EFUSE_BANK_BT_2 = 3,
HALMAC_EFUSE_BANK_MAX,
HALMAC_EFUSE_BANK_UNDEFINE = 0X7F,
};
struct halmac_txff_allocation {
u16 tx_fifo_pg_num;
u16 rsvd_pg_num;
u16 rsvd_drv_pg_num;
u16 ac_q_pg_num;
u16 high_queue_pg_num;
u16 low_queue_pg_num;
u16 normal_queue_pg_num;
u16 extra_queue_pg_num;
u16 pub_queue_pg_num;
u16 rsvd_pg_bndy;
u16 rsvd_drv_pg_bndy;
u16 rsvd_h2c_extra_info_pg_bndy;
u16 rsvd_h2c_queue_pg_bndy;
u16 rsvd_cpu_instr_pg_bndy;
u16 rsvd_fw_txbuff_pg_bndy;
enum halmac_la_mode la_mode;
enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode;
};
struct halmac_rqpn_map {
enum halmac_dma_mapping dma_map_vo;
enum halmac_dma_mapping dma_map_vi;
enum halmac_dma_mapping dma_map_be;
enum halmac_dma_mapping dma_map_bk;
enum halmac_dma_mapping dma_map_mg;
enum halmac_dma_mapping dma_map_hi;
};
struct halmac_security_setting {
u8 tx_encryption;
u8 rx_decryption;
u8 bip_enable;
};
struct halmac_cam_entry_info {
enum hal_security_type security_type;
u32 key[4];
u32 key_ext[4];
u8 mac_address[6];
u8 unicast;
u8 key_id;
u8 valid;
};
struct halmac_cam_entry_format {
u16 key_id : 2;
u16 type : 3;
u16 mic : 1;
u16 grp : 1;
u16 spp_mode : 1;
u16 rpt_md : 1;
u16 ext_sectype : 1;
u16 mgnt : 1;
u16 rsvd1 : 4;
u16 valid : 1;
u8 mac_address[6];
u32 key[4];
u32 rsvd[2];
};
struct halmac_tx_page_threshold_info {
u32 threshold;
enum halmac_dma_mapping dma_queue_sel;
};
struct halmac_ampdu_config {
u8 max_agg_num;
};
struct halmac_port_cfg {
u8 port0_sync_tsf;
u8 port1_sync_tsf;
};
struct halmac_rqpn_ {
enum halmac_trx_mode mode;
enum halmac_dma_mapping dma_map_vo;
enum halmac_dma_mapping dma_map_vi;
enum halmac_dma_mapping dma_map_be;
enum halmac_dma_mapping dma_map_bk;
enum halmac_dma_mapping dma_map_mg;
enum halmac_dma_mapping dma_map_hi;
};
struct halmac_pg_num_ {
enum halmac_trx_mode mode;
u16 hq_num;
u16 nq_num;
u16 lq_num;
u16 exq_num;
u16 gap_num; /*used for loopback mode*/
};
struct halmac_intf_phy_para_ {
u16 offset;
u16 value;
u16 ip_sel;
u16 cut;
u16 plaform;
};
struct halmac_iqk_para_ {
u8 clear;
u8 segment_iqk;
};
/* Hal mac adapter */
struct halmac_adapter {
/* Dma mapping of protocol queues */
enum halmac_dma_mapping halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM];
/* low power state option */
struct halmac_fwlps_option fwlps_option;
/* mac address information, suppot 2 ports */
union halmac_wlan_addr hal_mac_addr[HALMAC_PORTIDMAX];
/* bss address information, suppot 2 ports */
union halmac_wlan_addr hal_bss_addr[HALMAC_PORTIDMAX];
/* Protect h2c_packet_seq packet*/
spinlock_t h2c_seq_lock;
/* Protect Efuse map memory of halmac_adapter */
spinlock_t efuse_lock;
struct halmac_config_para_info config_para_info;
struct halmac_cs_info ch_sw_info;
struct halmac_event_trigger event_trigger;
/* HW related information */
struct halmac_hw_config_info hw_config_info;
struct halmac_sdio_free_space sdio_free_space;
struct halmac_snd_info snd_info;
/* Backup HalAdapter address */
void *hal_adapter_backup;
/* Driver or FW adapter address. Do not write this memory*/
void *driver_adapter;
u8 *hal_efuse_map;
/* Record function pointer of halmac api */
void *halmac_api;
/* Record function pointer of platform api */
struct halmac_platform_api *halmac_platform_api;
/* Record efuse used memory */
u32 efuse_end;
u32 h2c_buf_free_space;
u32 h2c_buff_size;
u32 max_download_size;
/* Chip ID, 8822B, 8821C... */
enum halmac_chip_id chip_id;
/* A cut, B cut... */
enum halmac_chip_ver chip_version;
struct halmac_fw_version fw_version;
struct halmac_state halmac_state;
/* Interface information, get from driver */
enum halmac_interface halmac_interface;
/* Noraml, WMM, P2P, LoopBack... */
enum halmac_trx_mode trx_mode;
struct halmac_txff_allocation txff_allocation;
u8 h2c_packet_seq; /* current h2c packet sequence number */
u16 ack_h2c_packet_seq; /*the acked h2c packet sequence number */
bool hal_efuse_map_valid;
u8 efuse_segment_size;
u8 rpwm_record; /* record rpwm value */
bool low_clk; /*LPS 32K or IPS 32K*/
u8 halmac_bulkout_num; /* USB bulkout num */
struct halmac_api_record api_record; /* API record */
bool gen_info_valid;
struct halmac_general_info general_info;
u8 drv_info_size;
enum halmac_sdio_cmd53_4byte_mode sdio_cmd53_4byte;
};
/* Function pointer of Hal mac API */
struct halmac_api {
enum halmac_ret_status (*halmac_mac_power_switch)(
struct halmac_adapter *halmac_adapter,
enum halmac_mac_power halmac_power);
enum halmac_ret_status (*halmac_download_firmware)(
struct halmac_adapter *halmac_adapter, u8 *hamacl_fw,
u32 halmac_fw_size);
enum halmac_ret_status (*halmac_free_download_firmware)(
struct halmac_adapter *halmac_adapter,
enum halmac_dlfw_mem dlfw_mem, u8 *hamacl_fw,
u32 halmac_fw_size);
enum halmac_ret_status (*halmac_get_fw_version)(
struct halmac_adapter *halmac_adapter,
struct halmac_fw_version *fw_version);
enum halmac_ret_status (*halmac_cfg_mac_addr)(
struct halmac_adapter *halmac_adapter, u8 halmac_port,
union halmac_wlan_addr *hal_address);
enum halmac_ret_status (*halmac_cfg_bssid)(
struct halmac_adapter *halmac_adapter, u8 halmac_port,
union halmac_wlan_addr *hal_address);
enum halmac_ret_status (*halmac_cfg_multicast_addr)(
struct halmac_adapter *halmac_adapter,
union halmac_wlan_addr *hal_address);
enum halmac_ret_status (*halmac_pre_init_system_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_init_system_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_init_trx_cfg)(
struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode mode);
enum halmac_ret_status (*halmac_init_h2c)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_cfg_rx_aggregation)(
struct halmac_adapter *halmac_adapter,
struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
enum halmac_ret_status (*halmac_init_protocol_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_init_edca_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_cfg_operation_mode)(
struct halmac_adapter *halmac_adapter,
enum halmac_wireless_mode wireless_mode);
enum halmac_ret_status (*halmac_cfg_ch_bw)(
struct halmac_adapter *halmac_adapter, u8 channel,
enum halmac_pri_ch_idx pri_ch_idx, enum halmac_bw bw);
enum halmac_ret_status (*halmac_cfg_bw)(
struct halmac_adapter *halmac_adapter, enum halmac_bw bw);
enum halmac_ret_status (*halmac_init_wmac_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_init_mac_cfg)(
struct halmac_adapter *halmac_adapter,
enum halmac_trx_mode mode);
enum halmac_ret_status (*halmac_init_sdio_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_init_usb_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_init_pcie_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_init_interface_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_deinit_sdio_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_deinit_usb_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_deinit_pcie_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_deinit_interface_cfg)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_get_efuse_size)(
struct halmac_adapter *halmac_adapter, u32 *halmac_size);
enum halmac_ret_status (*halmac_get_efuse_available_size)(
struct halmac_adapter *halmac_adapter, u32 *halmac_size);
enum halmac_ret_status (*halmac_dump_efuse_map)(
struct halmac_adapter *halmac_adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status (*halmac_dump_efuse_map_bt)(
struct halmac_adapter *halmac_adapter,
enum halmac_efuse_bank halmac_efues_bank, u32 bt_efuse_map_size,
u8 *bt_efuse_map);
enum halmac_ret_status (*halmac_write_efuse)(
struct halmac_adapter *halmac_adapter, u32 halmac_offset,
u8 halmac_value);
enum halmac_ret_status (*halmac_read_efuse)(
struct halmac_adapter *halmac_adapter, u32 halmac_offset,
u8 *value);
enum halmac_ret_status (*halmac_switch_efuse_bank)(
struct halmac_adapter *halmac_adapter,
enum halmac_efuse_bank halmac_efues_bank);
enum halmac_ret_status (*halmac_write_efuse_bt)(
struct halmac_adapter *halmac_adapter, u32 halmac_offset,
u8 halmac_value, enum halmac_efuse_bank halmac_efues_bank);
enum halmac_ret_status (*halmac_get_logical_efuse_size)(
struct halmac_adapter *halmac_adapter, u32 *halmac_size);
enum halmac_ret_status (*halmac_dump_logical_efuse_map)(
struct halmac_adapter *halmac_adapter,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status (*halmac_write_logical_efuse)(
struct halmac_adapter *halmac_adapter, u32 halmac_offset,
u8 halmac_value);
enum halmac_ret_status (*halmac_read_logical_efuse)(
struct halmac_adapter *halmac_adapter, u32 halmac_offset,
u8 *value);
enum halmac_ret_status (*halmac_pg_efuse_by_map)(
struct halmac_adapter *halmac_adapter,
struct halmac_pg_efuse_info *pg_efuse_info,
enum halmac_efuse_read_cfg cfg);
enum halmac_ret_status (*halmac_get_c2h_info)(
struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
u32 halmac_size);
enum halmac_ret_status (*halmac_cfg_fwlps_option)(
struct halmac_adapter *halmac_adapter,
struct halmac_fwlps_option *lps_option);
enum halmac_ret_status (*halmac_cfg_fwips_option)(
struct halmac_adapter *halmac_adapter,
struct halmac_fwips_option *ips_option);
enum halmac_ret_status (*halmac_enter_wowlan)(
struct halmac_adapter *halmac_adapter,
struct halmac_wowlan_option *wowlan_option);
enum halmac_ret_status (*halmac_leave_wowlan)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_enter_ps)(
struct halmac_adapter *halmac_adapter,
enum halmac_ps_state ps_state);
enum halmac_ret_status (*halmac_leave_ps)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_h2c_lb)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_debug)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_cfg_parameter)(
struct halmac_adapter *halmac_adapter,
struct halmac_phy_parameter_info *para_info, u8 full_fifo);
enum halmac_ret_status (*halmac_update_packet)(
struct halmac_adapter *halmac_adapter,
enum halmac_packet_id pkt_id, u8 *pkt, u32 pkt_size);
enum halmac_ret_status (*halmac_bcn_ie_filter)(
struct halmac_adapter *halmac_adapter,
struct halmac_bcn_ie_info *bcn_ie_info);
u8 (*halmac_reg_read_8)(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status (*halmac_reg_write_8)(
struct halmac_adapter *halmac_adapter, u32 halmac_offset,
u8 halmac_data);
u16 (*halmac_reg_read_16)(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
enum halmac_ret_status (*halmac_reg_write_16)(
struct halmac_adapter *halmac_adapter, u32 halmac_offset,
u16 halmac_data);
u32 (*halmac_reg_read_32)(struct halmac_adapter *halmac_adapter,
u32 halmac_offset);
u32 (*halmac_reg_read_indirect_32)(
struct halmac_adapter *halmac_adapter, u32 halmac_offset);
u8 (*halmac_reg_sdio_cmd53_read_n)(
struct halmac_adapter *halmac_adapter, u32 halmac_offset,
u32 halmac_size, u8 *halmac_data);
enum halmac_ret_status (*halmac_reg_write_32)(
struct halmac_adapter *halmac_adapter, u32 halmac_offset,
u32 halmac_data);
enum halmac_ret_status (*halmac_tx_allowed_sdio)(
struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
u32 halmac_size);
enum halmac_ret_status (*halmac_set_bulkout_num)(
struct halmac_adapter *halmac_adapter, u8 bulkout_num);
enum halmac_ret_status (*halmac_get_sdio_tx_addr)(
struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
u32 halmac_size, u32 *pcmd53_addr);
enum halmac_ret_status (*halmac_get_usb_bulkout_id)(
struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
u32 halmac_size, u8 *bulkout_id);
enum halmac_ret_status (*halmac_timer_2s)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_fill_txdesc_checksum)(
struct halmac_adapter *halmac_adapter, u8 *cur_desc);
enum halmac_ret_status (*halmac_update_datapack)(
struct halmac_adapter *halmac_adapter,
enum halmac_data_type halmac_data_type,
struct halmac_phy_parameter_info *para_info);
enum halmac_ret_status (*halmac_run_datapack)(
struct halmac_adapter *halmac_adapter,
enum halmac_data_type halmac_data_type);
enum halmac_ret_status (*halmac_cfg_drv_info)(
struct halmac_adapter *halmac_adapter,
enum halmac_drv_info halmac_drv_info);
enum halmac_ret_status (*halmac_send_bt_coex)(
struct halmac_adapter *halmac_adapter, u8 *bt_buf, u32 bt_size,
u8 ack);
enum halmac_ret_status (*halmac_verify_platform_api)(
struct halmac_adapter *halmac_adapte);
u32 (*halmac_get_fifo_size)(struct halmac_adapter *halmac_adapter,
enum hal_fifo_sel halmac_fifo_sel);
enum halmac_ret_status (*halmac_dump_fifo)(
struct halmac_adapter *halmac_adapter,
enum hal_fifo_sel halmac_fifo_sel, u32 halmac_start_addr,
u32 halmac_fifo_dump_size, u8 *fifo_map);
enum halmac_ret_status (*halmac_cfg_txbf)(
struct halmac_adapter *halmac_adapter, u8 userid,
enum halmac_bw bw, u8 txbf_en);
enum halmac_ret_status (*halmac_cfg_mumimo)(
struct halmac_adapter *halmac_adapter,
struct halmac_cfg_mumimo_para *cfgmu);
enum halmac_ret_status (*halmac_cfg_sounding)(
struct halmac_adapter *halmac_adapter,
enum halmac_snd_role role, enum halmac_data_rate datarate);
enum halmac_ret_status (*halmac_del_sounding)(
struct halmac_adapter *halmac_adapter,
enum halmac_snd_role role);
enum halmac_ret_status (*halmac_su_bfer_entry_init)(
struct halmac_adapter *halmac_adapter,
struct halmac_su_bfer_init_para *su_bfer_init);
enum halmac_ret_status (*halmac_su_bfee_entry_init)(
struct halmac_adapter *halmac_adapter, u8 userid, u16 paid);
enum halmac_ret_status (*halmac_mu_bfer_entry_init)(
struct halmac_adapter *halmac_adapter,
struct halmac_mu_bfer_init_para *mu_bfer_init);
enum halmac_ret_status (*halmac_mu_bfee_entry_init)(
struct halmac_adapter *halmac_adapter,
struct halmac_mu_bfee_init_para *mu_bfee_init);
enum halmac_ret_status (*halmac_su_bfer_entry_del)(
struct halmac_adapter *halmac_adapter, u8 userid);
enum halmac_ret_status (*halmac_su_bfee_entry_del)(
struct halmac_adapter *halmac_adapter, u8 userid);
enum halmac_ret_status (*halmac_mu_bfer_entry_del)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_mu_bfee_entry_del)(
struct halmac_adapter *halmac_adapter, u8 userid);
enum halmac_ret_status (*halmac_add_ch_info)(
struct halmac_adapter *halmac_adapter,
struct halmac_ch_info *ch_info);
enum halmac_ret_status (*halmac_add_extra_ch_info)(
struct halmac_adapter *halmac_adapter,
struct halmac_ch_extra_info *ch_extra_info);
enum halmac_ret_status (*halmac_ctrl_ch_switch)(
struct halmac_adapter *halmac_adapter,
struct halmac_ch_switch_option *cs_option);
enum halmac_ret_status (*halmac_p2pps)(
struct halmac_adapter *halmac_adapter,
struct halmac_p2pps *p2p_ps);
enum halmac_ret_status (*halmac_clear_ch_info)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_send_general_info)(
struct halmac_adapter *halmac_adapter,
struct halmac_general_info *pg_general_info);
enum halmac_ret_status (*halmac_start_iqk)(
struct halmac_adapter *halmac_adapter,
struct halmac_iqk_para_ *iqk_para);
enum halmac_ret_status (*halmac_ctrl_pwr_tracking)(
struct halmac_adapter *halmac_adapter,
struct halmac_pwr_tracking_option *pwr_tracking_opt);
enum halmac_ret_status (*halmac_psd)(
struct halmac_adapter *halmac_adapter, u16 start_psd,
u16 end_psd);
enum halmac_ret_status (*halmac_cfg_tx_agg_align)(
struct halmac_adapter *halmac_adapter, u8 enable,
u16 align_size);
enum halmac_ret_status (*halmac_query_status)(
struct halmac_adapter *halmac_adapter,
enum halmac_feature_id feature_id,
enum halmac_cmd_process_status *process_status, u8 *data,
u32 *size);
enum halmac_ret_status (*halmac_reset_feature)(
struct halmac_adapter *halmac_adapter,
enum halmac_feature_id feature_id);
enum halmac_ret_status (*halmac_check_fw_status)(
struct halmac_adapter *halmac_adapter, bool *fw_status);
enum halmac_ret_status (*halmac_dump_fw_dmem)(
struct halmac_adapter *halmac_adapter, u8 *dmem, u32 *size);
enum halmac_ret_status (*halmac_cfg_max_dl_size)(
struct halmac_adapter *halmac_adapter, u32 size);
enum halmac_ret_status (*halmac_cfg_la_mode)(
struct halmac_adapter *halmac_adapter,
enum halmac_la_mode la_mode);
enum halmac_ret_status (*halmac_cfg_rx_fifo_expanding_mode)(
struct halmac_adapter *halmac_adapter,
enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode);
enum halmac_ret_status (*halmac_config_security)(
struct halmac_adapter *halmac_adapter,
struct halmac_security_setting *sec_setting);
u8 (*halmac_get_used_cam_entry_num)(
struct halmac_adapter *halmac_adapter,
enum hal_security_type sec_type);
enum halmac_ret_status (*halmac_write_cam)(
struct halmac_adapter *halmac_adapter, u32 entry_index,
struct halmac_cam_entry_info *cam_entry_info);
enum halmac_ret_status (*halmac_read_cam_entry)(
struct halmac_adapter *halmac_adapter, u32 entry_index,
struct halmac_cam_entry_format *content);
enum halmac_ret_status (*halmac_clear_cam_entry)(
struct halmac_adapter *halmac_adapter, u32 entry_index);
enum halmac_ret_status (*halmac_get_hw_value)(
struct halmac_adapter *halmac_adapter, enum halmac_hw_id hw_id,
void *pvalue);
enum halmac_ret_status (*halmac_set_hw_value)(
struct halmac_adapter *halmac_adapter, enum halmac_hw_id hw_id,
void *pvalue);
enum halmac_ret_status (*halmac_cfg_drv_rsvd_pg_num)(
struct halmac_adapter *halmac_adapter,
enum halmac_drv_rsvd_pg_num pg_num);
enum halmac_ret_status (*halmac_get_chip_version)(
struct halmac_adapter *halmac_adapter,
struct halmac_ver *version);
enum halmac_ret_status (*halmac_chk_txdesc)(
struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
u32 halmac_size);
enum halmac_ret_status (*halmac_dl_drv_rsvd_page)(
struct halmac_adapter *halmac_adapter, u8 pg_offset,
u8 *hal_buf, u32 size);
enum halmac_ret_status (*halmac_pcie_switch)(
struct halmac_adapter *halmac_adapter,
enum halmac_pcie_cfg pcie_cfg);
enum halmac_ret_status (*halmac_phy_cfg)(
struct halmac_adapter *halmac_adapter,
enum halmac_intf_phy_platform platform);
enum halmac_ret_status (*halmac_cfg_csi_rate)(
struct halmac_adapter *halmac_adapter, u8 rssi, u8 current_rate,
u8 fixrate_en, u8 *new_rate);
enum halmac_ret_status (*halmac_sdio_cmd53_4byte)(
struct halmac_adapter *halmac_adapter,
enum halmac_sdio_cmd53_4byte_mode cmd53_4byte_mode);
enum halmac_ret_status (*halmac_interface_integration_tuning)(
struct halmac_adapter *halmac_adapter);
enum halmac_ret_status (*halmac_txfifo_is_empty)(
struct halmac_adapter *halmac_adapter, u32 chk_num);
};
#define HALMAC_GET_API(phalmac_adapter) \
((struct halmac_api *)phalmac_adapter->halmac_api)
static inline enum halmac_ret_status
halmac_adapter_validate(struct halmac_adapter *halmac_adapter)
{
if ((!halmac_adapter) ||
(halmac_adapter->hal_adapter_backup != halmac_adapter))
return HALMAC_RET_ADAPTER_INVALID;
return HALMAC_RET_SUCCESS;
}
static inline enum halmac_ret_status
halmac_api_validate(struct halmac_adapter *halmac_adapter)
{
if (halmac_adapter->halmac_state.api_state != HALMAC_API_STATE_INIT)
return HALMAC_RET_API_INVALID;
return HALMAC_RET_SUCCESS;
}
static inline enum halmac_ret_status
halmac_fw_validate(struct halmac_adapter *halmac_adapter)
{
if (halmac_adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE &&
halmac_adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT)
return HALMAC_RET_NO_DLFW;
return HALMAC_RET_SUCCESS;
}
#endif
drivers/staging/rtlwifi/halmac/halmac_usb_reg.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALMAC_USB_REG_H__
#define __HALMAC_USB_REG_H__
#endif /* __HALMAC_USB_REG_H__ */
drivers/staging/rtlwifi/halmac/rtl_halmac.c 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "halmac_api.h"
#include "rtl_halmac.h"
#include <linux/module.h>
#include <linux/vmalloc.h>
#define DEFAULT_INDICATOR_TIMELMT msecs_to_jiffies(1000) /* ms */
#define FIRMWARE_MAX_SIZE HALMAC_FW_SIZE_MAX_88XX
static struct rtl_halmac_ops rtl_halmac_operation = {
.halmac_init_adapter = rtl_halmac_init_adapter,
.halmac_deinit_adapter = rtl_halmac_deinit_adapter,
.halmac_init_hal = rtl_halmac_init_hal,
.halmac_deinit_hal = rtl_halmac_deinit_hal,
.halmac_poweron = rtl_halmac_poweron,
.halmac_poweroff = rtl_halmac_poweroff,
.halmac_phy_power_switch = rtl_halmac_phy_power_switch,
.halmac_set_mac_address = rtl_halmac_set_mac_address,
.halmac_set_bssid = rtl_halmac_set_bssid,
.halmac_get_physical_efuse_size = rtl_halmac_get_physical_efuse_size,
.halmac_read_physical_efuse_map = rtl_halmac_read_physical_efuse_map,
.halmac_get_logical_efuse_size = rtl_halmac_get_logical_efuse_size,
.halmac_read_logical_efuse_map = rtl_halmac_read_logical_efuse_map,
.halmac_set_bandwidth = rtl_halmac_set_bandwidth,
.halmac_c2h_handle = rtl_halmac_c2h_handle,
.halmac_chk_txdesc = rtl_halmac_chk_txdesc,
};
struct rtl_halmac_ops *rtl_halmac_get_ops_pointer(void)
{
return &rtl_halmac_operation;
}
EXPORT_SYMBOL(rtl_halmac_get_ops_pointer);
/*
* Driver API for HALMAC operations
*/
static u8 _halmac_reg_read_8(void *p, u32 offset)
{
struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
return rtl_read_byte(rtlpriv, offset);
}
static u16 _halmac_reg_read_16(void *p, u32 offset)
{
struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
return rtl_read_word(rtlpriv, offset);
}
static u32 _halmac_reg_read_32(void *p, u32 offset)
{
struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
return rtl_read_dword(rtlpriv, offset);
}
static void _halmac_reg_write_8(void *p, u32 offset, u8 val)
{
struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
rtl_write_byte(rtlpriv, offset, val);
}
static void _halmac_reg_write_16(void *p, u32 offset, u16 val)
{
struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
rtl_write_word(rtlpriv, offset, val);
}
static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
{
struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
rtl_write_dword(rtlpriv, offset, val);
}
static bool _halmac_write_data_rsvd_page(void *p, u8 *buf, u32 size)
{
struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
if (rtlpriv->cfg->ops->halmac_cb_write_data_rsvd_page &&
rtlpriv->cfg->ops->halmac_cb_write_data_rsvd_page(rtlpriv, buf,
size))
return true;
return false;
}
static bool _halmac_write_data_h2c(void *p, u8 *buf, u32 size)
{
struct rtl_priv *rtlpriv = (struct rtl_priv *)p;
if (rtlpriv->cfg->ops->halmac_cb_write_data_h2c &&
rtlpriv->cfg->ops->halmac_cb_write_data_h2c(rtlpriv, buf, size))
return true;
return false;
}
static const char *const RTL_HALMAC_FEATURE_NAME[] = {
"HALMAC_FEATURE_CFG_PARA",
"HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE",
"HALMAC_FEATURE_DUMP_LOGICAL_EFUSE",
"HALMAC_FEATURE_UPDATE_PACKET",
"HALMAC_FEATURE_UPDATE_DATAPACK",
"HALMAC_FEATURE_RUN_DATAPACK",
"HALMAC_FEATURE_CHANNEL_SWITCH",
"HALMAC_FEATURE_IQK",
"HALMAC_FEATURE_POWER_TRACKING",
"HALMAC_FEATURE_PSD",
"HALMAC_FEATURE_ALL"};
static inline bool is_valid_id_status(struct rtl_priv *rtlpriv,
enum halmac_feature_id id,
enum halmac_cmd_process_status status)
{
switch (id) {
case HALMAC_FEATURE_CFG_PARA:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
if (status != HALMAC_CMD_PROCESS_DONE) {
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
"%s: <WARN> id(%d) unspecified status(%d)!\n",
__func__, id, status);
}
break;
case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
if (status != HALMAC_CMD_PROCESS_DONE) {
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
"%s: <WARN> id(%d) unspecified status(%d)!\n",
__func__, id, status);
}
break;
case HALMAC_FEATURE_UPDATE_PACKET:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_UPDATE_DATAPACK:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_RUN_DATAPACK:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_CHANNEL_SWITCH:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_IQK:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_POWER_TRACKING:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_PSD:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_ALL:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: %s\n", __func__,
RTL_HALMAC_FEATURE_NAME[id]);
break;
default:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
"%s: unknown feature id(%d)\n", __func__, id);
return false;
}
return true;
}
static int init_halmac_event_with_waittime(struct rtl_priv *rtlpriv,
enum halmac_feature_id id, u8 *buf,
u32 size, u32 time)
{
struct completion *comp;
if (!rtlpriv->halmac.indicator[id].comp) {
comp = kzalloc(sizeof(*comp), GFP_KERNEL);
if (!comp)
return -1;
} else {
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
"%s: <WARN> id(%d) sctx is not NULL!!\n", __func__,
id);
comp = rtlpriv->halmac.indicator[id].comp;
rtlpriv->halmac.indicator[id].comp = NULL;
}
init_completion(comp);
rtlpriv->halmac.indicator[id].wait_ms = time;
rtlpriv->halmac.indicator[id].buffer = buf;
rtlpriv->halmac.indicator[id].buf_size = size;
rtlpriv->halmac.indicator[id].ret_size = 0;
rtlpriv->halmac.indicator[id].status = 0;
/* fill sctx at least to sure other variables are all ready! */
rtlpriv->halmac.indicator[id].comp = comp;
return 0;
}
static inline int init_halmac_event(struct rtl_priv *rtlpriv,
enum halmac_feature_id id, u8 *buf,
u32 size)
{
return init_halmac_event_with_waittime(rtlpriv, id, buf, size,
DEFAULT_INDICATOR_TIMELMT);
}
static void free_halmac_event(struct rtl_priv *rtlpriv,
enum halmac_feature_id id)
{
struct completion *comp;
if (!rtlpriv->halmac.indicator[id].comp)
return;
comp = rtlpriv->halmac.indicator[id].comp;
rtlpriv->halmac.indicator[id].comp = NULL;
kfree(comp);
}
static int wait_halmac_event(struct rtl_priv *rtlpriv,
enum halmac_feature_id id)
{
struct completion *comp;
int ret;
comp = rtlpriv->halmac.indicator[id].comp;
if (!comp)
return -1;
ret = wait_for_completion_timeout(
comp, rtlpriv->halmac.indicator[id].wait_ms);
free_halmac_event(rtlpriv, id);
if (ret > 0)
return 0;
return -1;
}
/*
* Return:
* Always return true, HALMAC don't care the return value.
*/
static bool
_halmac_event_indication(void *p, enum halmac_feature_id feature_id,
enum halmac_cmd_process_status process_status, u8 *buf,
u32 size)
{
struct rtl_priv *rtlpriv;
struct rtl_halmac_indicator *tbl, *indicator;
struct completion *comp;
u32 cpsz;
bool ret;
rtlpriv = (struct rtl_priv *)p;
tbl = rtlpriv->halmac.indicator;
ret = is_valid_id_status(rtlpriv, feature_id, process_status);
if (!ret)
goto exit;
indicator = &tbl[feature_id];
indicator->status = process_status;
indicator->ret_size = size;
if (!indicator->comp) {
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
"%s: No feature id(%d) waiting!!\n", __func__,
feature_id);
goto exit;
}
comp = indicator->comp;
if (process_status == HALMAC_CMD_PROCESS_ERROR) {
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
"%s: Something wrong id(%d)!!\n", __func__,
feature_id);
complete(comp); /* may provide error code */
goto exit;
}
if (size > indicator->buf_size) {
RT_TRACE(
rtlpriv, COMP_HALMAC, DBG_LOUD,
"%s: <WARN> id(%d) buffer is not enough(%d<%d), data will be truncated!\n",
__func__, feature_id, indicator->buf_size, size);
cpsz = indicator->buf_size;
} else {
cpsz = size;
}
if (cpsz && indicator->buffer)
memcpy(indicator->buffer, buf, cpsz);
complete(comp);
exit:
return true;
}
static struct halmac_platform_api rtl_halmac_platform_api = {
/* R/W register */
.REG_READ_8 = _halmac_reg_read_8,
.REG_READ_16 = _halmac_reg_read_16,
.REG_READ_32 = _halmac_reg_read_32,
.REG_WRITE_8 = _halmac_reg_write_8,
.REG_WRITE_16 = _halmac_reg_write_16,
.REG_WRITE_32 = _halmac_reg_write_32,
/* Write data */
/* impletement in HAL-IC level */
.SEND_RSVD_PAGE = _halmac_write_data_rsvd_page,
.SEND_H2C_PKT = _halmac_write_data_h2c,
.EVENT_INDICATION = _halmac_event_indication,
};
static int init_priv(struct rtl_halmac *halmac)
{
struct rtl_halmac_indicator *indicator;
u32 count, size;
halmac->send_general_info = 0;
count = HALMAC_FEATURE_ALL + 1;
size = sizeof(*indicator) * count;
indicator = kzalloc(size, GFP_KERNEL);
if (!indicator)
return -1;
halmac->indicator = indicator;
return 0;
}
static void deinit_priv(struct rtl_halmac *halmac)
{
struct rtl_halmac_indicator *indicator;
indicator = halmac->indicator;
halmac->indicator = NULL;
if (indicator) {
u32 count, size;
count = HALMAC_FEATURE_ALL + 1;
#ifdef CONFIG_RTL_DEBUG
{
struct submit_ctx *sctx;
u32 i;
for (i = 0; i < count; i++) {
if (!indicator[i].sctx)
continue;
RT_TRACE(
rtlpriv, COMP_HALMAC, DBG_LOUD,
"%s: <WARN> %s id(%d) sctx still exist!!\n",
__func__, RTL_HALMAC_FEATURE_NAME[i],
i);
sctx = indicator[i].sctx;
indicator[i].sctx = NULL;
rtl_mfree((u8 *)sctx, sizeof(*sctx));
}
}
#endif /* !CONFIG_RTL_DEBUG */
size = sizeof(*indicator) * count;
kfree((u8 *)indicator);
}
}
int rtl_halmac_init_adapter(struct rtl_priv *rtlpriv)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
enum halmac_interface intf;
enum halmac_ret_status status;
int err = 0;
struct halmac_platform_api *pf_api = &rtl_halmac_platform_api;
halmac = rtlpriv_to_halmac(rtlpriv);
if (halmac) {
err = 0;
goto out;
}
err = init_priv(&rtlpriv->halmac);
if (err)
goto out;
intf = HALMAC_INTERFACE_PCIE;
status = halmac_init_adapter(rtlpriv, pf_api, intf, &halmac, &api);
if (status != HALMAC_RET_SUCCESS) {
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
"%s: halmac_init_adapter fail!(status=%d)\n", __func__,
status);
err = -1;
goto out;
}
rtlpriv->halmac.internal = halmac;
out:
if (err)
rtl_halmac_deinit_adapter(rtlpriv);
return err;
}
int rtl_halmac_deinit_adapter(struct rtl_priv *rtlpriv)
{
struct halmac_adapter *halmac;
enum halmac_ret_status status;
int err = 0;
halmac = rtlpriv_to_halmac(rtlpriv);
if (!halmac) {
err = 0;
goto out;
}
deinit_priv(&rtlpriv->halmac);
halmac_halt_api(halmac);
status = halmac_deinit_adapter(halmac);
rtlpriv->halmac.internal = NULL;
if (status != HALMAC_RET_SUCCESS) {
err = -1;
goto out;
}
out:
return err;
}
int rtl_halmac_poweron(struct rtl_priv *rtlpriv)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
enum halmac_ret_status status;
int err = -1;
halmac = rtlpriv_to_halmac(rtlpriv);
if (!halmac)
goto out;
api = HALMAC_GET_API(halmac);
status = api->halmac_pre_init_system_cfg(halmac);
if (status != HALMAC_RET_SUCCESS)
goto out;
status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON);
if (status != HALMAC_RET_SUCCESS)
goto out;
status = api->halmac_init_system_cfg(halmac);
if (status != HALMAC_RET_SUCCESS)
goto out;
err = 0;
out:
return err;
}
int rtl_halmac_poweroff(struct rtl_priv *rtlpriv)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
enum halmac_ret_status status;
int err = -1;
halmac = rtlpriv_to_halmac(rtlpriv);
if (!halmac)
goto out;
api = HALMAC_GET_API(halmac);
status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF);
if (status != HALMAC_RET_SUCCESS)
goto out;
err = 0;
out:
return err;
}
/*
* Note:
* When this function return, the register REG_RCR may be changed.
*/
int rtl_halmac_config_rx_info(struct rtl_priv *rtlpriv,
enum halmac_drv_info info)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
enum halmac_ret_status status;
int err = -1;
halmac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(halmac);
status = api->halmac_cfg_drv_info(halmac, info);
if (status != HALMAC_RET_SUCCESS)
goto out;
err = 0;
out:
return err;
}
static enum halmac_ret_status init_mac_flow(struct rtl_priv *rtlpriv)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
enum halmac_ret_status status;
u8 wifi_test = 0;
int err;
halmac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(halmac);
if (wifi_test)
status = api->halmac_init_mac_cfg(halmac, HALMAC_TRX_MODE_WMM);
else
status = api->halmac_init_mac_cfg(halmac,
HALMAC_TRX_MODE_NORMAL);
if (status != HALMAC_RET_SUCCESS)
goto out;
err = rtl_halmac_rx_agg_switch(rtlpriv, true);
if (err)
goto out;
if (rtlpriv->cfg->maps[RTL_RC_VHT_RATE_1SS_MCS7])
status = api->halmac_cfg_operation_mode(
halmac, HALMAC_WIRELESS_MODE_AC);
else if (rtlpriv->cfg->maps[RTL_RC_HT_RATEMCS7])
status = api->halmac_cfg_operation_mode(halmac,
HALMAC_WIRELESS_MODE_N);
else if (rtlpriv->cfg->maps[RTL_RC_OFDM_RATE6M])
status = api->halmac_cfg_operation_mode(halmac,
HALMAC_WIRELESS_MODE_G);
else
status = api->halmac_cfg_operation_mode(halmac,
HALMAC_WIRELESS_MODE_B);
if (status != HALMAC_RET_SUCCESS)
goto out;
out:
return status;
}
static inline enum halmac_rf_type _rf_type_drv2halmac(enum rf_type rf_drv)
{
enum halmac_rf_type rf_mac;
switch (rf_drv) {
case RF_1T2R:
rf_mac = HALMAC_RF_1T2R;
break;
case RF_2T2R:
rf_mac = HALMAC_RF_2T2R;
break;
case RF_1T1R:
rf_mac = HALMAC_RF_1T1R;
break;
case RF_2T2R_GREEN:
rf_mac = HALMAC_RF_2T2R_GREEN;
break;
default:
rf_mac = (enum halmac_rf_type)rf_drv;
break;
}
return rf_mac;
}
static int _send_general_info(struct rtl_priv *rtlpriv)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
struct halmac_general_info info;
enum halmac_ret_status status;
halmac = rtlpriv_to_halmac(rtlpriv);
if (!halmac)
return -1;
api = HALMAC_GET_API(halmac);
memset(&info, 0, sizeof(info));
info.rfe_type = rtlpriv->rtlhal.rfe_type;
info.rf_type = _rf_type_drv2halmac(rtlpriv->phy.rf_type);
status = api->halmac_send_general_info(halmac, &info);
switch (status) {
case HALMAC_RET_SUCCESS:
break;
case HALMAC_RET_NO_DLFW:
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_WARNING,
"%s: halmac_send_general_info() fail because fw not dl!\n",
__func__);
/* fallthrough here */
default:
return -1;
}
return 0;
}
/*
* Notices:
* Make sure
* 1. rtl_hal_get_hwreg(HW_VAR_RF_TYPE)
* 2. HAL_DATA_TYPE.rfe_type
* already ready for use before calling this function.
*/
static int _halmac_init_hal(struct rtl_priv *rtlpriv, u8 *fw, u32 fwsize)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
enum halmac_ret_status status;
bool ok;
bool fw_ok = false;
int err, err_ret = -1;
halmac = rtlpriv_to_halmac(rtlpriv);
if (!halmac)
goto out;
api = HALMAC_GET_API(halmac);
/* StatePowerOff */
/* SKIP: halmac_init_adapter (Already done before) */
/* halmac_pre_Init_system_cfg */
/* halmac_mac_power_switch(on) */
/* halmac_Init_system_cfg */
err = rtl_halmac_poweron(rtlpriv);
if (err)
goto out;
/* StatePowerOn */
/* DownloadFW */
rtlpriv->halmac.send_general_info = 0;
if (fw && fwsize) {
err = rtl_halmac_dlfw(rtlpriv, fw, fwsize);
if (err)
goto out;
fw_ok = true;
}
/* InitMACFlow */
status = init_mac_flow(rtlpriv);
if (status != HALMAC_RET_SUCCESS)
goto out;
/* halmac_send_general_info */
if (fw_ok) {
rtlpriv->halmac.send_general_info = 0;
err = _send_general_info(rtlpriv);
if (err)
goto out;
} else {
rtlpriv->halmac.send_general_info = 1;
}
/* Init Phy parameter-MAC */
if (rtlpriv->cfg->ops->halmac_cb_init_mac_register)
ok = rtlpriv->cfg->ops->halmac_cb_init_mac_register(rtlpriv);
else
ok = false;
if (!ok)
goto out;
/* StateMacInitialized */
/* halmac_cfg_drv_info */
err = rtl_halmac_config_rx_info(rtlpriv, HALMAC_DRV_INFO_PHY_STATUS);
if (err)
goto out;
/* halmac_set_hw_value(HALMAC_HW_EN_BB_RF) */
/* Init BB, RF */
if (rtlpriv->cfg->ops->halmac_cb_init_bb_rf_register)
ok = rtlpriv->cfg->ops->halmac_cb_init_bb_rf_register(rtlpriv);
else
ok = false;
if (!ok)
goto out;
status = api->halmac_init_interface_cfg(halmac);
if (status != HALMAC_RET_SUCCESS)
goto out;
/* SKIP: halmac_verify_platform_api */
/* SKIP: halmac_h2c_lb */
/* StateRxIdle */
err_ret = 0;
out:
return err_ret;
}
int rtl_halmac_init_hal(struct rtl_priv *rtlpriv)
{
if (!rtlpriv->rtlhal.pfirmware || rtlpriv->rtlhal.fwsize == 0)
return -1;
return _halmac_init_hal(rtlpriv, rtlpriv->rtlhal.pfirmware,
rtlpriv->rtlhal.fwsize);
}
int rtl_halmac_deinit_hal(struct rtl_priv *rtlpriv)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
enum halmac_ret_status status;
int err = -1;
halmac = rtlpriv_to_halmac(rtlpriv);
if (!halmac)
goto out;
api = HALMAC_GET_API(halmac);
status = api->halmac_deinit_interface_cfg(halmac);
if (status != HALMAC_RET_SUCCESS)
goto out;
/* rtw_hal_power_off(adapter); */
status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF);
if (status != HALMAC_RET_SUCCESS)
goto out;
err = 0;
out:
return err;
}
int rtl_halmac_self_verify(struct rtl_priv *rtlpriv)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
int err = -1;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
status = api->halmac_verify_platform_api(mac);
if (status != HALMAC_RET_SUCCESS)
goto out;
status = api->halmac_h2c_lb(mac);
if (status != HALMAC_RET_SUCCESS)
goto out;
err = 0;
out:
return err;
}
int rtl_halmac_dlfw(struct rtl_priv *rtlpriv, u8 *fw, u32 fwsize)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
struct halmac_fw_version fw_version;
int err = 0;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
if ((!fw) || (!fwsize))
return -1;
/* 1. Driver Stop Tx */
/* ToDo */
/* 2. Driver Check Tx FIFO is empty */
/* ToDo */
/* 3. Config MAX download size */
api->halmac_cfg_max_dl_size(mac, 0x1000);
/* 4. Download Firmware */
mac->h2c_packet_seq = 0;
status = api->halmac_download_firmware(mac, fw, fwsize);
if (status != HALMAC_RET_SUCCESS)
return -1;
status = api->halmac_get_fw_version(mac, &fw_version);
if (status == HALMAC_RET_SUCCESS) {
rtlpriv->rtlhal.fw_version = fw_version.version;
rtlpriv->rtlhal.fw_subversion =
(fw_version.sub_version << 8) | (fw_version.sub_index);
RT_TRACE(
rtlpriv, COMP_HALMAC, DBG_DMESG,
"halmac report firmware version %04X.%04X\n",
rtlpriv->rtlhal.fw_version,
rtlpriv->rtlhal.fw_subversion);
}
if (rtlpriv->halmac.send_general_info) {
rtlpriv->halmac.send_general_info = 0;
err = _send_general_info(rtlpriv);
}
/* 5. Driver resume TX if needed */
/* ToDo */
/* 6. Reset driver variables if needed */
/*hal->LastHMEBoxNum = 0;*/
return err;
}
/*
* Description:
* Power on/off BB/RF domain.
*
* Parameters:
* enable true/false for power on/off
*
* Return:
* 0 Success
* others Fail
*/
int rtl_halmac_phy_power_switch(struct rtl_priv *rtlpriv, u8 enable)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
enum halmac_ret_status status;
halmac = rtlpriv_to_halmac(rtlpriv);
if (!halmac)
return -1;
api = HALMAC_GET_API(halmac);
status = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &enable);
if (status != HALMAC_RET_SUCCESS)
return -1;
return 0;
}
static bool _is_fw_read_cmd_down(struct rtl_priv *rtlpriv, u8 msgbox_num)
{
bool read_down = false;
int retry_cnts = 100;
u8 valid;
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
"%s, reg_1cc(%x), msg_box(%d)...\n", __func__,
rtl_read_byte(rtlpriv, REG_HMETFR), msgbox_num);
do {
valid = rtl_read_byte(rtlpriv, REG_HMETFR) & BIT(msgbox_num);
if (valid == 0)
read_down = true;
else
schedule();
} while ((!read_down) && (retry_cnts--));
return read_down;
}
int rtl_halmac_send_h2c(struct rtl_priv *rtlpriv, u8 *h2c)
{
u8 h2c_box_num = 0;
u32 msgbox_addr = 0;
u32 msgbox_ex_addr = 0;
__le32 h2c_cmd = 0;
__le32 h2c_cmd_ex = 0;
s32 ret = -1;
unsigned long flag = 0;
struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
if (!h2c) {
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD, "%s: pbuf is NULL\n",
__func__);
return ret;
}
spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
/* pay attention to if race condition happened in H2C cmd setting */
h2c_box_num = rtlhal->last_hmeboxnum;
if (!_is_fw_read_cmd_down(rtlpriv, h2c_box_num)) {
RT_TRACE(rtlpriv, COMP_HALMAC, DBG_LOUD,
" fw read cmd failed...\n");
goto exit;
}
/* Write Ext command(byte 4 -7) */
msgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);
memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE);
rtl_write_dword(rtlpriv, msgbox_ex_addr, le32_to_cpu(h2c_cmd_ex));
/* Write command (byte 0 -3 ) */
msgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE);
memcpy((u8 *)(&h2c_cmd), h2c, 4);
rtl_write_dword(rtlpriv, msgbox_addr, le32_to_cpu(h2c_cmd));
/* update last msg box number */
rtlhal->last_hmeboxnum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;
ret = 0;
exit:
spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
return ret;
}
int rtl_halmac_c2h_handle(struct rtl_priv *rtlpriv, u8 *c2h, u32 size)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
status = api->halmac_get_c2h_info(mac, c2h, size);
if (status != HALMAC_RET_SUCCESS)
return -1;
return 0;
}
int rtl_halmac_get_physical_efuse_size(struct rtl_priv *rtlpriv, u32 *size)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
u32 val;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
status = api->halmac_get_efuse_size(mac, &val);
if (status != HALMAC_RET_SUCCESS)
return -1;
*size = val;
return 0;
}
int rtl_halmac_read_physical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
u32 size)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
enum halmac_feature_id id;
int ret;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
id = HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE;
ret = init_halmac_event(rtlpriv, id, map, size);
if (ret)
return -1;
status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_DRV);
if (status != HALMAC_RET_SUCCESS) {
free_halmac_event(rtlpriv, id);
return -1;
}
ret = wait_halmac_event(rtlpriv, id);
if (ret)
return -1;
return 0;
}
int rtl_halmac_read_physical_efuse(struct rtl_priv *rtlpriv, u32 offset,
u32 cnt, u8 *data)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
u8 v;
u32 i;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
for (i = 0; i < cnt; i++) {
status = api->halmac_read_efuse(mac, offset + i, &v);
if (status != HALMAC_RET_SUCCESS)
return -1;
data[i] = v;
}
return 0;
}
int rtl_halmac_write_physical_efuse(struct rtl_priv *rtlpriv, u32 offset,
u32 cnt, u8 *data)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
u32 i;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
for (i = 0; i < cnt; i++) {
status = api->halmac_write_efuse(mac, offset + i, data[i]);
if (status != HALMAC_RET_SUCCESS)
return -1;
}
return 0;
}
int rtl_halmac_get_logical_efuse_size(struct rtl_priv *rtlpriv, u32 *size)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
u32 val;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
status = api->halmac_get_logical_efuse_size(mac, &val);
if (status != HALMAC_RET_SUCCESS)
return -1;
*size = val;
return 0;
}
int rtl_halmac_read_logical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
u32 size)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
enum halmac_feature_id id;
int ret;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
id = HALMAC_FEATURE_DUMP_LOGICAL_EFUSE;
ret = init_halmac_event(rtlpriv, id, map, size);
if (ret)
return -1;
status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_AUTO);
if (status != HALMAC_RET_SUCCESS) {
free_halmac_event(rtlpriv, id);
return -1;
}
ret = wait_halmac_event(rtlpriv, id);
if (ret)
return -1;
return 0;
}
int rtl_halmac_write_logical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
u32 size, u8 *maskmap, u32 masksize)
{
struct halmac_adapter *mac;
struct halmac_api *api;
struct halmac_pg_efuse_info pginfo;
enum halmac_ret_status status;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
pginfo.efuse_map = map;
pginfo.efuse_map_size = size;
pginfo.efuse_mask = maskmap;
pginfo.efuse_mask_size = masksize;
status = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO);
if (status != HALMAC_RET_SUCCESS)
return -1;
return 0;
}
int rtl_halmac_read_logical_efuse(struct rtl_priv *rtlpriv, u32 offset, u32 cnt,
u8 *data)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
u8 v;
u32 i;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
for (i = 0; i < cnt; i++) {
status = api->halmac_read_logical_efuse(mac, offset + i, &v);
if (status != HALMAC_RET_SUCCESS)
return -1;
data[i] = v;
}
return 0;
}
int rtl_halmac_write_logical_efuse(struct rtl_priv *rtlpriv, u32 offset,
u32 cnt, u8 *data)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
u32 i;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
for (i = 0; i < cnt; i++) {
status = api->halmac_write_logical_efuse(mac, offset + i,
data[i]);
if (status != HALMAC_RET_SUCCESS)
return -1;
}
return 0;
}
int rtl_halmac_set_mac_address(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
u8 port;
union halmac_wlan_addr hwa;
enum halmac_ret_status status;
int err = -1;
halmac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(halmac);
port = hwport;
memset(&hwa, 0, sizeof(hwa));
memcpy(hwa.address, addr, 6);
status = api->halmac_cfg_mac_addr(halmac, port, &hwa);
if (status != HALMAC_RET_SUCCESS)
goto out;
err = 0;
out:
return err;
}
int rtl_halmac_set_bssid(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
u8 port;
union halmac_wlan_addr hwa;
enum halmac_ret_status status;
int err = -1;
halmac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(halmac);
port = hwport;
memset(&hwa, 0, sizeof(union halmac_wlan_addr));
memcpy(hwa.address, addr, 6);
status = api->halmac_cfg_bssid(halmac, port, &hwa);
if (status != HALMAC_RET_SUCCESS)
goto out;
err = 0;
out:
return err;
}
int rtl_halmac_set_bandwidth(struct rtl_priv *rtlpriv, u8 channel,
u8 pri_ch_idx, u8 bw)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw);
if (status != HALMAC_RET_SUCCESS)
return -1;
return 0;
}
int rtl_halmac_get_hw_value(struct rtl_priv *rtlpriv, enum halmac_hw_id hw_id,
void *pvalue)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
status = api->halmac_get_hw_value(mac, hw_id, pvalue);
if (status != HALMAC_RET_SUCCESS)
return -1;
return 0;
}
int rtl_halmac_dump_fifo(struct rtl_priv *rtlpriv,
enum hal_fifo_sel halmac_fifo_sel)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
u8 *pfifo_map = NULL;
u32 fifo_size = 0;
s8 ret = 0;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel);
if (fifo_size)
pfifo_map = vmalloc(fifo_size);
if (!pfifo_map)
return -1;
status = api->halmac_dump_fifo(mac, halmac_fifo_sel, 0, fifo_size,
pfifo_map);
if (status != HALMAC_RET_SUCCESS) {
ret = -1;
goto _exit;
}
_exit:
if (pfifo_map)
vfree(pfifo_map);
return ret;
}
int rtl_halmac_rx_agg_switch(struct rtl_priv *rtlpriv, bool enable)
{
struct halmac_adapter *halmac;
struct halmac_api *api;
struct halmac_rxagg_cfg rxaggcfg;
enum halmac_ret_status status;
int err = -1;
halmac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(halmac);
memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg));
if (enable) {
/* enable RX agg. */
/* PCIE do nothing */
} else {
/* disable RX agg. */
rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
}
status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg);
if (status != HALMAC_RET_SUCCESS)
goto out;
err = 0;
out:
return err;
}
int rtl_halmac_get_wow_reason(struct rtl_priv *rtlpriv, u8 *reason)
{
u8 val8;
int err = -1;
val8 = rtl_read_byte(rtlpriv, 0x1C7);
if (val8 == 0xEA)
goto out;
*reason = val8;
err = 0;
out:
return err;
}
/*
* Description:
* Get RX driver info size. RX driver info is a small memory space between
* scriptor and RX payload.
*
* +-------------------------+
* | RX descriptor |
* | usually 24 bytes |
* +-------------------------+
* | RX driver info |
* | depends on driver cfg |
* +-------------------------+
* | RX paylad |
* | |
* +-------------------------+
*
* Parameter:
* d pointer to struct dvobj_priv of driver
* sz rx driver info size in bytes.
*
* Rteurn:
* 0 Success
* other Fail
*/
int rtl_halmac_get_drv_info_sz(struct rtl_priv *rtlpriv, u8 *sz)
{
/* enum halmac_ret_status status; */
u8 dw = 6; /* max number */
*sz = dw * 8;
return 0;
}
int rtl_halmac_get_rsvd_drv_pg_bndy(struct rtl_priv *rtlpriv, u16 *drv_pg)
{
enum halmac_ret_status status;
struct halmac_adapter *halmac = rtlpriv_to_halmac(rtlpriv);
struct halmac_api *api = HALMAC_GET_API(halmac);
status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY,
drv_pg);
if (status != HALMAC_RET_SUCCESS)
return -1;
return 0;
}
int rtl_halmac_chk_txdesc(struct rtl_priv *rtlpriv, u8 *txdesc, u32 size)
{
struct halmac_adapter *mac;
struct halmac_api *api;
enum halmac_ret_status status;
mac = rtlpriv_to_halmac(rtlpriv);
api = HALMAC_GET_API(mac);
status = api->halmac_chk_txdesc(mac, txdesc, size);
if (status != HALMAC_RET_SUCCESS)
return -1;
return 0;
}
MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
drivers/staging/rtlwifi/halmac/rtl_halmac.h 0 → 100644
View file @ 938a0447
/******************************************************************************
*
* Copyright(c) 2016 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef _RTL_HALMAC_H_
#define _RTL_HALMAC_H_
#include "halmac_api.h"
#define rtlpriv_to_halmac(priv) \
((struct halmac_adapter *)((priv)->halmac.internal))
/* for H2C cmd */
#define MAX_H2C_BOX_NUMS 4
#define MESSAGE_BOX_SIZE 4
#define EX_MESSAGE_BOX_SIZE 4
/* HALMAC API for Driver(HAL) */
int rtl_halmac_init_adapter(struct rtl_priv *rtlpriv);
int rtl_halmac_deinit_adapter(struct rtl_priv *rtlpriv);
int rtl_halmac_poweron(struct rtl_priv *rtlpriv);
int rtl_halmac_poweroff(struct rtl_priv *rtlpriv);
int rtl_halmac_init_hal(struct rtl_priv *rtlpriv);
int rtl_halmac_init_hal_fw(struct rtl_priv *rtlpriv, u8 *fw, u32 fwsize);
int rtl_halmac_init_hal_fw_file(struct rtl_priv *rtlpriv, u8 *fwpath);
int rtl_halmac_deinit_hal(struct rtl_priv *rtlpriv);
int rtl_halmac_self_verify(struct rtl_priv *rtlpriv);
int rtl_halmac_dlfw(struct rtl_priv *rtlpriv, u8 *fw, u32 fwsize);
int rtl_halmac_dlfw_from_file(struct rtl_priv *rtlpriv, u8 *fwpath);
int rtl_halmac_phy_power_switch(struct rtl_priv *rtlpriv, u8 enable);
int rtl_halmac_send_h2c(struct rtl_priv *rtlpriv, u8 *h2c);
int rtl_halmac_c2h_handle(struct rtl_priv *rtlpriv, u8 *c2h, u32 size);
int rtl_halmac_get_physical_efuse_size(struct rtl_priv *rtlpriv, u32 *size);
int rtl_halmac_read_physical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
u32 size);
int rtl_halmac_read_physical_efuse(struct rtl_priv *rtlpriv, u32 offset,
u32 cnt, u8 *data);
int rtl_halmac_write_physical_efuse(struct rtl_priv *rtlpriv, u32 offset,
u32 cnt, u8 *data);
int rtl_halmac_get_logical_efuse_size(struct rtl_priv *rtlpriv, u32 *size);
int rtl_halmac_read_logical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
u32 size);
int rtl_halmac_write_logical_efuse_map(struct rtl_priv *rtlpriv, u8 *map,
u32 size, u8 *maskmap, u32 masksize);
int rtl_halmac_read_logical_efuse(struct rtl_priv *rtlpriv, u32 offset, u32 cnt,
u8 *data);
int rtl_halmac_write_logical_efuse(struct rtl_priv *rtlpriv, u32 offset,
u32 cnt, u8 *data);
int rtl_halmac_config_rx_info(struct rtl_priv *rtlpriv, enum halmac_drv_info);
int rtl_halmac_set_mac_address(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr);
int rtl_halmac_set_bssid(struct rtl_priv *d, u8 hwport, u8 *addr);
int rtl_halmac_set_bandwidth(struct rtl_priv *rtlpriv, u8 channel,
u8 pri_ch_idx, u8 bw);
int rtl_halmac_rx_agg_switch(struct rtl_priv *rtlpriv, bool enable);
int rtl_halmac_get_hw_value(struct rtl_priv *d, enum halmac_hw_id hw_id,
void *pvalue);
int rtl_halmac_dump_fifo(struct rtl_priv *rtlpriv,
enum hal_fifo_sel halmac_fifo_sel);
int rtl_halmac_get_wow_reason(struct rtl_priv *rtlpriv, u8 *reason);
int rtl_halmac_get_drv_info_sz(struct rtl_priv *d, u8 *sz);
int rtl_halmac_get_rsvd_drv_pg_bndy(struct rtl_priv *dvobj, u16 *drv_pg);
int rtl_halmac_download_rsvd_page(struct rtl_priv *dvobj, u8 pg_offset,
u8 *pbuf, u32 size);
int rtl_halmac_chk_txdesc(struct rtl_priv *rtlpriv, u8 *txdesc, u32 size);
struct rtl_halmac_ops *rtl_halmac_get_ops_pointer(void);
#endif /* _RTL_HALMAC_H_ */
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