Commit 94f8dfc6 authored by Oscar Mateo's avatar Oscar Mateo Committed by Chris Wilson

drm/i915/selftests: Handle a potential failure of intel_ring_begin

Silence smatch over:

drivers/gpu/drm/i915/selftests/intel_workarounds.c:58 read_nonprivs() error: 'cs' dereferencing possible ERR_PTR()

by handling a potential (but unlikely) failure of intel_ring_begin.

Fixes: f4ecfbfc ("drm/i915: Check whitelist registers across resets")
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1523915821-30624-1-git-send-email-oscar.mateo@intel.com
parent 9f172f6f
...@@ -54,6 +54,11 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine) ...@@ -54,6 +54,11 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
srm++; srm++;
cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS); cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
if (IS_ERR(cs)) {
err = PTR_ERR(cs);
goto err_req;
}
for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) { for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
*cs++ = srm; *cs++ = srm;
*cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));
...@@ -75,6 +80,8 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine) ...@@ -75,6 +80,8 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
return result; return result;
err_req:
i915_request_add(rq);
err_pin: err_pin:
i915_vma_unpin(vma); i915_vma_unpin(vma);
err_obj: err_obj:
......
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