Commit 959dc258 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A collection of fixes from this week, it's been pretty quiet and
  nothing really stands out as particularly noteworthy here -- mostly
  minor fixes across the field:

   - ODROID booting was fixed due to PMIC interrupts missing in DT
   - a collection of i.MX fixes
   - minor Tegra fix for regulators
   - Rockchip fix and addition of SoC-specific mailing list to make it
     easier to find posted patches"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  bus: arm-ccn: Fix warning message
  ARM: shmobile: koelsch: Remove non-existent i2c6 pinmux
  ARM: tegra: apalis/colibri t30: fix on-module 5v0 supplies
  MAINTAINERS: add new Rockchip SoC list
  ARM: dts: rockchip: readd missing mmc0 pinctrl settings
  ARM: dts: ODROID i2c improvements
  ARM: dts: Enable PMIC interrupts on ODROID
  ARM: dts: imx6sx: fix the pad setting for uart CTS_B
  ARM: dts: i.MX53: fix apparent bug in VPU clks
  ARM: imx: correct gpu2d_axi and gpu3d_axi clock setting
  ARM: dts: imx6: edmqmx6: change enet reset pin
  ARM: dts: vf610-twr: Fix pinctrl_esdhc1 pin definitions.
  ARM: imx: remove unnecessary ARCH_HAS_OPP select
  ARM: imx: fix TLB missing of IOMUXC base address during suspend
  ARM: imx6: fix SMP compilation again
  ARM: dt: sun6i: Add #address-cells and #size-cells to i2c controller nodes
parents fa7f78e0 bf87bb12
...@@ -1277,6 +1277,7 @@ F: drivers/scsi/arm/ ...@@ -1277,6 +1277,7 @@ F: drivers/scsi/arm/
ARM/Rockchip SoC support ARM/Rockchip SoC support
M: Heiko Stuebner <heiko@sntech.de> M: Heiko Stuebner <heiko@sntech.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-rockchip@lists.infradead.org
S: Maintained S: Maintained
F: arch/arm/mach-rockchip/ F: arch/arm/mach-rockchip/
F: drivers/*/*rockchip* F: drivers/*/*rockchip*
......
...@@ -134,6 +134,8 @@ xusbxti { ...@@ -134,6 +134,8 @@ xusbxti {
i2c@13860000 { i2c@13860000 {
pinctrl-0 = <&i2c0_bus>; pinctrl-0 = <&i2c0_bus>;
pinctrl-names = "default"; pinctrl-names = "default";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
status = "okay"; status = "okay";
usb3503: usb3503@08 { usb3503: usb3503@08 {
...@@ -148,6 +150,10 @@ usb3503: usb3503@08 { ...@@ -148,6 +150,10 @@ usb3503: usb3503@08 {
max77686: pmic@09 { max77686: pmic@09 {
compatible = "maxim,max77686"; compatible = "maxim,max77686";
interrupt-parent = <&gpx3>;
interrupts = <2 0>;
pinctrl-names = "default";
pinctrl-0 = <&max77686_irq>;
reg = <0x09>; reg = <0x09>;
#clock-cells = <1>; #clock-cells = <1>;
...@@ -368,4 +374,11 @@ gpio_power_key: power_key { ...@@ -368,4 +374,11 @@ gpio_power_key: power_key {
samsung,pins = "gpx1-3"; samsung,pins = "gpx1-3";
samsung,pin-pud = <0>; samsung,pin-pud = <0>;
}; };
max77686_irq: max77686-irq {
samsung,pins = "gpx3-2";
samsung,pin-function = <0>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
}; };
...@@ -731,7 +731,7 @@ vpu: vpu@63ff4000 { ...@@ -731,7 +731,7 @@ vpu: vpu@63ff4000 {
compatible = "fsl,imx53-vpu"; compatible = "fsl,imx53-vpu";
reg = <0x63ff4000 0x1000>; reg = <0x63ff4000 0x1000>;
interrupts = <9>; interrupts = <9>;
clocks = <&clks IMX5_CLK_VPU_GATE>, clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
<&clks IMX5_CLK_VPU_GATE>; <&clks IMX5_CLK_VPU_GATE>;
clock-names = "per", "ahb"; clock-names = "per", "ahb";
resets = <&src 1>; resets = <&src 1>;
......
...@@ -119,7 +119,7 @@ &fec { ...@@ -119,7 +119,7 @@ &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>; phy-reset-gpios = <&gpio1 25 0>;
phy-supply = <&vgen2_1v2_eth>; phy-supply = <&vgen2_1v2_eth>;
status = "okay"; status = "okay";
}; };
...@@ -339,6 +339,7 @@ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 ...@@ -339,6 +339,7 @@ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>; >;
}; };
......
This diff is collapsed.
...@@ -275,11 +275,6 @@ msiof0_pins: spi1 { ...@@ -275,11 +275,6 @@ msiof0_pins: spi1 {
renesas,function = "msiof0"; renesas,function = "msiof0";
}; };
i2c6_pins: i2c6 {
renesas,groups = "i2c6";
renesas,function = "i2c6";
};
usb0_pins: usb0 { usb0_pins: usb0 {
renesas,groups = "usb0"; renesas,groups = "usb0";
renesas,function = "usb0"; renesas,function = "usb0";
...@@ -420,8 +415,6 @@ eeprom@50 { ...@@ -420,8 +415,6 @@ eeprom@50 {
}; };
&i2c6 { &i2c6 {
pinctrl-names = "default";
pinctrl-0 = <&i2c6_pins>;
status = "okay"; status = "okay";
clock-frequency = <100000>; clock-frequency = <100000>;
......
...@@ -149,6 +149,8 @@ vcc28_cif: regulator@12 { ...@@ -149,6 +149,8 @@ vcc28_cif: regulator@12 {
&mmc0 { /* sdmmc */ &mmc0 { /* sdmmc */
num-slots = <1>; num-slots = <1>;
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
vmmc-supply = <&vcc_sd0>; vmmc-supply = <&vcc_sd0>;
slot@0 { slot@0 {
......
...@@ -179,6 +179,8 @@ vcc28: REG12 { ...@@ -179,6 +179,8 @@ vcc28: REG12 {
&mmc0 { &mmc0 {
num-slots = <1>; num-slots = <1>;
status = "okay"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
vmmc-supply = <&vcc_sd0>; vmmc-supply = <&vcc_sd0>;
slot@0 { slot@0 {
......
...@@ -660,6 +660,8 @@ i2c0: i2c@01c2ac00 { ...@@ -660,6 +660,8 @@ i2c0: i2c@01c2ac00 {
clock-frequency = <100000>; clock-frequency = <100000>;
resets = <&apb2_rst 0>; resets = <&apb2_rst 0>;
status = "disabled"; status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
}; };
i2c1: i2c@01c2b000 { i2c1: i2c@01c2b000 {
...@@ -670,6 +672,8 @@ i2c1: i2c@01c2b000 { ...@@ -670,6 +672,8 @@ i2c1: i2c@01c2b000 {
clock-frequency = <100000>; clock-frequency = <100000>;
resets = <&apb2_rst 1>; resets = <&apb2_rst 1>;
status = "disabled"; status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
}; };
i2c2: i2c@01c2b400 { i2c2: i2c@01c2b400 {
...@@ -680,6 +684,8 @@ i2c2: i2c@01c2b400 { ...@@ -680,6 +684,8 @@ i2c2: i2c@01c2b400 {
clock-frequency = <100000>; clock-frequency = <100000>;
resets = <&apb2_rst 2>; resets = <&apb2_rst 2>;
status = "disabled"; status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
}; };
i2c3: i2c@01c2b800 { i2c3: i2c@01c2b800 {
...@@ -690,6 +696,8 @@ i2c3: i2c@01c2b800 { ...@@ -690,6 +696,8 @@ i2c3: i2c@01c2b800 {
clock-frequency = <100000>; clock-frequency = <100000>;
resets = <&apb2_rst 3>; resets = <&apb2_rst 3>;
status = "disabled"; status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
}; };
gmac: ethernet@01c30000 { gmac: ethernet@01c30000 {
......
...@@ -423,7 +423,7 @@ pmic: tps65911@2d { ...@@ -423,7 +423,7 @@ pmic: tps65911@2d {
vcc4-supply = <&sys_3v3_reg>; vcc4-supply = <&sys_3v3_reg>;
vcc5-supply = <&sys_3v3_reg>; vcc5-supply = <&sys_3v3_reg>;
vcc6-supply = <&vio_reg>; vcc6-supply = <&vio_reg>;
vcc7-supply = <&sys_5v0_reg>; vcc7-supply = <&charge_pump_5v0_reg>;
vccio-supply = <&sys_3v3_reg>; vccio-supply = <&sys_3v3_reg>;
regulators { regulators {
...@@ -674,5 +674,14 @@ sys_3v3_reg: regulator@100 { ...@@ -674,5 +674,14 @@ sys_3v3_reg: regulator@100 {
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-always-on; regulator-always-on;
}; };
charge_pump_5v0_reg: regulator@101 {
compatible = "regulator-fixed";
reg = <101>;
regulator-name = "5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
}; };
}; };
...@@ -201,7 +201,7 @@ pmic: tps65911@2d { ...@@ -201,7 +201,7 @@ pmic: tps65911@2d {
vcc4-supply = <&sys_3v3_reg>; vcc4-supply = <&sys_3v3_reg>;
vcc5-supply = <&sys_3v3_reg>; vcc5-supply = <&sys_3v3_reg>;
vcc6-supply = <&vio_reg>; vcc6-supply = <&vio_reg>;
vcc7-supply = <&sys_5v0_reg>; vcc7-supply = <&charge_pump_5v0_reg>;
vccio-supply = <&sys_3v3_reg>; vccio-supply = <&sys_3v3_reg>;
regulators { regulators {
...@@ -373,5 +373,14 @@ sys_3v3_reg: regulator@100 { ...@@ -373,5 +373,14 @@ sys_3v3_reg: regulator@100 {
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-always-on; regulator-always-on;
}; };
charge_pump_5v0_reg: regulator@101 {
compatible = "regulator-fixed";
reg = <101>;
regulator-name = "5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
}; };
}; };
...@@ -168,7 +168,7 @@ VF610_PAD_PTB22__DSPI0_SCK 0x1182 ...@@ -168,7 +168,7 @@ VF610_PAD_PTB22__DSPI0_SCK 0x1182
}; };
pinctrl_esdhc1: esdhc1grp { pinctrl_esdhc1: esdhc1grp {
fsl,fsl,pins = < fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
......
...@@ -85,7 +85,6 @@ config SOC_IMX25 ...@@ -85,7 +85,6 @@ config SOC_IMX25
config SOC_IMX27 config SOC_IMX27
bool bool
select ARCH_HAS_OPP
select CPU_ARM926T select CPU_ARM926T
select IMX_HAVE_IOMUX_V1 select IMX_HAVE_IOMUX_V1
select MXC_AVIC select MXC_AVIC
...@@ -659,7 +658,6 @@ comment "Device tree only" ...@@ -659,7 +658,6 @@ comment "Device tree only"
config SOC_IMX5 config SOC_IMX5
bool bool
select ARCH_HAS_OPP
select HAVE_IMX_SRC select HAVE_IMX_SRC
select MXC_TZIC select MXC_TZIC
......
...@@ -93,9 +93,11 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o ...@@ -93,9 +93,11 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o
ifdef CONFIG_SOC_IMX6
AFLAGS_headsmp.o :=-Wa,-march=armv7-a AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
endif
obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
......
...@@ -194,6 +194,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -194,6 +194,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
if (cpu_is_imx6dl()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
}
clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
...@@ -217,8 +221,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -217,8 +221,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
if (cpu_is_imx6q()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
}
clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
......
...@@ -173,6 +173,8 @@ ENTRY(imx6_suspend) ...@@ -173,6 +173,8 @@ ENTRY(imx6_suspend)
ldr r6, [r11, #0x0] ldr r6, [r11, #0x0]
ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
ldr r6, [r11, #0x0] ldr r6, [r11, #0x0]
ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
ldr r6, [r11, #0x0]
/* use r11 to store the IO address */ /* use r11 to store the IO address */
ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
......
...@@ -662,7 +662,7 @@ static int arm_ccn_pmu_event_init(struct perf_event *event) ...@@ -662,7 +662,7 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
} }
if (e->num_vcs && vc >= e->num_vcs) { if (e->num_vcs && vc >= e->num_vcs) {
dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n", dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n",
port, node_xp); vc, node_xp);
return -EINVAL; return -EINVAL;
} }
valid = 1; valid = 1;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment