Commit 9782979e authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'samsung-dt-4.10-2' of...

Merge tag 'samsung-dt-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Pull "Samsung DeviceTree second update for v4.10" from Krzysztof Kozłowski:

1. Cleanups in MSHC nodes.
2. Enable ADC on Odroid boards.
3. Fix interrupt flags on recently added DMA sound nodes in Exynos5410.

* tag 'samsung-dt-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: Remove the cd-gpios property for eMMC of Odroid XU3/4
  ARM: dts: exynos: Specify snps, dwmac in compatible string for gmac
  ARM: dts: exynos: Fix invalid GIC interrupt flags in audio block of Exynos5410
  ARM: dts: exynos: Add ADCs on 4412 and 5422 based odroid boards.
  ARM: dts: exynos: Replace "clock-freq-min-max" with "max-frequency"
parents bb986384 79700041
...@@ -28,7 +28,7 @@ &mshc_2 { ...@@ -28,7 +28,7 @@ &mshc_2 {
vqmmc-supply = <&ldo3_reg>; vqmmc-supply = <&ldo3_reg>;
card-detect-delay = <200>; card-detect-delay = <200>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
clock-freq-min-max = <400000 100000000>; max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>; samsung,dw-mshc-ddr-timing = <1 2>;
......
...@@ -310,7 +310,7 @@ &mshc_0 { ...@@ -310,7 +310,7 @@ &mshc_0 {
card-detect-delay = <200>; card-detect-delay = <200>;
vmmc-supply = <&ldo12_reg>; vmmc-supply = <&ldo12_reg>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
clock-freq-min-max = <400000 100000000>; max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>; samsung,dw-mshc-ddr-timing = <1 2>;
......
...@@ -435,7 +435,7 @@ &mshc_0 { ...@@ -435,7 +435,7 @@ &mshc_0 {
card-detect-delay = <200>; card-detect-delay = <200>;
vmmc-supply = <&vemmc_reg>; vmmc-supply = <&vemmc_reg>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
clock-freq-min-max = <400000 100000000>; max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>; samsung,dw-mshc-ddr-timing = <1 2>;
......
...@@ -649,7 +649,7 @@ &mshc_0 { ...@@ -649,7 +649,7 @@ &mshc_0 {
card-detect-delay = <200>; card-detect-delay = <200>;
vmmc-supply = <&ldo12_reg>; vmmc-supply = <&ldo12_reg>;
clock-frequency = <100000000>; clock-frequency = <100000000>;
clock-freq-min-max = <400000 100000000>; max-frequency = <100000000>;
samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-ciu-div = <1>;
samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-sdr-timing = <0 1>;
samsung,dw-mshc-ddr-timing = <1 2>; samsung,dw-mshc-ddr-timing = <1 2>;
......
...@@ -64,6 +64,11 @@ regulator_p3v3 { ...@@ -64,6 +64,11 @@ regulator_p3v3 {
}; };
}; };
&adc {
vdd-supply = <&ldo10_reg>;
status = "okay";
};
/* VDDQ for MSHC (eMMC card) */ /* VDDQ for MSHC (eMMC card) */
&buck8_reg { &buck8_reg {
regulator-name = "BUCK8_VDDQ_MMC4_2.8V"; regulator-name = "BUCK8_VDDQ_MMC4_2.8V";
......
...@@ -203,7 +203,7 @@ amba { ...@@ -203,7 +203,7 @@ amba {
pdma0: pdma@12680000 { pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>; reg = <0x121A0000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>; clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
...@@ -214,7 +214,7 @@ pdma0: pdma@12680000 { ...@@ -214,7 +214,7 @@ pdma0: pdma@12680000 {
pdma1: pdma@12690000 { pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>; reg = <0x121B0000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>; clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
......
...@@ -147,6 +147,11 @@ map6 { ...@@ -147,6 +147,11 @@ map6 {
}; };
}; };
&adc {
vdd-supply = <&ldo4_reg>;
status = "okay";
};
&bus_wcore { &bus_wcore {
devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>, devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
<&nocp_mem1_0>, <&nocp_mem1_1>; <&nocp_mem1_0>, <&nocp_mem1_1>;
...@@ -293,6 +298,12 @@ ldo3_reg: LDO3 { ...@@ -293,6 +298,12 @@ ldo3_reg: LDO3 {
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
}; };
ldo4_reg: LDO4 {
regulator-name = "vdd_adc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo5_reg: LDO5 { ldo5_reg: LDO5 {
regulator-name = "vdd_ldo5"; regulator-name = "vdd_ldo5";
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
...@@ -499,7 +510,6 @@ hdmiddc@50 { ...@@ -499,7 +510,6 @@ hdmiddc@50 {
&mmc_0 { &mmc_0 {
status = "okay"; status = "okay";
mmc-pwrseq = <&emmc_pwrseq>; mmc-pwrseq = <&emmc_pwrseq>;
cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
card-detect-delay = <200>; card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-sdr-timing = <0 4>;
......
...@@ -197,7 +197,7 @@ watchdog@110000 { ...@@ -197,7 +197,7 @@ watchdog@110000 {
}; };
gmac: ethernet@00230000 { gmac: ethernet@00230000 {
compatible = "snps,dwmac-3.70a"; compatible = "snps,dwmac-3.70a", "snps,dwmac";
reg = <0x00230000 0x8000>; reg = <0x00230000 0x8000>;
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 31 4>; interrupts = <GIC_SPI 31 4>;
......
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