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Kirill Smelkov
linux
Commits
97af71fa
Commit
97af71fa
authored
Mar 03, 2014
by
Ben Skeggs
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
drm/gf100-/gr: split gpc state into its subunits
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
c33b1e8c
Changes
19
Hide whitespace changes
Inline
Side-by-side
Showing
19 changed files
with
348 additions
and
348 deletions
+348
-348
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
+30
-11
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+45
-3
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h
+17
-0
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
+14
-34
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
+9
-38
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
+9
-36
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
+25
-16
drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
+14
-31
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
+15
-37
drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
+15
-25
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+50
-2
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+16
-2
drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
+21
-15
drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c
drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c
+9
-1
drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
+9
-29
drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
+9
-1
drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
+20
-18
drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
+10
-24
drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
+11
-25
No files found.
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
View file @
97af71fa
...
@@ -382,8 +382,7 @@ nv108_grctx_pack_hub[] = {
...
@@ -382,8 +382,7 @@ nv108_grctx_pack_hub[] = {
};
};
static
const
struct
nvc0_graph_init
static
const
struct
nvc0_graph_init
nv108_grctx_init_gpc_0
[]
=
{
nv108_grctx_init_prop_0
[]
=
{
{
0x418380
,
1
,
0x04
,
0x00000016
},
{
0x418400
,
1
,
0x04
,
0x38005e00
},
{
0x418400
,
1
,
0x04
,
0x38005e00
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x41840c
,
1
,
0x04
,
0x00001008
},
{
0x41840c
,
1
,
0x04
,
0x00001008
},
...
@@ -392,11 +391,21 @@ nv108_grctx_init_gpc_0[] = {
...
@@ -392,11 +391,21 @@ nv108_grctx_init_gpc_0[] = {
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{}
};
static
const
struct
nvc0_graph_init
nv108_grctx_init_gpc_unk_1
[]
=
{
{
0x418600
,
1
,
0x04
,
0x0000007f
},
{
0x418600
,
1
,
0x04
,
0x0000007f
},
{
0x418684
,
1
,
0x04
,
0x0000001f
},
{
0x418684
,
1
,
0x04
,
0x0000001f
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
{
0x418704
,
2
,
0x04
,
0x00000080
},
{
0x418704
,
2
,
0x04
,
0x00000080
},
{
0x41870c
,
2
,
0x04
,
0x00000000
},
{
0x41870c
,
2
,
0x04
,
0x00000000
},
{}
};
static
const
struct
nvc0_graph_init
nv108_grctx_init_setup_0
[]
=
{
{
0x418800
,
1
,
0x04
,
0x7006863a
},
{
0x418800
,
1
,
0x04
,
0x7006863a
},
{
0x418808
,
1
,
0x04
,
0x00000000
},
{
0x418808
,
1
,
0x04
,
0x00000000
},
{
0x41880c
,
1
,
0x04
,
0x00000030
},
{
0x41880c
,
1
,
0x04
,
0x00000030
},
...
@@ -407,10 +416,11 @@ nv108_grctx_init_gpc_0[] = {
...
@@ -407,10 +416,11 @@ nv108_grctx_init_gpc_0[] = {
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188fc
,
1
,
0x04
,
0x20100058
},
{
0x4188fc
,
1
,
0x04
,
0x20100058
},
{
0x41891c
,
1
,
0x04
,
0x00ff00ff
},
{}
{
0x418924
,
1
,
0x04
,
0x00000000
},
};
{
0x418928
,
1
,
0x04
,
0x00ffff00
},
{
0x41892c
,
1
,
0x04
,
0x0000ff00
},
static
const
struct
nvc0_graph_init
nv108_grctx_init_crstr_0
[]
=
{
{
0x418b00
,
1
,
0x04
,
0x0000001e
},
{
0x418b00
,
1
,
0x04
,
0x0000001e
},
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
...
@@ -419,22 +429,31 @@ nv108_grctx_init_gpc_0[] = {
...
@@ -419,22 +429,31 @@ nv108_grctx_init_gpc_0[] = {
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{}
};
static
const
struct
nvc0_graph_init
nv108_grctx_init_gpm_0
[]
=
{
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c40
,
1
,
0x04
,
0xffffffff
},
{
0x418c40
,
1
,
0x04
,
0xffffffff
},
{
0x418c6c
,
1
,
0x04
,
0x00000001
},
{
0x418c6c
,
1
,
0x04
,
0x00000001
},
{
0x418c80
,
1
,
0x04
,
0x2020000c
},
{
0x418c80
,
1
,
0x04
,
0x2020000c
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x418d24
,
1
,
0x04
,
0x00000000
},
{
0x419000
,
1
,
0x04
,
0x00000780
},
{
0x419004
,
2
,
0x04
,
0x00000000
},
{
0x419014
,
1
,
0x04
,
0x00000004
},
{}
{}
};
};
static
const
struct
nvc0_graph_pack
static
const
struct
nvc0_graph_pack
nv108_grctx_pack_gpc
[]
=
{
nv108_grctx_pack_gpc
[]
=
{
{
nv108_grctx_init_gpc_0
},
{
nvc0_grctx_init_gpc_unk_0
},
{
nv108_grctx_init_prop_0
},
{
nv108_grctx_init_gpc_unk_1
},
{
nv108_grctx_init_setup_0
},
{
nvc0_grctx_init_zcull_0
},
{
nv108_grctx_init_crstr_0
},
{
nv108_grctx_init_gpm_0
},
{
nvf0_grctx_init_gpc_unk_2
},
{
nvc0_grctx_init_gcc_0
},
{}
{}
};
};
...
...
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
View file @
97af71fa
...
@@ -762,9 +762,14 @@ nvc0_grctx_pack_hub[] = {
...
@@ -762,9 +762,14 @@ nvc0_grctx_pack_hub[] = {
{}
{}
};
};
static
const
struct
nvc0_graph_init
const
struct
nvc0_graph_init
nvc0_grctx_init_gpc_0
[]
=
{
nvc0_grctx_init_gpc_
unk_
0
[]
=
{
{
0x418380
,
1
,
0x04
,
0x00000016
},
{
0x418380
,
1
,
0x04
,
0x00000016
},
{}
};
const
struct
nvc0_graph_init
nvc0_grctx_init_prop_0
[]
=
{
{
0x418400
,
1
,
0x04
,
0x38004e00
},
{
0x418400
,
1
,
0x04
,
0x38004e00
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x418408
,
1
,
0x04
,
0x00000000
},
{
0x418408
,
1
,
0x04
,
0x00000000
},
...
@@ -774,6 +779,11 @@ nvc0_grctx_init_gpc_0[] = {
...
@@ -774,6 +779,11 @@ nvc0_grctx_init_gpc_0[] = {
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{}
};
const
struct
nvc0_graph_init
nvc0_grctx_init_gpc_unk_1
[]
=
{
{
0x418600
,
1
,
0x04
,
0x0000001f
},
{
0x418600
,
1
,
0x04
,
0x0000001f
},
{
0x418684
,
1
,
0x04
,
0x0000000f
},
{
0x418684
,
1
,
0x04
,
0x0000000f
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
...
@@ -781,6 +791,11 @@ nvc0_grctx_init_gpc_0[] = {
...
@@ -781,6 +791,11 @@ nvc0_grctx_init_gpc_0[] = {
{
0x418708
,
1
,
0x04
,
0x00000000
},
{
0x418708
,
1
,
0x04
,
0x00000000
},
{
0x41870c
,
1
,
0x04
,
0x07c80000
},
{
0x41870c
,
1
,
0x04
,
0x07c80000
},
{
0x418710
,
1
,
0x04
,
0x00000000
},
{
0x418710
,
1
,
0x04
,
0x00000000
},
{}
};
static
const
struct
nvc0_graph_init
nvc0_grctx_init_setup_0
[]
=
{
{
0x418800
,
1
,
0x04
,
0x0006860a
},
{
0x418800
,
1
,
0x04
,
0x0006860a
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418828
,
1
,
0x04
,
0x00008442
},
{
0x418828
,
1
,
0x04
,
0x00008442
},
...
@@ -789,10 +804,20 @@ nvc0_grctx_init_gpc_0[] = {
...
@@ -789,10 +804,20 @@ nvc0_grctx_init_gpc_0[] = {
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188fc
,
1
,
0x04
,
0x00100000
},
{
0x4188fc
,
1
,
0x04
,
0x00100000
},
{}
};
const
struct
nvc0_graph_init
nvc0_grctx_init_zcull_0
[]
=
{
{
0x41891c
,
1
,
0x04
,
0x00ff00ff
},
{
0x41891c
,
1
,
0x04
,
0x00ff00ff
},
{
0x418924
,
1
,
0x04
,
0x00000000
},
{
0x418924
,
1
,
0x04
,
0x00000000
},
{
0x418928
,
1
,
0x04
,
0x00ffff00
},
{
0x418928
,
1
,
0x04
,
0x00ffff00
},
{
0x41892c
,
1
,
0x04
,
0x0000ff00
},
{
0x41892c
,
1
,
0x04
,
0x0000ff00
},
{}
};
const
struct
nvc0_graph_init
nvc0_grctx_init_crstr_0
[]
=
{
{
0x418b00
,
1
,
0x04
,
0x00000000
},
{
0x418b00
,
1
,
0x04
,
0x00000000
},
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
...
@@ -801,10 +826,20 @@ nvc0_grctx_init_gpc_0[] = {
...
@@ -801,10 +826,20 @@ nvc0_grctx_init_gpc_0[] = {
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{}
};
const
struct
nvc0_graph_init
nvc0_grctx_init_gpm_0
[]
=
{
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c80
,
1
,
0x04
,
0x20200004
},
{
0x418c80
,
1
,
0x04
,
0x20200004
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{}
};
const
struct
nvc0_graph_init
nvc0_grctx_init_gcc_0
[]
=
{
{
0x419000
,
1
,
0x04
,
0x00000780
},
{
0x419000
,
1
,
0x04
,
0x00000780
},
{
0x419004
,
2
,
0x04
,
0x00000000
},
{
0x419004
,
2
,
0x04
,
0x00000000
},
{
0x419014
,
1
,
0x04
,
0x00000004
},
{
0x419014
,
1
,
0x04
,
0x00000004
},
...
@@ -813,7 +848,14 @@ nvc0_grctx_init_gpc_0[] = {
...
@@ -813,7 +848,14 @@ nvc0_grctx_init_gpc_0[] = {
const
struct
nvc0_graph_pack
const
struct
nvc0_graph_pack
nvc0_grctx_pack_gpc
[]
=
{
nvc0_grctx_pack_gpc
[]
=
{
{
nvc0_grctx_init_gpc_0
},
{
nvc0_grctx_init_gpc_unk_0
},
{
nvc0_grctx_init_prop_0
},
{
nvc0_grctx_init_gpc_unk_1
},
{
nvc0_grctx_init_setup_0
},
{
nvc0_grctx_init_zcull_0
},
{
nvc0_grctx_init_crstr_0
},
{
nvc0_grctx_init_gpm_0
},
{
nvc0_grctx_init_gcc_0
},
{}
{}
};
};
...
...
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h
View file @
97af71fa
...
@@ -94,6 +94,13 @@ extern const struct nvc0_graph_init nvc0_grctx_init_rstr2d_0[];
...
@@ -94,6 +94,13 @@ extern const struct nvc0_graph_init nvc0_grctx_init_rstr2d_0[];
extern
const
struct
nvc0_graph_init
nvc0_grctx_init_scc_0
[];
extern
const
struct
nvc0_graph_init
nvc0_grctx_init_scc_0
[];
extern
const
struct
nvc0_graph_pack
nvc0_grctx_pack_gpc
[];
extern
const
struct
nvc0_graph_pack
nvc0_grctx_pack_gpc
[];
extern
const
struct
nvc0_graph_init
nvc0_grctx_init_gpc_unk_0
[];
extern
const
struct
nvc0_graph_init
nvc0_grctx_init_prop_0
[];
extern
const
struct
nvc0_graph_init
nvc0_grctx_init_gpc_unk_1
[];
extern
const
struct
nvc0_graph_init
nvc0_grctx_init_zcull_0
[];
extern
const
struct
nvc0_graph_init
nvc0_grctx_init_crstr_0
[];
extern
const
struct
nvc0_graph_init
nvc0_grctx_init_gpm_0
[];
extern
const
struct
nvc0_graph_init
nvc0_grctx_init_gcc_0
[];
extern
const
struct
nvc0_graph_pack
nvc0_grctx_pack_zcull
[];
extern
const
struct
nvc0_graph_pack
nvc0_grctx_pack_zcull
[];
...
@@ -101,6 +108,8 @@ extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[];
...
@@ -101,6 +108,8 @@ extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[];
extern
const
struct
nvc0_graph_init
nvc1_grctx_init_9097_0
[];
extern
const
struct
nvc0_graph_init
nvc1_grctx_init_9097_0
[];
extern
const
struct
nvc0_graph_init
nvc1_grctx_init_gpm_0
[];
extern
const
struct
nvc0_graph_init
nvc8_grctx_init_9197_0
[];
extern
const
struct
nvc0_graph_init
nvc8_grctx_init_9197_0
[];
extern
const
struct
nvc0_graph_init
nvc8_grctx_init_9297_0
[];
extern
const
struct
nvc0_graph_init
nvc8_grctx_init_9297_0
[];
...
@@ -111,14 +120,22 @@ extern const struct nvc0_graph_pack nvd9_grctx_pack_mthd[];
...
@@ -111,14 +120,22 @@ extern const struct nvc0_graph_pack nvd9_grctx_pack_mthd[];
extern
const
struct
nvc0_graph_init
nvd9_grctx_init_fe_0
[];
extern
const
struct
nvc0_graph_init
nvd9_grctx_init_fe_0
[];
extern
const
struct
nvc0_graph_init
nvd9_grctx_init_be_0
[];
extern
const
struct
nvc0_graph_init
nvd9_grctx_init_be_0
[];
extern
const
struct
nvc0_graph_init
nvd9_grctx_init_prop_0
[];
extern
const
struct
nvc0_graph_init
nvd9_grctx_init_gpc_unk_1
[];
extern
const
struct
nvc0_graph_init
nvd9_grctx_init_crstr_0
[];
extern
const
struct
nvc0_graph_init
nve4_grctx_init_memfmt_0
[];
extern
const
struct
nvc0_graph_init
nve4_grctx_init_memfmt_0
[];
extern
const
struct
nvc0_graph_init
nve4_grctx_init_ds_0
[];
extern
const
struct
nvc0_graph_init
nve4_grctx_init_ds_0
[];
extern
const
struct
nvc0_graph_init
nve4_grctx_init_scc_0
[];
extern
const
struct
nvc0_graph_init
nve4_grctx_init_scc_0
[];
extern
const
struct
nvc0_graph_init
nve4_grctx_init_gpm_0
[];
extern
const
struct
nvc0_graph_pack
nvf0_grctx_pack_mthd
[];
extern
const
struct
nvc0_graph_pack
nvf0_grctx_pack_mthd
[];
extern
const
struct
nvc0_graph_init
nvf0_grctx_init_pri_0
[];
extern
const
struct
nvc0_graph_init
nvf0_grctx_init_pri_0
[];
extern
const
struct
nvc0_graph_init
nvf0_grctx_init_cwd_0
[];
extern
const
struct
nvc0_graph_init
nvf0_grctx_init_cwd_0
[];
extern
const
struct
nvc0_graph_init
nvf0_grctx_init_gpc_unk_2
[];
#endif
#endif
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
View file @
97af71fa
...
@@ -643,24 +643,7 @@ nvc1_grctx_pack_hub[] = {
...
@@ -643,24 +643,7 @@ nvc1_grctx_pack_hub[] = {
};
};
static
const
struct
nvc0_graph_init
static
const
struct
nvc0_graph_init
nvc1_grctx_init_gpc_0
[]
=
{
nvc1_grctx_init_setup_0
[]
=
{
{
0x418380
,
1
,
0x04
,
0x00000016
},
{
0x418400
,
1
,
0x04
,
0x38004e00
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x418408
,
1
,
0x04
,
0x00000000
},
{
0x41840c
,
1
,
0x04
,
0x00001008
},
{
0x418410
,
1
,
0x04
,
0x0fff0fff
},
{
0x418414
,
1
,
0x04
,
0x00200fff
},
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{
0x418600
,
1
,
0x04
,
0x0000001f
},
{
0x418684
,
1
,
0x04
,
0x0000000f
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
{
0x418704
,
1
,
0x04
,
0x00000080
},
{
0x418708
,
1
,
0x04
,
0x00000000
},
{
0x41870c
,
1
,
0x04
,
0x07c80000
},
{
0x418710
,
1
,
0x04
,
0x00000000
},
{
0x418800
,
1
,
0x04
,
0x0006860a
},
{
0x418800
,
1
,
0x04
,
0x0006860a
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418828
,
1
,
0x04
,
0x00008442
},
{
0x418828
,
1
,
0x04
,
0x00008442
},
...
@@ -669,32 +652,29 @@ nvc1_grctx_init_gpc_0[] = {
...
@@ -669,32 +652,29 @@ nvc1_grctx_init_gpc_0[] = {
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188fc
,
1
,
0x04
,
0x00100018
},
{
0x4188fc
,
1
,
0x04
,
0x00100018
},
{
0x41891c
,
1
,
0x04
,
0x00ff00ff
},
{}
{
0x418924
,
1
,
0x04
,
0x00000000
},
};
{
0x418928
,
1
,
0x04
,
0x00ffff00
},
{
0x41892c
,
1
,
0x04
,
0x0000ff00
},
const
struct
nvc0_graph_init
{
0x418b00
,
1
,
0x04
,
0x00000000
},
nvc1_grctx_init_gpm_0
[]
=
{
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
{
0x418b10
,
1
,
0x04
,
0x020398a4
},
{
0x418b14
,
1
,
0x04
,
0x0e629062
},
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c6c
,
1
,
0x04
,
0x00000001
},
{
0x418c6c
,
1
,
0x04
,
0x00000001
},
{
0x418c80
,
1
,
0x04
,
0x20200004
},
{
0x418c80
,
1
,
0x04
,
0x20200004
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x419000
,
1
,
0x04
,
0x00000780
},
{
0x419004
,
2
,
0x04
,
0x00000000
},
{
0x419014
,
1
,
0x04
,
0x00000004
},
{}
{}
};
};
static
const
struct
nvc0_graph_pack
static
const
struct
nvc0_graph_pack
nvc1_grctx_pack_gpc
[]
=
{
nvc1_grctx_pack_gpc
[]
=
{
{
nvc1_grctx_init_gpc_0
},
{
nvc0_grctx_init_gpc_unk_0
},
{
nvc0_grctx_init_prop_0
},
{
nvc0_grctx_init_gpc_unk_1
},
{
nvc1_grctx_init_setup_0
},
{
nvc0_grctx_init_zcull_0
},
{
nvc0_grctx_init_crstr_0
},
{
nvc1_grctx_init_gpm_0
},
{
nvc0_grctx_init_gcc_0
},
{}
{}
};
};
...
...
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
View file @
97af71fa
...
@@ -302,24 +302,7 @@ nvc8_grctx_pack_mthd[] = {
...
@@ -302,24 +302,7 @@ nvc8_grctx_pack_mthd[] = {
};
};
static
const
struct
nvc0_graph_init
static
const
struct
nvc0_graph_init
nvc8_grctx_init_gpc_0
[]
=
{
nvc8_grctx_init_setup_0
[]
=
{
{
0x418380
,
1
,
0x04
,
0x00000016
},
{
0x418400
,
1
,
0x04
,
0x38004e00
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x418408
,
1
,
0x04
,
0x00000000
},
{
0x41840c
,
1
,
0x04
,
0x00001008
},
{
0x418410
,
1
,
0x04
,
0x0fff0fff
},
{
0x418414
,
1
,
0x04
,
0x00200fff
},
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{
0x418600
,
1
,
0x04
,
0x0000001f
},
{
0x418684
,
1
,
0x04
,
0x0000000f
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
{
0x418704
,
1
,
0x04
,
0x00000080
},
{
0x418708
,
1
,
0x04
,
0x00000000
},
{
0x41870c
,
1
,
0x04
,
0x07c80000
},
{
0x418710
,
1
,
0x04
,
0x00000000
},
{
0x418800
,
1
,
0x04
,
0x0006860a
},
{
0x418800
,
1
,
0x04
,
0x0006860a
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418828
,
1
,
0x04
,
0x00008442
},
{
0x418828
,
1
,
0x04
,
0x00008442
},
...
@@ -328,31 +311,19 @@ nvc8_grctx_init_gpc_0[] = {
...
@@ -328,31 +311,19 @@ nvc8_grctx_init_gpc_0[] = {
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188fc
,
1
,
0x04
,
0x20100000
},
{
0x4188fc
,
1
,
0x04
,
0x20100000
},
{
0x41891c
,
1
,
0x04
,
0x00ff00ff
},
{
0x418924
,
1
,
0x04
,
0x00000000
},
{
0x418928
,
1
,
0x04
,
0x00ffff00
},
{
0x41892c
,
1
,
0x04
,
0x0000ff00
},
{
0x418b00
,
1
,
0x04
,
0x00000000
},
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
{
0x418b10
,
1
,
0x04
,
0x020398a4
},
{
0x418b14
,
1
,
0x04
,
0x0e629062
},
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c80
,
1
,
0x04
,
0x20200004
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x419000
,
1
,
0x04
,
0x00000780
},
{
0x419004
,
2
,
0x04
,
0x00000000
},
{
0x419014
,
1
,
0x04
,
0x00000004
},
{}
{}
};
};
static
const
struct
nvc0_graph_pack
static
const
struct
nvc0_graph_pack
nvc8_grctx_pack_gpc
[]
=
{
nvc8_grctx_pack_gpc
[]
=
{
{
nvc8_grctx_init_gpc_0
},
{
nvc0_grctx_init_gpc_unk_0
},
{
nvc0_grctx_init_prop_0
},
{
nvc0_grctx_init_gpc_unk_1
},
{
nvc8_grctx_init_setup_0
},
{
nvc0_grctx_init_zcull_0
},
{
nvc0_grctx_init_crstr_0
},
{
nvc0_grctx_init_gpm_0
},
{
nvc0_grctx_init_gcc_0
},
{}
{}
};
};
...
...
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
View file @
97af71fa
...
@@ -69,21 +69,7 @@ nvd7_grctx_pack_hub[] = {
...
@@ -69,21 +69,7 @@ nvd7_grctx_pack_hub[] = {
};
};
static
const
struct
nvc0_graph_init
static
const
struct
nvc0_graph_init
nvd7_grctx_init_gpc_0
[]
=
{
nvd7_grctx_init_setup_0
[]
=
{
{
0x418380
,
1
,
0x04
,
0x00000016
},
{
0x418400
,
1
,
0x04
,
0x38004e00
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x41840c
,
1
,
0x04
,
0x00001008
},
{
0x418410
,
1
,
0x04
,
0x0fff0fff
},
{
0x418414
,
1
,
0x04
,
0x02200fff
},
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{
0x418600
,
1
,
0x04
,
0x0000001f
},
{
0x418684
,
1
,
0x04
,
0x0000000f
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
{
0x418704
,
1
,
0x04
,
0x00000080
},
{
0x418708
,
3
,
0x04
,
0x00000000
},
{
0x418800
,
1
,
0x04
,
0x7006860a
},
{
0x418800
,
1
,
0x04
,
0x7006860a
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418828
,
1
,
0x04
,
0x00008442
},
{
0x418828
,
1
,
0x04
,
0x00008442
},
...
@@ -92,32 +78,19 @@ nvd7_grctx_init_gpc_0[] = {
...
@@ -92,32 +78,19 @@ nvd7_grctx_init_gpc_0[] = {
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188fc
,
1
,
0x04
,
0x20100018
},
{
0x4188fc
,
1
,
0x04
,
0x20100018
},
{
0x41891c
,
1
,
0x04
,
0x00ff00ff
},
{
0x418924
,
1
,
0x04
,
0x00000000
},
{
0x418928
,
1
,
0x04
,
0x00ffff00
},
{
0x41892c
,
1
,
0x04
,
0x0000ff00
},
{
0x418b00
,
1
,
0x04
,
0x00000006
},
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
{
0x418b10
,
1
,
0x04
,
0x020398a4
},
{
0x418b14
,
1
,
0x04
,
0x0e629062
},
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c6c
,
1
,
0x04
,
0x00000001
},
{
0x418c80
,
1
,
0x04
,
0x20200004
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x419000
,
1
,
0x04
,
0x00000780
},
{
0x419004
,
2
,
0x04
,
0x00000000
},
{
0x419014
,
1
,
0x04
,
0x00000004
},
{}
{}
};
};
static
const
struct
nvc0_graph_pack
static
const
struct
nvc0_graph_pack
nvd7_grctx_pack_gpc
[]
=
{
nvd7_grctx_pack_gpc
[]
=
{
{
nvd7_grctx_init_gpc_0
},
{
nvc0_grctx_init_gpc_unk_0
},
{
nvd9_grctx_init_prop_0
},
{
nvd9_grctx_init_gpc_unk_1
},
{
nvd7_grctx_init_setup_0
},
{
nvc0_grctx_init_zcull_0
},
{
nvd9_grctx_init_crstr_0
},
{
nvc1_grctx_init_gpm_0
},
{
nvc0_grctx_init_gcc_0
},
{}
{}
};
};
...
...
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
View file @
97af71fa
...
@@ -382,9 +382,8 @@ nvd9_grctx_pack_hub[] = {
...
@@ -382,9 +382,8 @@ nvd9_grctx_pack_hub[] = {
{}
{}
};
};
static
const
struct
nvc0_graph_init
const
struct
nvc0_graph_init
nvd9_grctx_init_gpc_0
[]
=
{
nvd9_grctx_init_prop_0
[]
=
{
{
0x418380
,
1
,
0x04
,
0x00000016
},
{
0x418400
,
1
,
0x04
,
0x38004e00
},
{
0x418400
,
1
,
0x04
,
0x38004e00
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x41840c
,
1
,
0x04
,
0x00001008
},
{
0x41840c
,
1
,
0x04
,
0x00001008
},
...
@@ -393,11 +392,21 @@ nvd9_grctx_init_gpc_0[] = {
...
@@ -393,11 +392,21 @@ nvd9_grctx_init_gpc_0[] = {
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{}
};
const
struct
nvc0_graph_init
nvd9_grctx_init_gpc_unk_1
[]
=
{
{
0x418600
,
1
,
0x04
,
0x0000001f
},
{
0x418600
,
1
,
0x04
,
0x0000001f
},
{
0x418684
,
1
,
0x04
,
0x0000000f
},
{
0x418684
,
1
,
0x04
,
0x0000000f
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
{
0x418704
,
1
,
0x04
,
0x00000080
},
{
0x418704
,
1
,
0x04
,
0x00000080
},
{
0x418708
,
3
,
0x04
,
0x00000000
},
{
0x418708
,
3
,
0x04
,
0x00000000
},
{}
};
static
const
struct
nvc0_graph_init
nvd9_grctx_init_setup_0
[]
=
{
{
0x418800
,
1
,
0x04
,
0x7006860a
},
{
0x418800
,
1
,
0x04
,
0x7006860a
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418828
,
1
,
0x04
,
0x00008442
},
{
0x418828
,
1
,
0x04
,
0x00008442
},
...
@@ -406,10 +415,11 @@ nvd9_grctx_init_gpc_0[] = {
...
@@ -406,10 +415,11 @@ nvd9_grctx_init_gpc_0[] = {
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188fc
,
1
,
0x04
,
0x20100008
},
{
0x4188fc
,
1
,
0x04
,
0x20100008
},
{
0x41891c
,
1
,
0x04
,
0x00ff00ff
},
{}
{
0x418924
,
1
,
0x04
,
0x00000000
},
};
{
0x418928
,
1
,
0x04
,
0x00ffff00
},
{
0x41892c
,
1
,
0x04
,
0x0000ff00
},
const
struct
nvc0_graph_init
nvd9_grctx_init_crstr_0
[]
=
{
{
0x418b00
,
1
,
0x04
,
0x00000006
},
{
0x418b00
,
1
,
0x04
,
0x00000006
},
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
...
@@ -418,20 +428,19 @@ nvd9_grctx_init_gpc_0[] = {
...
@@ -418,20 +428,19 @@ nvd9_grctx_init_gpc_0[] = {
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c6c
,
1
,
0x04
,
0x00000001
},
{
0x418c80
,
1
,
0x04
,
0x20200004
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x419000
,
1
,
0x04
,
0x00000780
},
{
0x419004
,
2
,
0x04
,
0x00000000
},
{
0x419014
,
1
,
0x04
,
0x00000004
},
{}
{}
};
};
static
const
struct
nvc0_graph_pack
static
const
struct
nvc0_graph_pack
nvd9_grctx_pack_gpc
[]
=
{
nvd9_grctx_pack_gpc
[]
=
{
{
nvd9_grctx_init_gpc_0
},
{
nvc0_grctx_init_gpc_unk_0
},
{
nvd9_grctx_init_prop_0
},
{
nvd9_grctx_init_gpc_unk_1
},
{
nvd9_grctx_init_setup_0
},
{
nvc0_grctx_init_zcull_0
},
{
nvd9_grctx_init_crstr_0
},
{
nvc1_grctx_init_gpm_0
},
{
nvc0_grctx_init_gcc_0
},
{}
{}
};
};
...
...
drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
View file @
97af71fa
...
@@ -714,21 +714,7 @@ nve4_grctx_pack_hub[] = {
...
@@ -714,21 +714,7 @@ nve4_grctx_pack_hub[] = {
};
};
static
const
struct
nvc0_graph_init
static
const
struct
nvc0_graph_init
nve4_grctx_init_gpc_0
[]
=
{
nve4_grctx_init_setup_0
[]
=
{
{
0x418380
,
1
,
0x04
,
0x00000016
},
{
0x418400
,
1
,
0x04
,
0x38004e00
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x41840c
,
1
,
0x04
,
0x00001008
},
{
0x418410
,
1
,
0x04
,
0x0fff0fff
},
{
0x418414
,
1
,
0x04
,
0x02200fff
},
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{
0x418600
,
1
,
0x04
,
0x0000001f
},
{
0x418684
,
1
,
0x04
,
0x0000000f
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
{
0x418704
,
1
,
0x04
,
0x00000080
},
{
0x418708
,
3
,
0x04
,
0x00000000
},
{
0x418800
,
1
,
0x04
,
0x7006860a
},
{
0x418800
,
1
,
0x04
,
0x7006860a
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418808
,
3
,
0x04
,
0x00000000
},
{
0x418828
,
1
,
0x04
,
0x00000044
},
{
0x418828
,
1
,
0x04
,
0x00000044
},
...
@@ -737,33 +723,30 @@ nve4_grctx_init_gpc_0[] = {
...
@@ -737,33 +723,30 @@ nve4_grctx_init_gpc_0[] = {
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188fc
,
1
,
0x04
,
0x20100018
},
{
0x4188fc
,
1
,
0x04
,
0x20100018
},
{
0x41891c
,
1
,
0x04
,
0x00ff00ff
},
{}
{
0x418924
,
1
,
0x04
,
0x00000000
},
};
{
0x418928
,
1
,
0x04
,
0x00ffff00
},
{
0x41892c
,
1
,
0x04
,
0x0000ff00
},
const
struct
nvc0_graph_init
{
0x418b00
,
1
,
0x04
,
0x00000006
},
nve4_grctx_init_gpm_0
[]
=
{
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
{
0x418b10
,
1
,
0x04
,
0x020398a4
},
{
0x418b14
,
1
,
0x04
,
0x0e629062
},
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c40
,
1
,
0x04
,
0xffffffff
},
{
0x418c40
,
1
,
0x04
,
0xffffffff
},
{
0x418c6c
,
1
,
0x04
,
0x00000001
},
{
0x418c6c
,
1
,
0x04
,
0x00000001
},
{
0x418c80
,
1
,
0x04
,
0x20200004
},
{
0x418c80
,
1
,
0x04
,
0x20200004
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x419000
,
1
,
0x04
,
0x00000780
},
{
0x419004
,
2
,
0x04
,
0x00000000
},
{
0x419014
,
1
,
0x04
,
0x00000004
},
{}
{}
};
};
static
const
struct
nvc0_graph_pack
static
const
struct
nvc0_graph_pack
nve4_grctx_pack_gpc
[]
=
{
nve4_grctx_pack_gpc
[]
=
{
{
nve4_grctx_init_gpc_0
},
{
nvc0_grctx_init_gpc_unk_0
},
{
nvd9_grctx_init_prop_0
},
{
nvd9_grctx_init_gpc_unk_1
},
{
nve4_grctx_init_setup_0
},
{
nvc0_grctx_init_zcull_0
},
{
nvd9_grctx_init_crstr_0
},
{
nve4_grctx_init_gpm_0
},
{
nvc0_grctx_init_gcc_0
},
{}
{}
};
};
...
...
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
View file @
97af71fa
...
@@ -684,21 +684,7 @@ nvf0_grctx_pack_hub[] = {
...
@@ -684,21 +684,7 @@ nvf0_grctx_pack_hub[] = {
};
};
static
const
struct
nvc0_graph_init
static
const
struct
nvc0_graph_init
nvf0_grctx_init_gpc_0
[]
=
{
nvf0_grctx_init_setup_0
[]
=
{
{
0x418380
,
1
,
0x04
,
0x00000016
},
{
0x418400
,
1
,
0x04
,
0x38004e00
},
{
0x418404
,
1
,
0x04
,
0x71e0ffff
},
{
0x41840c
,
1
,
0x04
,
0x00001008
},
{
0x418410
,
1
,
0x04
,
0x0fff0fff
},
{
0x418414
,
1
,
0x04
,
0x02200fff
},
{
0x418450
,
6
,
0x04
,
0x00000000
},
{
0x418468
,
1
,
0x04
,
0x00000001
},
{
0x41846c
,
2
,
0x04
,
0x00000000
},
{
0x418600
,
1
,
0x04
,
0x0000001f
},
{
0x418684
,
1
,
0x04
,
0x0000000f
},
{
0x418700
,
1
,
0x04
,
0x00000002
},
{
0x418704
,
1
,
0x04
,
0x00000080
},
{
0x418708
,
3
,
0x04
,
0x00000000
},
{
0x418800
,
1
,
0x04
,
0x7006860a
},
{
0x418800
,
1
,
0x04
,
0x7006860a
},
{
0x418808
,
1
,
0x04
,
0x00000000
},
{
0x418808
,
1
,
0x04
,
0x00000000
},
{
0x41880c
,
1
,
0x04
,
0x00000030
},
{
0x41880c
,
1
,
0x04
,
0x00000030
},
...
@@ -709,34 +695,26 @@ nvf0_grctx_init_gpc_0[] = {
...
@@ -709,34 +695,26 @@ nvf0_grctx_init_gpc_0[] = {
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e0
,
1
,
0x04
,
0x01000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188e8
,
5
,
0x04
,
0x00000000
},
{
0x4188fc
,
1
,
0x04
,
0x20100018
},
{
0x4188fc
,
1
,
0x04
,
0x20100018
},
{
0x41891c
,
1
,
0x04
,
0x00ff00ff
},
{}
{
0x418924
,
1
,
0x04
,
0x00000000
},
};
{
0x418928
,
1
,
0x04
,
0x00ffff00
},
{
0x41892c
,
1
,
0x04
,
0x0000ff00
},
const
struct
nvc0_graph_init
{
0x418b00
,
1
,
0x04
,
0x00000006
},
nvf0_grctx_init_gpc_unk_2
[]
=
{
{
0x418b08
,
1
,
0x04
,
0x0a418820
},
{
0x418b0c
,
1
,
0x04
,
0x062080e6
},
{
0x418b10
,
1
,
0x04
,
0x020398a4
},
{
0x418b14
,
1
,
0x04
,
0x0e629062
},
{
0x418b18
,
1
,
0x04
,
0x0a418820
},
{
0x418b1c
,
1
,
0x04
,
0x000000e6
},
{
0x418bb8
,
1
,
0x04
,
0x00000103
},
{
0x418c08
,
1
,
0x04
,
0x00000001
},
{
0x418c10
,
8
,
0x04
,
0x00000000
},
{
0x418c40
,
1
,
0x04
,
0xffffffff
},
{
0x418c6c
,
1
,
0x04
,
0x00000001
},
{
0x418c80
,
1
,
0x04
,
0x20200004
},
{
0x418c8c
,
1
,
0x04
,
0x00000001
},
{
0x418d24
,
1
,
0x04
,
0x00000000
},
{
0x418d24
,
1
,
0x04
,
0x00000000
},
{
0x419000
,
1
,
0x04
,
0x00000780
},
{
0x419004
,
2
,
0x04
,
0x00000000
},
{
0x419014
,
1
,
0x04
,
0x00000004
},
{}
{}
};
};
static
const
struct
nvc0_graph_pack
static
const
struct
nvc0_graph_pack
nvf0_grctx_pack_gpc
[]
=
{
nvf0_grctx_pack_gpc
[]
=
{
{
nvf0_grctx_init_gpc_0
},
{
nvc0_grctx_init_gpc_unk_0
},
{
nvd9_grctx_init_prop_0
},
{
nvd9_grctx_init_gpc_unk_1
},
{
nvf0_grctx_init_setup_0
},
{
nvc0_grctx_init_zcull_0
},
{
nvd9_grctx_init_crstr_0
},
{
nve4_grctx_init_gpm_0
},
{
nvf0_grctx_init_gpc_unk_2
},
{
nvc0_grctx_init_gcc_0
},
{}
{}
};
};
...
...
drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
View file @
97af71fa
...
@@ -69,37 +69,19 @@ nv108_graph_init_ds_0[] = {
...
@@ -69,37 +69,19 @@ nv108_graph_init_ds_0[] = {
};
};
static
const
struct
nvc0_graph_init
static
const
struct
nvc0_graph_init
nv108_graph_init_gpc_0
[]
=
{
nv108_graph_init_gpc_unk_0
[]
=
{
{
0x418408
,
1
,
0x04
,
0x00000000
},
{
0x4184a0
,
3
,
0x04
,
0x00000000
},
{
0x418604
,
1
,
0x04
,
0x00000000
},
{
0x418604
,
1
,
0x04
,
0x00000000
},
{
0x418680
,
1
,
0x04
,
0x00000000
},
{
0x418680
,
1
,
0x04
,
0x00000000
},
{
0x418714
,
1
,
0x04
,
0x00000000
},
{
0x418714
,
1
,
0x04
,
0x00000000
},
{
0x418384
,
2
,
0x04
,
0x00000000
},
{
0x418384
,
2
,
0x04
,
0x00000000
},
{
0x418814
,
3
,
0x04
,
0x00000000
},
{}
{
0x418b04
,
1
,
0x04
,
0x00000000
},
};
static
const
struct
nvc0_graph_init
nv108_graph_init_setup_1
[]
=
{
{
0x4188c8
,
2
,
0x04
,
0x00000000
},
{
0x4188c8
,
2
,
0x04
,
0x00000000
},
{
0x4188d0
,
1
,
0x04
,
0x00010000
},
{
0x4188d0
,
1
,
0x04
,
0x00010000
},
{
0x4188d4
,
1
,
0x04
,
0x00000201
},
{
0x4188d4
,
1
,
0x04
,
0x00000201
},
{
0x418910
,
1
,
0x04
,
0x00010001
},
{
0x418914
,
1
,
0x04
,
0x00000301
},
{
0x418918
,
1
,
0x04
,
0x00800000
},
{
0x418980
,
1
,
0x04
,
0x77777770
},
{
0x418984
,
3
,
0x04
,
0x77777777
},
{
0x418c04
,
1
,
0x04
,
0x00000000
},
{
0x418c64
,
2
,
0x04
,
0x00000000
},
{
0x418c88
,
1
,
0x04
,
0x00000000
},
{
0x418cb4
,
2
,
0x04
,
0x00000000
},
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418d28
,
2
,
0x04
,
0x00000000
},
{
0x418f00
,
1
,
0x04
,
0x00000400
},
{
0x418f08
,
1
,
0x04
,
0x00000000
},
{
0x418f20
,
2
,
0x04
,
0x00000000
},
{
0x418e00
,
1
,
0x04
,
0x00000000
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x418e1c
,
2
,
0x04
,
0x00000000
},
{
0x41900c
,
1
,
0x04
,
0x00000000
},
{
0x419018
,
1
,
0x04
,
0x00000000
},
{}
{}
};
};
...
@@ -154,7 +136,15 @@ nv108_graph_pack_mmio[] = {
...
@@ -154,7 +136,15 @@ nv108_graph_pack_mmio[] = {
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_scc_0
},
{
nvf0_graph_init_sked_0
},
{
nvf0_graph_init_sked_0
},
{
nvf0_graph_init_cwd_0
},
{
nvf0_graph_init_cwd_0
},
{
nv108_graph_init_gpc_0
},
{
nvd9_graph_init_prop_0
},
{
nv108_graph_init_gpc_unk_0
},
{
nvc0_graph_init_setup_0
},
{
nvc0_graph_init_crstr_0
},
{
nv108_graph_init_setup_1
},
{
nvc0_graph_init_zcull_0
},
{
nvd9_graph_init_gpm_0
},
{
nvf0_graph_init_gpc_unk_1
},
{
nvc0_graph_init_gcc_0
},
{
nv108_graph_init_tpc_0
},
{
nv108_graph_init_tpc_0
},
{
nvd7_graph_init_ppc_0
},
{
nvd7_graph_init_ppc_0
},
{
nve4_graph_init_be_0
},
{
nve4_graph_init_be_0
},
...
...
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View file @
97af71fa
...
@@ -206,29 +206,69 @@ nvc0_graph_init_scc_0[] = {
...
@@ -206,29 +206,69 @@ nvc0_graph_init_scc_0[] = {
};
};
const
struct
nvc0_graph_init
const
struct
nvc0_graph_init
nvc0_graph_init_
gpc
_0
[]
=
{
nvc0_graph_init_
prop
_0
[]
=
{
{
0x4184a0
,
1
,
0x04
,
0x00000000
},
{
0x4184a0
,
1
,
0x04
,
0x00000000
},
{}
};
const
struct
nvc0_graph_init
nvc0_graph_init_gpc_unk_0
[]
=
{
{
0x418604
,
1
,
0x04
,
0x00000000
},
{
0x418604
,
1
,
0x04
,
0x00000000
},
{
0x418680
,
1
,
0x04
,
0x00000000
},
{
0x418680
,
1
,
0x04
,
0x00000000
},
{
0x418714
,
1
,
0x04
,
0x80000000
},
{
0x418714
,
1
,
0x04
,
0x80000000
},
{
0x418384
,
1
,
0x04
,
0x00000000
},
{
0x418384
,
1
,
0x04
,
0x00000000
},
{}
};
const
struct
nvc0_graph_init
nvc0_graph_init_setup_0
[]
=
{
{
0x418814
,
3
,
0x04
,
0x00000000
},
{
0x418814
,
3
,
0x04
,
0x00000000
},
{}
};
const
struct
nvc0_graph_init
nvc0_graph_init_crstr_0
[]
=
{
{
0x418b04
,
1
,
0x04
,
0x00000000
},
{
0x418b04
,
1
,
0x04
,
0x00000000
},
{}
};
const
struct
nvc0_graph_init
nvc0_graph_init_setup_1
[]
=
{
{
0x4188c8
,
1
,
0x04
,
0x80000000
},
{
0x4188c8
,
1
,
0x04
,
0x80000000
},
{
0x4188cc
,
1
,
0x04
,
0x00000000
},
{
0x4188cc
,
1
,
0x04
,
0x00000000
},
{
0x4188d0
,
1
,
0x04
,
0x00010000
},
{
0x4188d0
,
1
,
0x04
,
0x00010000
},
{
0x4188d4
,
1
,
0x04
,
0x00000001
},
{
0x4188d4
,
1
,
0x04
,
0x00000001
},
{}
};
const
struct
nvc0_graph_init
nvc0_graph_init_zcull_0
[]
=
{
{
0x418910
,
1
,
0x04
,
0x00010001
},
{
0x418910
,
1
,
0x04
,
0x00010001
},
{
0x418914
,
1
,
0x04
,
0x00000301
},
{
0x418914
,
1
,
0x04
,
0x00000301
},
{
0x418918
,
1
,
0x04
,
0x00800000
},
{
0x418918
,
1
,
0x04
,
0x00800000
},
{
0x418980
,
1
,
0x04
,
0x77777770
},
{
0x418980
,
1
,
0x04
,
0x77777770
},
{
0x418984
,
3
,
0x04
,
0x77777777
},
{
0x418984
,
3
,
0x04
,
0x77777777
},
{}
};
const
struct
nvc0_graph_init
nvc0_graph_init_gpm_0
[]
=
{
{
0x418c04
,
1
,
0x04
,
0x00000000
},
{
0x418c04
,
1
,
0x04
,
0x00000000
},
{
0x418c88
,
1
,
0x04
,
0x00000000
},
{
0x418c88
,
1
,
0x04
,
0x00000000
},
{}
};
const
struct
nvc0_graph_init
nvc0_graph_init_gpc_unk_1
[]
=
{
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418f08
,
1
,
0x04
,
0x00000000
},
{
0x418f08
,
1
,
0x04
,
0x00000000
},
{
0x418e00
,
1
,
0x04
,
0x00000050
},
{
0x418e00
,
1
,
0x04
,
0x00000050
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{}
};
const
struct
nvc0_graph_init
nvc0_graph_init_gcc_0
[]
=
{
{
0x41900c
,
1
,
0x04
,
0x00000000
},
{
0x41900c
,
1
,
0x04
,
0x00000000
},
{
0x419018
,
1
,
0x04
,
0x00000000
},
{
0x419018
,
1
,
0x04
,
0x00000000
},
{}
{}
...
@@ -304,7 +344,15 @@ nvc0_graph_pack_mmio[] = {
...
@@ -304,7 +344,15 @@ nvc0_graph_pack_mmio[] = {
{
nvc0_graph_init_pd_0
},
{
nvc0_graph_init_pd_0
},
{
nvc0_graph_init_ds_0
},
{
nvc0_graph_init_ds_0
},
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_gpc_0
},
{
nvc0_graph_init_prop_0
},
{
nvc0_graph_init_gpc_unk_0
},
{
nvc0_graph_init_setup_0
},
{
nvc0_graph_init_crstr_0
},
{
nvc0_graph_init_setup_1
},
{
nvc0_graph_init_zcull_0
},
{
nvc0_graph_init_gpm_0
},
{
nvc0_graph_init_gpc_unk_1
},
{
nvc0_graph_init_gcc_0
},
{
nvc0_graph_init_tpc_0
},
{
nvc0_graph_init_tpc_0
},
{
nvc0_graph_init_be_0
},
{
nvc0_graph_init_be_0
},
{
nvc0_graph_init_fe_1
},
{
nvc0_graph_init_fe_1
},
...
...
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
View file @
97af71fa
...
@@ -172,16 +172,29 @@ extern const struct nvc0_graph_init nvc0_graph_init_rstr2d_0[];
...
@@ -172,16 +172,29 @@ extern const struct nvc0_graph_init nvc0_graph_init_rstr2d_0[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_pd_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_pd_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_ds_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_ds_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_scc_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_scc_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_gpc_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_prop_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_gpc_unk_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_setup_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_crstr_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_setup_1
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_zcull_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_gpm_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_gpc_unk_1
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_gcc_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_be_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_be_0
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_fe_1
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_fe_1
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_tpc_1
[];
extern
const
struct
nvc0_graph_init
nvc0_graph_init_tpc_1
[];
extern
const
struct
nvc0_graph_init
nvc4_graph_init_ds_0
[];
extern
const
struct
nvc0_graph_init
nvc4_graph_init_ds_0
[];
extern
const
struct
nvc0_graph_init
nvc1_graph_init_gpc_unk_0
[];
extern
const
struct
nvc0_graph_init
nvc1_graph_init_setup_1
[];
extern
const
struct
nvc0_graph_init
nvd9_graph_init_pd_0
[];
extern
const
struct
nvc0_graph_init
nvd9_graph_init_pd_0
[];
extern
const
struct
nvc0_graph_init
nvd9_graph_init_ds_0
[];
extern
const
struct
nvc0_graph_init
nvd9_graph_init_ds_0
[];
extern
const
struct
nvc0_graph_init
nvd9_graph_init_gpc_0
[];
extern
const
struct
nvc0_graph_init
nvd9_graph_init_prop_0
[];
extern
const
struct
nvc0_graph_init
nvd9_graph_init_gpm_0
[];
extern
const
struct
nvc0_graph_init
nvd9_graph_init_gpc_unk_1
[];
extern
const
struct
nvc0_graph_init
nvd9_graph_init_fe_1
[];
extern
const
struct
nvc0_graph_init
nvd9_graph_init_fe_1
[];
extern
const
struct
nvc0_graph_init
nvd7_graph_init_ppc_0
[];
extern
const
struct
nvc0_graph_init
nvd7_graph_init_ppc_0
[];
...
@@ -192,6 +205,7 @@ extern const struct nvc0_graph_init nve4_graph_init_be_0[];
...
@@ -192,6 +205,7 @@ extern const struct nvc0_graph_init nve4_graph_init_be_0[];
extern
const
struct
nvc0_graph_init
nvf0_graph_init_fe_0
[];
extern
const
struct
nvc0_graph_init
nvf0_graph_init_fe_0
[];
extern
const
struct
nvc0_graph_init
nvf0_graph_init_sked_0
[];
extern
const
struct
nvc0_graph_init
nvf0_graph_init_sked_0
[];
extern
const
struct
nvc0_graph_init
nvf0_graph_init_cwd_0
[];
extern
const
struct
nvc0_graph_init
nvf0_graph_init_cwd_0
[];
extern
const
struct
nvc0_graph_init
nvf0_graph_init_gpc_unk_1
[];
#endif
#endif
drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
View file @
97af71fa
...
@@ -43,31 +43,29 @@ nvc1_graph_sclass[] = {
...
@@ -43,31 +43,29 @@ nvc1_graph_sclass[] = {
* PGRAPH register lists
* PGRAPH register lists
******************************************************************************/
******************************************************************************/
static
const
struct
nvc0_graph_init
const
struct
nvc0_graph_init
nvc1_graph_init_gpc_0
[]
=
{
nvc1_graph_init_gpc_unk_0
[]
=
{
{
0x4184a0
,
1
,
0x04
,
0x00000000
},
{
0x418604
,
1
,
0x04
,
0x00000000
},
{
0x418604
,
1
,
0x04
,
0x00000000
},
{
0x418680
,
1
,
0x04
,
0x00000000
},
{
0x418680
,
1
,
0x04
,
0x00000000
},
{
0x418714
,
1
,
0x04
,
0x00000000
},
{
0x418714
,
1
,
0x04
,
0x00000000
},
{
0x418384
,
1
,
0x04
,
0x00000000
},
{
0x418384
,
1
,
0x04
,
0x00000000
},
{
0x418814
,
3
,
0x04
,
0x00000000
},
{}
{
0x418b04
,
1
,
0x04
,
0x00000000
},
};
const
struct
nvc0_graph_init
nvc1_graph_init_setup_1
[]
=
{
{
0x4188c8
,
2
,
0x04
,
0x00000000
},
{
0x4188c8
,
2
,
0x04
,
0x00000000
},
{
0x4188d0
,
1
,
0x04
,
0x00010000
},
{
0x4188d0
,
1
,
0x04
,
0x00010000
},
{
0x4188d4
,
1
,
0x04
,
0x00000001
},
{
0x4188d4
,
1
,
0x04
,
0x00000001
},
{
0x418910
,
1
,
0x04
,
0x00010001
},
{}
{
0x418914
,
1
,
0x04
,
0x00000301
},
};
{
0x418918
,
1
,
0x04
,
0x00800000
},
{
0x418980
,
1
,
0x04
,
0x77777770
},
static
const
struct
nvc0_graph_init
{
0x418984
,
3
,
0x04
,
0x77777777
},
nvc1_graph_init_gpc_unk_1
[]
=
{
{
0x418c04
,
1
,
0x04
,
0x00000000
},
{
0x418c88
,
1
,
0x04
,
0x00000000
},
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418f08
,
1
,
0x04
,
0x00000000
},
{
0x418f08
,
1
,
0x04
,
0x00000000
},
{
0x418e00
,
1
,
0x04
,
0x00000003
},
{
0x418e00
,
1
,
0x04
,
0x00000003
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x41900c
,
1
,
0x04
,
0x00000000
},
{
0x419018
,
1
,
0x04
,
0x00000000
},
{}
{}
};
};
...
@@ -122,7 +120,15 @@ nvc1_graph_pack_mmio[] = {
...
@@ -122,7 +120,15 @@ nvc1_graph_pack_mmio[] = {
{
nvc0_graph_init_pd_0
},
{
nvc0_graph_init_pd_0
},
{
nvc4_graph_init_ds_0
},
{
nvc4_graph_init_ds_0
},
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_scc_0
},
{
nvc1_graph_init_gpc_0
},
{
nvc0_graph_init_prop_0
},
{
nvc1_graph_init_gpc_unk_0
},
{
nvc0_graph_init_setup_0
},
{
nvc0_graph_init_crstr_0
},
{
nvc1_graph_init_setup_1
},
{
nvc0_graph_init_zcull_0
},
{
nvc0_graph_init_gpm_0
},
{
nvc1_graph_init_gpc_unk_1
},
{
nvc0_graph_init_gcc_0
},
{
nvc1_graph_init_tpc_0
},
{
nvc1_graph_init_tpc_0
},
{
nvc0_graph_init_be_0
},
{
nvc0_graph_init_be_0
},
{
nvc0_graph_init_fe_1
},
{
nvc0_graph_init_fe_1
},
...
...
drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c
View file @
97af71fa
...
@@ -87,7 +87,15 @@ nvc4_graph_pack_mmio[] = {
...
@@ -87,7 +87,15 @@ nvc4_graph_pack_mmio[] = {
{
nvc0_graph_init_pd_0
},
{
nvc0_graph_init_pd_0
},
{
nvc4_graph_init_ds_0
},
{
nvc4_graph_init_ds_0
},
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_gpc_0
},
{
nvc0_graph_init_prop_0
},
{
nvc0_graph_init_gpc_unk_0
},
{
nvc0_graph_init_setup_0
},
{
nvc0_graph_init_crstr_0
},
{
nvc0_graph_init_setup_1
},
{
nvc0_graph_init_zcull_0
},
{
nvc0_graph_init_gpm_0
},
{
nvc0_graph_init_gpc_unk_1
},
{
nvc0_graph_init_gcc_0
},
{
nvc4_graph_init_tpc_0
},
{
nvc4_graph_init_tpc_0
},
{
nvc0_graph_init_be_0
},
{
nvc0_graph_init_be_0
},
{
nvc0_graph_init_fe_1
},
{
nvc0_graph_init_fe_1
},
...
...
drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
View file @
97af71fa
...
@@ -44,34 +44,6 @@ nvc8_graph_sclass[] = {
...
@@ -44,34 +44,6 @@ nvc8_graph_sclass[] = {
* PGRAPH register lists
* PGRAPH register lists
******************************************************************************/
******************************************************************************/
static
const
struct
nvc0_graph_init
nvc8_graph_init_gpc_0
[]
=
{
{
0x4184a0
,
1
,
0x04
,
0x00000000
},
{
0x418604
,
1
,
0x04
,
0x00000000
},
{
0x418680
,
1
,
0x04
,
0x00000000
},
{
0x418714
,
1
,
0x04
,
0x80000000
},
{
0x418384
,
1
,
0x04
,
0x00000000
},
{
0x418814
,
3
,
0x04
,
0x00000000
},
{
0x418b04
,
1
,
0x04
,
0x00000000
},
{
0x4188c8
,
2
,
0x04
,
0x00000000
},
{
0x4188d0
,
1
,
0x04
,
0x00010000
},
{
0x4188d4
,
1
,
0x04
,
0x00000001
},
{
0x418910
,
1
,
0x04
,
0x00010001
},
{
0x418914
,
1
,
0x04
,
0x00000301
},
{
0x418918
,
1
,
0x04
,
0x00800000
},
{
0x418980
,
1
,
0x04
,
0x77777770
},
{
0x418984
,
3
,
0x04
,
0x77777777
},
{
0x418c04
,
1
,
0x04
,
0x00000000
},
{
0x418c88
,
1
,
0x04
,
0x00000000
},
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418f08
,
1
,
0x04
,
0x00000000
},
{
0x418e00
,
1
,
0x04
,
0x00000050
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x41900c
,
1
,
0x04
,
0x00000000
},
{
0x419018
,
1
,
0x04
,
0x00000000
},
{}
};
static
const
struct
nvc0_graph_init
static
const
struct
nvc0_graph_init
nvc8_graph_init_tpc_0
[]
=
{
nvc8_graph_init_tpc_0
[]
=
{
{
0x419d08
,
2
,
0x04
,
0x00000000
},
{
0x419d08
,
2
,
0x04
,
0x00000000
},
...
@@ -118,7 +90,15 @@ nvc8_graph_pack_mmio[] = {
...
@@ -118,7 +90,15 @@ nvc8_graph_pack_mmio[] = {
{
nvc0_graph_init_pd_0
},
{
nvc0_graph_init_pd_0
},
{
nvc0_graph_init_ds_0
},
{
nvc0_graph_init_ds_0
},
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_scc_0
},
{
nvc8_graph_init_gpc_0
},
{
nvc0_graph_init_prop_0
},
{
nvc0_graph_init_gpc_unk_0
},
{
nvc0_graph_init_setup_0
},
{
nvc0_graph_init_crstr_0
},
{
nvc1_graph_init_setup_1
},
{
nvc0_graph_init_zcull_0
},
{
nvc0_graph_init_gpm_0
},
{
nvc0_graph_init_gpc_unk_1
},
{
nvc0_graph_init_gcc_0
},
{
nvc8_graph_init_tpc_0
},
{
nvc8_graph_init_tpc_0
},
{
nvc0_graph_init_be_0
},
{
nvc0_graph_init_be_0
},
{
nvc0_graph_init_fe_1
},
{
nvc0_graph_init_fe_1
},
...
...
drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
View file @
97af71fa
...
@@ -90,7 +90,15 @@ nvd7_graph_pack_mmio[] = {
...
@@ -90,7 +90,15 @@ nvd7_graph_pack_mmio[] = {
{
nvd9_graph_init_pd_0
},
{
nvd9_graph_init_pd_0
},
{
nvd9_graph_init_ds_0
},
{
nvd9_graph_init_ds_0
},
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_scc_0
},
{
nvd9_graph_init_gpc_0
},
{
nvd9_graph_init_prop_0
},
{
nvc1_graph_init_gpc_unk_0
},
{
nvc0_graph_init_setup_0
},
{
nvc0_graph_init_crstr_0
},
{
nvc1_graph_init_setup_1
},
{
nvc0_graph_init_zcull_0
},
{
nvd9_graph_init_gpm_0
},
{
nvd9_graph_init_gpc_unk_1
},
{
nvc0_graph_init_gcc_0
},
{
nvd7_graph_init_tpc_0
},
{
nvd7_graph_init_tpc_0
},
{
nvd7_graph_init_ppc_0
},
{
nvd7_graph_init_ppc_0
},
{
nvc0_graph_init_be_0
},
{
nvc0_graph_init_be_0
},
...
...
drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
View file @
97af71fa
...
@@ -47,27 +47,23 @@ nvd9_graph_init_ds_0[] = {
...
@@ -47,27 +47,23 @@ nvd9_graph_init_ds_0[] = {
};
};
const
struct
nvc0_graph_init
const
struct
nvc0_graph_init
nvd9_graph_init_
gpc
_0
[]
=
{
nvd9_graph_init_
prop
_0
[]
=
{
{
0x418408
,
1
,
0x04
,
0x00000000
},
{
0x418408
,
1
,
0x04
,
0x00000000
},
{
0x4184a0
,
3
,
0x04
,
0x00000000
},
{
0x4184a0
,
3
,
0x04
,
0x00000000
},
{
0x418604
,
1
,
0x04
,
0x00000000
},
{}
{
0x418680
,
1
,
0x04
,
0x00000000
},
};
{
0x418714
,
1
,
0x04
,
0x00000000
},
{
0x418384
,
1
,
0x04
,
0x00000000
},
const
struct
nvc0_graph_init
{
0x418814
,
3
,
0x04
,
0x00000000
},
nvd9_graph_init_gpm_0
[]
=
{
{
0x418b04
,
1
,
0x04
,
0x00000000
},
{
0x4188c8
,
2
,
0x04
,
0x00000000
},
{
0x4188d0
,
1
,
0x04
,
0x00010000
},
{
0x4188d4
,
1
,
0x04
,
0x00000001
},
{
0x418910
,
1
,
0x04
,
0x00010001
},
{
0x418914
,
1
,
0x04
,
0x00000301
},
{
0x418918
,
1
,
0x04
,
0x00800000
},
{
0x418980
,
1
,
0x04
,
0x77777770
},
{
0x418984
,
3
,
0x04
,
0x77777777
},
{
0x418c04
,
1
,
0x04
,
0x00000000
},
{
0x418c04
,
1
,
0x04
,
0x00000000
},
{
0x418c64
,
2
,
0x04
,
0x00000000
},
{
0x418c64
,
2
,
0x04
,
0x00000000
},
{
0x418c88
,
1
,
0x04
,
0x00000000
},
{
0x418c88
,
1
,
0x04
,
0x00000000
},
{
0x418cb4
,
2
,
0x04
,
0x00000000
},
{
0x418cb4
,
2
,
0x04
,
0x00000000
},
{}
};
const
struct
nvc0_graph_init
nvd9_graph_init_gpc_unk_1
[]
=
{
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418d28
,
2
,
0x04
,
0x00000000
},
{
0x418d28
,
2
,
0x04
,
0x00000000
},
{
0x418f00
,
1
,
0x04
,
0x00000000
},
{
0x418f00
,
1
,
0x04
,
0x00000000
},
...
@@ -76,8 +72,6 @@ nvd9_graph_init_gpc_0[] = {
...
@@ -76,8 +72,6 @@ nvd9_graph_init_gpc_0[] = {
{
0x418e00
,
1
,
0x04
,
0x00000003
},
{
0x418e00
,
1
,
0x04
,
0x00000003
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x418e1c
,
2
,
0x04
,
0x00000000
},
{
0x418e1c
,
2
,
0x04
,
0x00000000
},
{
0x41900c
,
1
,
0x04
,
0x00000000
},
{
0x419018
,
1
,
0x04
,
0x00000000
},
{}
{}
};
};
...
@@ -143,7 +137,15 @@ nvd9_graph_pack_mmio[] = {
...
@@ -143,7 +137,15 @@ nvd9_graph_pack_mmio[] = {
{
nvd9_graph_init_pd_0
},
{
nvd9_graph_init_pd_0
},
{
nvd9_graph_init_ds_0
},
{
nvd9_graph_init_ds_0
},
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_scc_0
},
{
nvd9_graph_init_gpc_0
},
{
nvd9_graph_init_prop_0
},
{
nvc1_graph_init_gpc_unk_0
},
{
nvc0_graph_init_setup_0
},
{
nvc0_graph_init_crstr_0
},
{
nvc1_graph_init_setup_1
},
{
nvc0_graph_init_zcull_0
},
{
nvd9_graph_init_gpm_0
},
{
nvd9_graph_init_gpc_unk_1
},
{
nvc0_graph_init_gcc_0
},
{
nvd9_graph_init_tpc_0
},
{
nvd9_graph_init_tpc_0
},
{
nvc0_graph_init_be_0
},
{
nvc0_graph_init_be_0
},
{
nvd9_graph_init_fe_1
},
{
nvd9_graph_init_fe_1
},
...
...
drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
View file @
97af71fa
...
@@ -81,27 +81,7 @@ nve4_graph_init_cwd_0[] = {
...
@@ -81,27 +81,7 @@ nve4_graph_init_cwd_0[] = {
};
};
static
const
struct
nvc0_graph_init
static
const
struct
nvc0_graph_init
nve4_graph_init_gpc_0
[]
=
{
nve4_graph_init_gpc_unk_1
[]
=
{
{
0x418408
,
1
,
0x04
,
0x00000000
},
{
0x4184a0
,
3
,
0x04
,
0x00000000
},
{
0x418604
,
1
,
0x04
,
0x00000000
},
{
0x418680
,
1
,
0x04
,
0x00000000
},
{
0x418714
,
1
,
0x04
,
0x00000000
},
{
0x418384
,
1
,
0x04
,
0x00000000
},
{
0x418814
,
3
,
0x04
,
0x00000000
},
{
0x418b04
,
1
,
0x04
,
0x00000000
},
{
0x4188c8
,
2
,
0x04
,
0x00000000
},
{
0x4188d0
,
1
,
0x04
,
0x00010000
},
{
0x4188d4
,
1
,
0x04
,
0x00000001
},
{
0x418910
,
1
,
0x04
,
0x00010001
},
{
0x418914
,
1
,
0x04
,
0x00000301
},
{
0x418918
,
1
,
0x04
,
0x00800000
},
{
0x418980
,
1
,
0x04
,
0x77777770
},
{
0x418984
,
3
,
0x04
,
0x77777777
},
{
0x418c04
,
1
,
0x04
,
0x00000000
},
{
0x418c64
,
2
,
0x04
,
0x00000000
},
{
0x418c88
,
1
,
0x04
,
0x00000000
},
{
0x418cb4
,
2
,
0x04
,
0x00000000
},
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418d28
,
2
,
0x04
,
0x00000000
},
{
0x418d28
,
2
,
0x04
,
0x00000000
},
{
0x418f00
,
1
,
0x04
,
0x00000000
},
{
0x418f00
,
1
,
0x04
,
0x00000000
},
...
@@ -110,8 +90,6 @@ nve4_graph_init_gpc_0[] = {
...
@@ -110,8 +90,6 @@ nve4_graph_init_gpc_0[] = {
{
0x418e00
,
1
,
0x04
,
0x00000060
},
{
0x418e00
,
1
,
0x04
,
0x00000060
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x418e1c
,
2
,
0x04
,
0x00000000
},
{
0x418e1c
,
2
,
0x04
,
0x00000000
},
{
0x41900c
,
1
,
0x04
,
0x00000000
},
{
0x419018
,
1
,
0x04
,
0x00000000
},
{}
{}
};
};
...
@@ -175,7 +153,15 @@ nve4_graph_pack_mmio[] = {
...
@@ -175,7 +153,15 @@ nve4_graph_pack_mmio[] = {
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_scc_0
},
{
nve4_graph_init_sked_0
},
{
nve4_graph_init_sked_0
},
{
nve4_graph_init_cwd_0
},
{
nve4_graph_init_cwd_0
},
{
nve4_graph_init_gpc_0
},
{
nvd9_graph_init_prop_0
},
{
nvc1_graph_init_gpc_unk_0
},
{
nvc0_graph_init_setup_0
},
{
nvc0_graph_init_crstr_0
},
{
nvc1_graph_init_setup_1
},
{
nvc0_graph_init_zcull_0
},
{
nvd9_graph_init_gpm_0
},
{
nve4_graph_init_gpc_unk_1
},
{
nvc0_graph_init_gcc_0
},
{
nve4_graph_init_tpc_0
},
{
nve4_graph_init_tpc_0
},
{
nvd7_graph_init_ppc_0
},
{
nvd7_graph_init_ppc_0
},
{
nve4_graph_init_be_0
},
{
nve4_graph_init_be_0
},
...
...
drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
View file @
97af71fa
...
@@ -75,28 +75,8 @@ nvf0_graph_init_cwd_0[] = {
...
@@ -75,28 +75,8 @@ nvf0_graph_init_cwd_0[] = {
{}
{}
};
};
static
const
struct
nvc0_graph_init
const
struct
nvc0_graph_init
nvf0_graph_init_gpc_0
[]
=
{
nvf0_graph_init_gpc_unk_1
[]
=
{
{
0x418408
,
1
,
0x04
,
0x00000000
},
{
0x4184a0
,
3
,
0x04
,
0x00000000
},
{
0x418604
,
1
,
0x04
,
0x00000000
},
{
0x418680
,
1
,
0x04
,
0x00000000
},
{
0x418714
,
1
,
0x04
,
0x00000000
},
{
0x418384
,
1
,
0x04
,
0x00000000
},
{
0x418814
,
3
,
0x04
,
0x00000000
},
{
0x418b04
,
1
,
0x04
,
0x00000000
},
{
0x4188c8
,
2
,
0x04
,
0x00000000
},
{
0x4188d0
,
1
,
0x04
,
0x00010000
},
{
0x4188d4
,
1
,
0x04
,
0x00000001
},
{
0x418910
,
1
,
0x04
,
0x00010001
},
{
0x418914
,
1
,
0x04
,
0x00000301
},
{
0x418918
,
1
,
0x04
,
0x00800000
},
{
0x418980
,
1
,
0x04
,
0x77777770
},
{
0x418984
,
3
,
0x04
,
0x77777777
},
{
0x418c04
,
1
,
0x04
,
0x00000000
},
{
0x418c64
,
2
,
0x04
,
0x00000000
},
{
0x418c88
,
1
,
0x04
,
0x00000000
},
{
0x418cb4
,
2
,
0x04
,
0x00000000
},
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418d00
,
1
,
0x04
,
0x00000000
},
{
0x418d28
,
2
,
0x04
,
0x00000000
},
{
0x418d28
,
2
,
0x04
,
0x00000000
},
{
0x418f00
,
1
,
0x04
,
0x00000400
},
{
0x418f00
,
1
,
0x04
,
0x00000400
},
...
@@ -105,8 +85,6 @@ nvf0_graph_init_gpc_0[] = {
...
@@ -105,8 +85,6 @@ nvf0_graph_init_gpc_0[] = {
{
0x418e00
,
1
,
0x04
,
0x00000000
},
{
0x418e00
,
1
,
0x04
,
0x00000000
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x418e08
,
1
,
0x04
,
0x00000000
},
{
0x418e1c
,
2
,
0x04
,
0x00000000
},
{
0x418e1c
,
2
,
0x04
,
0x00000000
},
{
0x41900c
,
1
,
0x04
,
0x00000000
},
{
0x419018
,
1
,
0x04
,
0x00000000
},
{}
{}
};
};
...
@@ -162,7 +140,15 @@ nvf0_graph_pack_mmio[] = {
...
@@ -162,7 +140,15 @@ nvf0_graph_pack_mmio[] = {
{
nvc0_graph_init_scc_0
},
{
nvc0_graph_init_scc_0
},
{
nvf0_graph_init_sked_0
},
{
nvf0_graph_init_sked_0
},
{
nvf0_graph_init_cwd_0
},
{
nvf0_graph_init_cwd_0
},
{
nvf0_graph_init_gpc_0
},
{
nvd9_graph_init_prop_0
},
{
nvc1_graph_init_gpc_unk_0
},
{
nvc0_graph_init_setup_0
},
{
nvc0_graph_init_crstr_0
},
{
nvc1_graph_init_setup_1
},
{
nvc0_graph_init_zcull_0
},
{
nvd9_graph_init_gpm_0
},
{
nvf0_graph_init_gpc_unk_1
},
{
nvc0_graph_init_gcc_0
},
{
nvf0_graph_init_tpc_0
},
{
nvf0_graph_init_tpc_0
},
{
nvd7_graph_init_ppc_0
},
{
nvd7_graph_init_ppc_0
},
{
nve4_graph_init_be_0
},
{
nve4_graph_init_be_0
},
...
...
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