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Commit 97be8ab2 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'v4.16-next-dts64' of... 

Merge tag 'v4.16-next-dts64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt

Pull "ARM: mediatek: dts64 updates for v4.16-next" from Matthias Brugger:

- mt2712e add auxadc devcie

mt7622:
- fix clock bindings description
- add nodes for mmc, usb, SATA, PCI, ethernet, cpufreq, PMIC mt6380,
pinctrl, scpsys and clock devices

* tag 'v4.16-next-dts64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: mt2712: Add auxadc device node.
  dt-bindings: clock: mediatek: add missing required #reset-cells
  arm64: dts: mt7622: add mmc related device nodes
  arm64: dts: mt7622: add usb device nodes
  arm64: dts: mt7622: add SATA device nodes
  arm64: dts: mt7622: add PCIe device nodes
  arm64: dts: mt7622: add ethernet device nodes
  arm64: dts: mt7622: add flash related device nodes
  arm64: dts: mt7622: add SoC and peripheral related device nodes
  arm64: dts: mt7622: turn uart0 clock to real ones
  arm64: dts: mt7622: add cpufreq related device nodes
  arm64: dts: mt7622: add PMIC MT6380 related nodes
  arm64: dts: mt7622: add pinctrl related device nodes
  arm64: dts: mt7622: add power domain controller device nodes
  arm64: dts: mt7622: add clock controller device nodes
parents 00730c5b 5f599552
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Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
View file @ 97be8ab2
...@@ -9,6 +9,7 @@ Required Properties: ...@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-ethsys", "syscon" - "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon" - "mediatek,mt7622-ethsys", "syscon"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
- #reset-cells: Must be 1
The ethsys controller uses the common clk binding from The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt Documentation/devicetree/bindings/clock/clock-bindings.txt
......
Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
View file @ 97be8ab2
...@@ -8,6 +8,7 @@ Required Properties: ...@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be: - compatible: Should be:
- "mediatek,mt7622-pciesys", "syscon" - "mediatek,mt7622-pciesys", "syscon"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
- #reset-cells: Must be 1
The PCIESYS controller uses the common clk binding from The PCIESYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt Documentation/devicetree/bindings/clock/clock-bindings.txt
...@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 { ...@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon"; compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0 0x1a100800 0 0x1000>; reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>;
}; };
Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
View file @ 97be8ab2
...@@ -8,6 +8,7 @@ Required Properties: ...@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be: - compatible: Should be:
- "mediatek,mt7622-ssusbsys", "syscon" - "mediatek,mt7622-ssusbsys", "syscon"
- #clock-cells: Must be 1 - #clock-cells: Must be 1
- #reset-cells: Must be 1
The SSUSBSYS controller uses the common clk binding from The SSUSBSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt Documentation/devicetree/bindings/clock/clock-bindings.txt
...@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 { ...@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys", "syscon"; compatible = "mediatek,mt7622-ssusbsys", "syscon";
reg = <0 0x1a000000 0 0x1000>; reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>;
}; };
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
View file @ 97be8ab2
...@@ -41,6 +41,10 @@ cpus_fixed_vproc1: fixedregulator@1 { ...@@ -41,6 +41,10 @@ cpus_fixed_vproc1: fixedregulator@1 {
}; };
&auxadc {
status = "okay";
};
&cpu0 { &cpu0 {
proc-supply = <&cpus_fixed_vproc0>; proc-supply = <&cpus_fixed_vproc0>;
}; };
......
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View file @ 97be8ab2
...@@ -289,6 +289,15 @@ gic: interrupt-controller@10510000 { ...@@ -289,6 +289,15 @@ gic: interrupt-controller@10510000 {
(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
auxadc: adc@11001000 {
compatible = "mediatek,mt2712-auxadc";
reg = <0 0x11001000 0 0x1000>;
clocks = <&pericfg CLK_PERI_AUXADC>;
clock-names = "main";
#io-channel-cells = <1>;
status = "disabled";
};
uart0: serial@11002000 { uart0: serial@11002000 {
compatible = "mediatek,mt2712-uart", compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart"; "mediatek,mt6577-uart";
......
arch/arm64/boot/dts/mediatek/mt6380.dtsi 0 → 100644
View file @ 97be8ab2
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for MediaTek MT6380 regulator
*
* Copyright (c) 2018 MediaTek Inc.
* Author: Chenglin Xu <chenglin.xu@mediatek.com>
* Sean Wang <sean.wang@mediatek.com>
*/
&pwrap {
regulators {
compatible = "mediatek,mt6380-regulator";
mt6380_vcpu_reg: buck-vcore1 {
regulator-name = "vcore1";
regulator-min-microvolt = < 600000>;
regulator-max-microvolt = <1393750>;
regulator-ramp-delay = <6250>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vcore_reg: buck-vcore {
regulator-name = "vcore";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1393750>;
regulator-ramp-delay = <6250>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vrf_reg: buck-vrf {
regulator-name = "vrf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1575000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vm_reg: ldo-vm {
regulator-name = "vm";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1400000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6380_va_reg: ldo-va {
regulator-name = "va";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vphy_reg: ldo-vphy {
regulator-name = "vphy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vddr_reg: ldo-vddr {
regulator-name = "vddr";
regulator-min-microvolt = <1240000>;
regulator-max-microvolt = <1840000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
mt6380_vt_reg: ldo-vt {
regulator-name = "vt";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <0>;
regulator-always-on;
regulator-boot-on;
};
};
};
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View file @ 97be8ab2
...@@ -7,7 +7,11 @@ ...@@ -7,7 +7,11 @@
*/ */
/dts-v1/; /dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "mt7622.dtsi" #include "mt7622.dtsi"
#include "mt6380.dtsi"
/ { / {
model = "MediaTek MT7622 RFB1 board"; model = "MediaTek MT7622 RFB1 board";
...@@ -17,11 +21,476 @@ chosen { ...@@ -17,11 +21,476 @@ chosen {
bootargs = "console=ttyS0,115200n1"; bootargs = "console=ttyS0,115200n1";
}; };
cpus {
cpu@0 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
cpu@1 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
};
gpio-keys {
compatible = "gpio-keys-polled";
poll-interval = <100>;
factory {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 0 0>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 102 0>;
};
};
memory { memory {
reg = <0 0x40000000 0 0x3F000000>; reg = <0 0x40000000 0 0x3F000000>;
}; };
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
status = "okay";
pcie@0,0 {
status = "okay";
};
};
&pio {
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
function = "emmc", "emmc_rst";
groups = "emmc";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
*/
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
bias-pull-down;
};
};
emmc_pins_uhs: emmc-pins-uhs {
mux {
function = "emmc";
groups = "emmc";
};
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
drive-strength = <4>;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
drive-strength = <4>;
bias-pull-down;
};
};
eth_pins: eth-pins {
mux {
function = "eth";
groups = "mdc_mdio", "rgmii_via_gmac2";
};
};
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
groups = "i2c2_0";
};
};
i2s1_pins: i2s1-pins {
mux {
function = "i2s";
groups = "i2s_out_bclk_ws_mclk",
"i2s1_in_data",
"i2s1_out_data";
};
};
irrx_pins: irrx-pins {
mux {
function = "ir";
groups = "ir_1_rx";
};
};
irtx_pins: irtx-pins {
mux {
function = "ir";
groups = "ir_1_tx";
};
};
/* Parallel nand is shared pin with eMMC */
parallel_nand_pins: parallel-nand-pins {
mux {
function = "flash";
groups = "par_nand";
};
};
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie0_pad_perst",
"pcie0_1_waken",
"pcie0_1_clkreq";
};
};
pcie1_pins: pcie1-pins {
mux {
function = "pcie";
groups = "pcie1_pad_perst",
"pcie1_0_waken",
"pcie1_0_clkreq";
};
};
pmic_bus_pins: pmic-bus-pins {
mux {
function = "pmic";
groups = "pmic_bus";
};
};
pwm7_pins: pwm1-2-pins {
mux {
function = "pwm";
groups = "pwm_ch7_2";
};
};
wled_pins: wled-pins {
mux {
function = "led";
groups = "wled";
};
};
sd0_pins_default: sd0-pins-default {
mux {
function = "sd";
groups = "sd_0";
};
/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
* DAT2, DAT3, CMD, CLK for SD respectively.
*/
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
drive-strength = <8>;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
drive-strength = <12>;
bias-pull-down;
};
conf-cd {
pins = "TXD3";
bias-pull-up;
};
};
sd0_pins_uhs: sd0-pins-uhs {
mux {
function = "sd";
groups = "sd_0";
};
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
bias-pull-down;
};
};
/* Serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
};
spic0_pins: spic0-pins {
mux {
function = "spi";
groups = "spic0_0";
};
};
spic1_pins: spic1-pins {
mux {
function = "spi";
groups = "spic1_0";
};
};
/* SPI-NOR is shared pin with serial NAND */
spi_nor_pins: spi-nor-pins {
mux {
function = "flash";
groups = "spi_nor";
};
};
/* serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0_0_tx_rx" ;
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2_1_tx_rx" ;
};
};
watchdog_pins: watchdog-pins {
mux {
function = "watchdog";
groups = "watchdog";
};
};
};
&bch {
status = "disabled";
};
&btif {
status = "okay";
};
&cir {
pinctrl-names = "default";
pinctrl-0 = <&irrx_pins>;
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
status = "okay";
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-handle = <&phy5>;
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
phy5: ethernet-phy@5 {
reg = <5>;
phy-mode = "sgmii";
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_uhs>;
status = "okay";
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
non-removable;
};
&mmc1 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&sd0_pins_default>;
pinctrl-1 = <&sd0_pins_uhs>;
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <1>;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};
&nandc {
pinctrl-names = "default";
pinctrl-0 = <&parallel_nand_pins>;
status = "disabled";
};
&nor_flash {
pinctrl-names = "default";
pinctrl-0 = <&spi_nor_pins>;
status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm7_pins>;
status = "okay";
};
&pwrap {
pinctrl-names = "default";
pinctrl-0 = <&pmic_bus_pins>;
status = "okay";
};
&sata {
status = "okay";
};
&sata_phy {
status = "okay";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spic0_pins>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic1_pins>;
status = "okay";
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&u3phy {
status = "okay";
}; };
&uart0 { &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;
status = "okay"; status = "okay";
}; };
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View file @ 97be8ab2
...@@ -8,6 +8,11 @@ ...@@ -8,6 +8,11 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7622-clk.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/reset/mt7622-reset.h>
#include <dt-bindings/thermal/thermal.h>
/ { / {
compatible = "mediatek,mt7622"; compatible = "mediatek,mt7622";
...@@ -15,6 +20,50 @@ / { ...@@ -15,6 +20,50 @@ / {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-300000000 {
opp-hz = /bits/ 64 <30000000>;
opp-microvolt = <950000>;
};
opp-437500000 {
opp-hz = /bits/ 64 <437500000>;
opp-microvolt = <1000000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1050000>;
};
opp-812500000 {
opp-hz = /bits/ 64 <812500000>;
opp-microvolt = <1100000>;
};
opp-1025000000 {
opp-hz = /bits/ 64 <1025000000>;
opp-microvolt = <1150000>;
};
opp-1137500000 {
opp-hz = /bits/ 64 <1137500000>;
opp-microvolt = <1200000>;
};
opp-1262500000 {
opp-hz = /bits/ 64 <1262500000>;
opp-microvolt = <1250000>;
};
opp-1350000000 {
opp-hz = /bits/ 64 <1350000000>;
opp-microvolt = <1310000>;
};
};
cpus { cpus {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <0>; #size-cells = <0>;
...@@ -23,6 +72,11 @@ cpu0: cpu@0 { ...@@ -23,6 +72,11 @@ cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>; reg = <0x0 0x0>;
clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
enable-method = "psci"; enable-method = "psci";
clock-frequency = <1300000000>; clock-frequency = <1300000000>;
}; };
...@@ -31,21 +85,26 @@ cpu1: cpu@1 { ...@@ -31,21 +85,26 @@ cpu1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>; reg = <0x0 0x1>;
clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci"; enable-method = "psci";
clock-frequency = <1300000000>; clock-frequency = <1300000000>;
}; };
}; };
uart_clk: dummy25m { pwrap_clk: dummy40m {
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <25000000>;
}; };
bus_clk: dummy280m { clk25m: oscillator {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <280000000>; clock-frequency = <25000000>;
clock-output-names = "clkxtal";
}; };
psci { psci {
...@@ -65,6 +124,58 @@ secmon_reserved: secmon@43000000 { ...@@ -65,6 +124,58 @@ secmon_reserved: secmon@43000000 {
}; };
}; };
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&thermal 0>;
trips {
cpu_passive: cpu-passive {
temperature = <47000>;
hysteresis = <2000>;
type = "passive";
};
cpu_active: cpu-active {
temperature = <67000>;
hysteresis = <2000>;
type = "active";
};
cpu_hot: cpu-hot {
temperature = <87000>;
hysteresis = <2000>;
type = "hot";
};
cpu-crit {
temperature = <107000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_passive>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_active>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map2 {
trip = <&cpu_hot>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
...@@ -78,6 +189,58 @@ IRQ_TYPE_LEVEL_HIGH)>, ...@@ -78,6 +189,58 @@ IRQ_TYPE_LEVEL_HIGH)>,
IRQ_TYPE_LEVEL_HIGH)>; IRQ_TYPE_LEVEL_HIGH)>;
}; };
infracfg: infracfg@10000000 {
compatible = "mediatek,mt7622-infracfg",
"syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pwrap: pwrap@10001000 {
compatible = "mediatek,mt7622-pwrap";
reg = <0 0x10001000 0 0x250>;
reg-names = "pwrap";
clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
clock-names = "spi", "wrap";
resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
reset-names = "pwrap";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
pericfg: pericfg@10002000 {
compatible = "mediatek,mt7622-pericfg",
"syscon";
reg = <0 0x10002000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
scpsys: scpsys@10006000 {
compatible = "mediatek,mt7622-scpsys",
"syscon";
#power-domain-cells = <1>;
reg = <0 0x10006000 0 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
infracfg = <&infracfg>;
clocks = <&topckgen CLK_TOP_HIF_SEL>;
clock-names = "hif_sel";
};
cir: cir@10009000 {
compatible = "mediatek,mt7622-cir";
reg = <0 0x10009000 0 0x1000>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_IRRX_PD>,
<&topckgen CLK_TOP_AXI_SEL>;
clock-names = "clk", "bus";
status = "disabled";
};
sysirq: interrupt-controller@10200620 { sysirq: interrupt-controller@10200620 {
compatible = "mediatek,mt7622-sysirq", compatible = "mediatek,mt7622-sysirq",
"mediatek,mt6577-sysirq"; "mediatek,mt6577-sysirq";
...@@ -87,6 +250,62 @@ sysirq: interrupt-controller@10200620 { ...@@ -87,6 +250,62 @@ sysirq: interrupt-controller@10200620 {
reg = <0 0x10200620 0 0x20>; reg = <0 0x10200620 0 0x20>;
}; };
efuse: efuse@10206000 {
compatible = "mediatek,mt7622-efuse",
"mediatek,efuse";
reg = <0 0x10206000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
thermal_calibration: calib@198 {
reg = <0x198 0xc>;
};
};
apmixedsys: apmixedsys@10209000 {
compatible = "mediatek,mt7622-apmixedsys",
"syscon";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
topckgen: topckgen@10210000 {
compatible = "mediatek,mt7622-topckgen",
"syscon";
reg = <0 0x10210000 0 0x1000>;
#clock-cells = <1>;
};
rng: rng@1020f000 {
compatible = "mediatek,mt7622-rng",
"mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x1000>;
clocks = <&infracfg CLK_INFRA_TRNG>;
clock-names = "rng";
};
pio: pinctrl@10211000 {
compatible = "mediatek,mt7622-pinctrl";
reg = <0 0x10211000 0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
watchdog: watchdog@10212000 {
compatible = "mediatek,mt7622-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x10212000 0 0x800>;
};
rtc: rtc@10212800 {
compatible = "mediatek,mt7622-rtc",
"mediatek,soc-rtc";
reg = <0 0x10212800 0 0x200>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_RTC>;
clock-names = "rtc";
};
gic: interrupt-controller@10300000 { gic: interrupt-controller@10300000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
interrupt-controller; interrupt-controller;
...@@ -98,13 +317,459 @@ gic: interrupt-controller@10300000 { ...@@ -98,13 +317,459 @@ gic: interrupt-controller@10300000 {
<0 0x10360000 0 0x2000>; <0 0x10360000 0 0x2000>;
}; };
auxadc: adc@11001000 {
compatible = "mediatek,mt7622-auxadc";
reg = <0 0x11001000 0 0x1000>;
clocks = <&pericfg CLK_PERI_AUXADC_PD>;
clock-names = "main";
#io-channel-cells = <1>;
};
uart0: serial@11002000 { uart0: serial@11002000 {
compatible = "mediatek,mt7622-uart", compatible = "mediatek,mt7622-uart",
"mediatek,mt6577-uart"; "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>; reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>, <&bus_clk>; clocks = <&topckgen CLK_TOP_UART_SEL>,
<&pericfg CLK_PERI_UART1_PD>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt7622-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&pericfg CLK_PERI_UART1_PD>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt7622-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&pericfg CLK_PERI_UART2_PD>;
clock-names = "baud", "bus";
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt7622-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&pericfg CLK_PERI_UART3_PD>;
clock-names = "baud", "bus";
status = "disabled";
};
pwm: pwm@11006000 {
compatible = "mediatek,mt7622-pwm";
reg = <0 0x11006000 0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_PWM_SEL>,
<&pericfg CLK_PERI_PWM_PD>,
<&pericfg CLK_PERI_PWM1_PD>,
<&pericfg CLK_PERI_PWM2_PD>,
<&pericfg CLK_PERI_PWM3_PD>,
<&pericfg CLK_PERI_PWM4_PD>,
<&pericfg CLK_PERI_PWM5_PD>,
<&pericfg CLK_PERI_PWM6_PD>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
"pwm5", "pwm6";
status = "disabled";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt7622-i2c";
reg = <0 0x11007000 0 0x90>,
<0 0x11000100 0 0x80>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
clock-div = <16>;
clocks = <&pericfg CLK_PERI_I2C0_PD>,
<&pericfg CLK_PERI_AP_DMA_PD>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt7622-i2c";
reg = <0 0x11008000 0 0x90>,
<0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
clock-div = <16>;
clocks = <&pericfg CLK_PERI_I2C1_PD>,
<&pericfg CLK_PERI_AP_DMA_PD>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11009000 {
compatible = "mediatek,mt7622-i2c";
reg = <0 0x11009000 0 0x90>,
<0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
clock-div = <16>;
clocks = <&pericfg CLK_PERI_I2C2_PD>,
<&pericfg CLK_PERI_AP_DMA_PD>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@1100a000 {
compatible = "mediatek,mt7622-spi";
reg = <0 0x1100a000 0 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
<&topckgen CLK_TOP_SPI0_SEL>,
<&pericfg CLK_PERI_SPI0_PD>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
thermal: thermal@1100b000 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt7622-thermal";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_THERM_PD>,
<&pericfg CLK_PERI_AUXADC_PD>;
clock-names = "therm", "auxadc";
resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
reset-names = "therm";
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration>;
nvmem-cell-names = "calibration-data";
};
btif: serial@1100c000 {
compatible = "mediatek,mt7622-btif",
"mediatek,mtk-btif";
reg = <0 0x1100c000 0 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_BTIF_PD>;
clock-names = "main";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
nandc: nfi@1100d000 {
compatible = "mediatek,mt7622-nfc";
reg = <0 0x1100D000 0 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_NFI_PD>,
<&pericfg CLK_PERI_SNFI_PD>;
clock-names = "nfi_clk", "pad_clk";
ecc-engine = <&bch>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
bch: ecc@1100e000 {
compatible = "mediatek,mt7622-ecc";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_NFIECC_PD>;
clock-names = "nfiecc_clk";
status = "disabled";
};
nor_flash: spi@11014000 {
compatible = "mediatek,mt7622-nor",
"mediatek,mt8173-nor";
reg = <0 0x11014000 0 0xe0>;
clocks = <&pericfg CLK_PERI_FLASH_PD>,
<&topckgen CLK_TOP_FLASH_SEL>;
clock-names = "spi", "sf";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@11016000 {
compatible = "mediatek,mt7622-spi";
reg = <0 0x11016000 0 0x100>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
<&topckgen CLK_TOP_SPI1_SEL>,
<&pericfg CLK_PERI_SPI1_PD>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart4: serial@11019000 {
compatible = "mediatek,mt7622-uart",
"mediatek,mt6577-uart";
reg = <0 0x11019000 0 0x400>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UART_SEL>,
<&pericfg CLK_PERI_UART4_PD>;
clock-names = "baud", "bus"; clock-names = "baud", "bus";
status = "disabled"; status = "disabled";
}; };
mmc0: mmc@11230000 {
compatible = "mediatek,mt7622-mmc";
reg = <0 0x11230000 0 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
<&topckgen CLK_TOP_MSDC50_0_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt7622-mmc";
reg = <0 0x11240000 0 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
<&topckgen CLK_TOP_AXI_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys",
"syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
ssusb: usb@1a0c0000 {
compatible = "mediatek,mt7622-xhci",
"mediatek,mtk-xhci";
reg = <0 0x1a0c0000 0 0x01000>,
<0 0x1a0c4700 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
<&ssusbsys CLK_SSUSB_REF_EN>,
<&ssusbsys CLK_SSUSB_MCU_EN>,
<&ssusbsys CLK_SSUSB_DMA_EN>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>,
<&u2port1 PHY_TYPE_USB2>;
status = "disabled";
};
u3phy: usb-phy@1a0c4000 {
compatible = "mediatek,mt7622-u3phy",
"mediatek,generic-tphy-v1";
reg = <0 0x1a0c4000 0 0x700>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
u2port0: usb-phy@1a0c4800 {
reg = <0 0x1a0c4800 0 0x0100>;
#phy-cells = <1>;
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
clock-names = "ref";
};
u3port0: usb-phy@1a0c4900 {
reg = <0 0x1a0c4900 0 0x0700>;
#phy-cells = <1>;
clocks = <&clk25m>;
clock-names = "ref";
};
u2port1: usb-phy@1a0c5000 {
reg = <0 0x1a0c5000 0 0x0100>;
#phy-cells = <1>;
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
clock-names = "ref";
};
};
pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys",
"syscon";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pcie: pcie@1a140000 {
compatible = "mediatek,mt7622-pcie";
device_type = "pci";
reg = <0 0x1a140000 0 0x1000>,
<0 0x1a143000 0 0x1000>,
<0 0x1a145000 0 0x1000>;
reg-names = "subsys", "port0", "port1";
#address-cells = <3>;
#size-cells = <2>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
<&pciesys CLK_PCIE_P1_MAC_EN>,
<&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P0_AHB_EN>,
<&pciesys CLK_PCIE_P0_AUX_EN>,
<&pciesys CLK_PCIE_P1_AUX_EN>,
<&pciesys CLK_PCIE_P0_AXI_EN>,
<&pciesys CLK_PCIE_P1_AXI_EN>,
<&pciesys CLK_PCIE_P0_OBFF_EN>,
<&pciesys CLK_PCIE_P1_OBFF_EN>,
<&pciesys CLK_PCIE_P0_PIPE_EN>,
<&pciesys CLK_PCIE_P1_PIPE_EN>;
clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
"aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
"obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
status = "disabled";
pcie0: pcie@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
status = "disabled";
num-lanes = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
status = "disabled";
num-lanes = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
sata: sata@1a200000 {
compatible = "mediatek,mt7622-ahci",
"mediatek,mtk-ahci";
reg = <0 0x1a200000 0 0x1100>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
clocks = <&pciesys CLK_SATA_AHB_EN>,
<&pciesys CLK_SATA_AXI_EN>,
<&pciesys CLK_SATA_ASIC_EN>,
<&pciesys CLK_SATA_RBC_EN>,
<&pciesys CLK_SATA_PM_EN>;
clock-names = "ahb", "axi", "asic", "rbc", "pm";
phys = <&sata_port PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
<&pciesys MT7622_SATA_PHY_SW_RST>,
<&pciesys MT7622_SATA_PHY_REG_RST>;
reset-names = "axi", "sw", "reg";
mediatek,phy-mode = <&pciesys>;
status = "disabled";
};
sata_phy: sata-phy@1a243000 {
compatible = "mediatek,generic-tphy-v1";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
sata_port: sata-phy@1a243000 {
reg = <0 0x1a243000 0 0x0100>;
clocks = <&topckgen CLK_TOP_ETH_500M>;
clock-names = "ref";
#phy-cells = <1>;
};
};
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7622-ethsys",
"syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
eth: ethernet@1b100000 {
compatible = "mediatek,mt7622-eth",
"mediatek,mt2701-eth",
"syscon";
reg = <0 0x1b100000 0 0x20000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_ETH_SEL>,
<&ethsys CLK_ETH_ESW_EN>,
<&ethsys CLK_ETH_GP0_EN>,
<&ethsys CLK_ETH_GP1_EN>,
<&ethsys CLK_ETH_GP2_EN>,
<&sgmiisys CLK_SGMII_TX250M_EN>,
<&sgmiisys CLK_SGMII_RX250M_EN>,
<&sgmiisys CLK_SGMII_CDR_REF>,
<&sgmiisys CLK_SGMII_CDR_FB>,
<&topckgen CLK_TOP_SGMIIPLL>,
<&apmixedsys CLK_APMIXED_ETH2PLL>;
clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
"sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
"eth2pll";
power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
mediatek,ethsys = <&ethsys>;
mediatek,sgmiisys = <&sgmiisys>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sgmiisys: sgmiisys@1b128000 {
compatible = "mediatek,mt7622-sgmiisys",
"syscon";
reg = <0 0x1b128000 0 0x1000>;
#clock-cells = <1>;
};
}; };
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