Commit 98fb2b95 authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Stephen Boyd

clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock

In the user manual of A33 SoC, the bit 22 and 23 of pll-mipi control
register is called "LDO{1,2}_EN", and according to the BSP source code
from Allwinner [1], the LDOs are enabled during the clock's enabling
process.

The clock failed to generate output if the two LDOs are not enabled.

Add the two bits to the clock's gate bits, so that the LDOs are enabled
when the PLL is enabled.

[1] https://github.com/allwinner-zh/linux-3.4-sunxi/blob/master/drivers/clk/sunxi/clk-sun8iw5.c#L429

Fixes: d05c748b ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.xyz>
Acked-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 95881a54
...@@ -131,7 +131,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", ...@@ -131,7 +131,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
8, 4, /* N */ 8, 4, /* N */
4, 2, /* K */ 4, 2, /* K */
0, 4, /* M */ 0, 4, /* M */
BIT(31), /* gate */ BIT(31) | BIT(23) | BIT(22), /* gate */
BIT(28), /* lock */ BIT(28), /* lock */
CLK_SET_RATE_UNGATE); CLK_SET_RATE_UNGATE);
......
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