drm/amd/powerplay: expose supported clock domains only through sysfs

Do not expose those unsupported clock domains through sysfs on
Arcturus.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

@@ -2828,12 +2828,14 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 			DRM_ERROR("failed to create device file pp_dpm_socclk\n");
 			return ret;
 		}
+		if (adev->asic_type != CHIP_ARCTURUS) {
 			ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
 			if (ret) {
 				DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
 				return ret;
 			}
 		}
+	}
 	if (adev->asic_type >= CHIP_VEGA20) {
 		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
 		if (ret) {
@@ -2841,11 +2843,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 			return ret;
 		}
 	}
+	if (adev->asic_type != CHIP_ARCTURUS) {
 		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
 		if (ret) {
 			DRM_ERROR("failed to create device file pp_dpm_pcie\n");
 			return ret;
 		}
+	}
 	ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
 	if (ret) {
 		DRM_ERROR("failed to create device file pp_sclk_od\n");
@@ -2948,8 +2952,10 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 	device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
 	if (adev->asic_type >= CHIP_VEGA10) {
 		device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
+		if (adev->asic_type != CHIP_ARCTURUS)
 			device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
 	}
+	if (adev->asic_type != CHIP_ARCTURUS)
 		device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
 	if (adev->asic_type >= CHIP_VEGA20)
 		device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);