Commit 9ca3ba01 authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter

drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpll

Prepare chv_find_best_dpll to be used for BXT too, where we want to
consider the error between target and calculated frequency too when
choosing a better PLL configuration.

No functional change.
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 24be4e46
...@@ -786,6 +786,16 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, ...@@ -786,6 +786,16 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
unsigned int best_error_ppm, unsigned int best_error_ppm,
unsigned int *error_ppm) unsigned int *error_ppm)
{ {
/*
* For CHV ignore the error and consider only the P value.
* Prefer a bigger P value based on HW requirements.
*/
if (IS_CHERRYVIEW(dev)) {
*error_ppm = 0;
return calculated_clock->p > best_clock->p;
}
if (WARN_ON_ONCE(!target_freq)) if (WARN_ON_ONCE(!target_freq))
return false; return false;
...@@ -864,11 +874,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, ...@@ -864,11 +874,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
intel_clock_t *best_clock) intel_clock_t *best_clock)
{ {
struct drm_device *dev = crtc->base.dev; struct drm_device *dev = crtc->base.dev;
unsigned int best_error_ppm;
intel_clock_t clock; intel_clock_t clock;
uint64_t m2; uint64_t m2;
int found = false; int found = false;
memset(best_clock, 0, sizeof(*best_clock)); memset(best_clock, 0, sizeof(*best_clock));
best_error_ppm = 1000000;
/* /*
* Based on hardware doc, the n always set to 1, and m1 always * Based on hardware doc, the n always set to 1, and m1 always
...@@ -882,6 +894,7 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, ...@@ -882,6 +894,7 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
for (clock.p2 = limit->p2.p2_fast; for (clock.p2 = limit->p2.p2_fast;
clock.p2 >= limit->p2.p2_slow; clock.p2 >= limit->p2.p2_slow;
clock.p2 -= clock.p2 > 10 ? 2 : 1) { clock.p2 -= clock.p2 > 10 ? 2 : 1) {
unsigned int error_ppm;
clock.p = clock.p1 * clock.p2; clock.p = clock.p1 * clock.p2;
...@@ -898,12 +911,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, ...@@ -898,12 +911,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
if (!intel_PLL_is_valid(dev, limit, &clock)) if (!intel_PLL_is_valid(dev, limit, &clock))
continue; continue;
/* based on hardware requirement, prefer bigger p if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
*/ best_error_ppm, &error_ppm))
if (clock.p > best_clock->p) { continue;
*best_clock = clock;
found = true; *best_clock = clock;
} best_error_ppm = error_ppm;
found = true;
} }
} }
......
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