Commit 9d40f423 authored by Joel Stanley's avatar Joel Stanley

Merge branch 'aspeed-clk-for-v5.5'

This contains the dt-bindings headers for the ethernet clocks.
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
parents 8737481e d8d9ad83
...@@ -39,6 +39,8 @@ ...@@ -39,6 +39,8 @@
#define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_BCLK 33
#define ASPEED_CLK_MPLL 34 #define ASPEED_CLK_MPLL 34
#define ASPEED_CLK_24M 35 #define ASPEED_CLK_24M 35
#define ASPEED_CLK_MAC1RCLK 36
#define ASPEED_CLK_MAC2RCLK 37
#define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_XDMA 0
#define ASPEED_RESET_MCTP 1 #define ASPEED_RESET_MCTP 1
......
...@@ -83,6 +83,10 @@ ...@@ -83,6 +83,10 @@
#define ASPEED_CLK_MAC12 64 #define ASPEED_CLK_MAC12 64
#define ASPEED_CLK_MAC34 65 #define ASPEED_CLK_MAC34 65
#define ASPEED_CLK_USBPHY_40M 66 #define ASPEED_CLK_USBPHY_40M 66
#define ASPEED_CLK_MAC1RCLK 67
#define ASPEED_CLK_MAC2RCLK 68
#define ASPEED_CLK_MAC3RCLK 69
#define ASPEED_CLK_MAC4RCLK 70
/* Only list resets here that are not part of a gate */ /* Only list resets here that are not part of a gate */
#define ASPEED_RESET_ADC 55 #define ASPEED_RESET_ADC 55
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment