Commit 9d9541d4 authored by Boris Brezillon's avatar Boris Brezillon Committed by Greg Kroah-Hartman

clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk

commit 68af4fa8 upstream.

bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
to zero when disabling the clock.

Make sure we preserve this value by reading the previous a2w_reg value
first and ORing the result with A2W_PLL_CHANNEL_DISABLE.
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 41691b88 ("clk: bcm2835: Add support for programming the audio domain clocks")
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e01b04be
......@@ -1082,7 +1082,9 @@ static void bcm2835_pll_divider_off(struct clk_hw *hw)
cprman_write(cprman, data->cm_reg,
(cprman_read(cprman, data->cm_reg) &
~data->load_mask) | data->hold_mask);
cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE);
cprman_write(cprman, data->a2w_reg,
cprman_read(cprman, data->a2w_reg) |
A2W_PLL_CHANNEL_DISABLE);
spin_unlock(&cprman->regs_lock);
}
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment