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Commit 9de194ff authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-dt2-for-v4.10' of... 

Merge tag 'renesas-dt2-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Second Round of Renesas ARM Based SoC DT Updates for v4.10" from Simon Horman:

Enhancements:
* Add device nodes for PRR
* Add r8a7745 SoC and sk-rzg1e board
* Add r8a7743 SoC and sk-rzg1m board
* Enable SDR-104 and I2C demuxer on alt, koelsch and lager boards

Corrections:
* Use SYSC "always-on" PM Domain for sound on r8a7794 SoC
* Correct hsusb parent clock on r8a7794 SoC
* Correct PFC names for DU on alt board

* tag 'renesas-dt2-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (33 commits)
  ARM: dts: r8a7794: Add device node for PRR
  ARM: dts: r8a7793: Add device node for PRR
  ARM: dts: r8a7792: Add device node for PRR
  ARM: dts: r8a7791: Add device node for PRR
  ARM: dts: r8a7790: Add device node for PRR
  ARM: dts: r8a7779: Add device node for PRR
  ARM: dts: r8a73a4: Add device node for PRR
  ARM: dts: sk-rzg1e: add Ether support
  ARM: dts: sk-rzg1e: initial device tree
  ARM: dts: r8a7745: add IRQC support
  ARM: dts: r8a7745: add Ether support
  ARM: dts: r8a7745: add [H]SCIF{|A|B} support
  ARM: dts: r8a7745: add SYS-DMAC support
  ARM: dts: r8a7745: initial SoC device tree
  ARM: dts: sk-rzg1m: add Ether support
  ARM: dts: sk-rzg1m: initial device tree
  ARM: dts: r8a7743: add IRQC support
  ARM: dts: r8a7743: add Ether support
  ARM: dts: r8a7743: add [H]SCIF{A|B} support
  ARM: dts: r8a7743: add SYS-DMAC support
  ...
parents 0b416097 2357adb6
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Showing with 1270 additions and 12 deletions
arch/arm/boot/dts/Makefile
View file @ 9de194ff
......@@ -694,6 +694,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r7s72100-rskrza1.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
......
arch/arm/boot/dts/r8a73a4.dtsi
View file @ 9de194ff
......@@ -751,6 +751,11 @@ R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
};
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
......
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts 0 → 100644
View file @ 9de194ff
/*
* Device Tree Source for the SK-RZG1M board
*
* Copyright (C) 2016 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7743.dtsi"
/ {
model = "SK-RZG1M";
compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
aliases {
serial0 = &scif0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
memory@200000000 {
device_type = "memory";
reg = <2 0x00000000 0 0x40000000>;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&scif0 {
status = "okay";
};
&ether {
phy-handle = <&phy1>;
renesas,ether-link-active-low;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&irqc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
};
};
arch/arm/boot/dts/r8a7743.dtsi 0 → 100644
View file @ 9de194ff
This diff is collapsed.
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts 0 → 100644
View file @ 9de194ff
/*
* Device Tree Source for the SK-RZG1E board
*
* Copyright (C) 2016 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7745.dtsi"
/ {
model = "SK-RZG1E";
compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
aliases {
serial0 = &scif2;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&scif2 {
status = "okay";
};
&ether {
phy-handle = <&phy1>;
renesas,ether-link-active-low;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&irqc>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
};
};
arch/arm/boot/dts/r8a7745.dtsi 0 → 100644
View file @ 9de194ff
This diff is collapsed.
arch/arm/boot/dts/r8a7779.dtsi
View file @ 9de194ff
......@@ -590,6 +590,11 @@ R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
};
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0xff000044 4>;
};
sysc: system-controller@ffd85000 {
compatible = "renesas,r8a7779-sysc";
reg = <0xffd85000 0x0200>;
......
arch/arm/boot/dts/r8a7790-lager.dts
View file @ 9de194ff
......@@ -50,7 +50,9 @@ / {
aliases {
serial0 = &scif0;
serial1 = &scifa1;
i2c8 = "i2cexio";
i2c8 = &gpioi2c1;
i2c10 = &i2cexio0;
i2c11 = &i2cexio1;
};
chosen {
......@@ -265,6 +267,17 @@ x13_clk: x13-clock {
clock-frequency = <148500000>;
};
gpioi2c1: i2c-8 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
&gpio1 16 GPIO_ACTIVE_HIGH /* scl */
>;
i2c-gpio,delay-us = <5>;
};
/*
* IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
* We use the I2C demuxer, so the desired IP core can be selected at runtime
......@@ -273,11 +286,26 @@ x13_clk: x13-clock {
* bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
* instantiate the slave device at runtime according to the documentation.
* You can then communicate with the slave via IIC3.
*
* IIC0/I2C0 does not appear to support fallback to GPIO.
*/
i2cexio: i2c-8 {
i2cexio0: i2c-10 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&iic0>, <&i2c0>;
i2c-bus-name = "i2c-exio";
i2c-bus-name = "i2c-exio0";
#address-cells = <1>;
#size-cells = <0>;
};
/*
* IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
* This is similar to the arangement described for i2cexio0 (above)
* with a fallback to GPIO also provided.
*/
i2cexio1: i2c-11 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
i2c-bus-name = "i2c-exio1";
#address-cells = <1>;
#size-cells = <0>;
};
......@@ -403,6 +431,11 @@ iic0_pins: iic0 {
function = "iic0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
iic1_pins: iic1 {
groups = "iic1";
function = "iic1";
......@@ -575,6 +608,7 @@ &sdhi0 {
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
......@@ -596,18 +630,22 @@ &cpu0 {
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "i2c-exio";
pinctrl-names = "i2c-exio0";
};
&iic0 {
pinctrl-0 = <&iic0_pins>;
pinctrl-names = "i2c-exio";
pinctrl-names = "i2c-exio0";
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "i2c-exio1";
};
&iic1 {
status = "okay";
pinctrl-0 = <&iic1_pins>;
pinctrl-names = "default";
pinctrl-names = "i2c-exio1";
};
&iic2 {
......
arch/arm/boot/dts/r8a7790.dtsi
View file @ 9de194ff
......@@ -1471,6 +1471,11 @@ R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_S
};
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7790-sysc";
reg = <0 0xe6180000 0 0x0200>;
......
arch/arm/boot/dts/r8a7791-koelsch.dts
View file @ 9de194ff
......@@ -50,6 +50,8 @@ / {
aliases {
serial0 = &scif0;
serial1 = &scif1;
i2c9 = &gpioi2c1;
i2c12 = &i2cexio1;
};
chosen {
......@@ -298,6 +300,29 @@ x13_clk: x13-clock {
#clock-cells = <0>;
clock-frequency = <148500000>;
};
gpioi2c1: i2c-9 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
gpios = <&gpio7 16 GPIO_ACTIVE_HIGH /* sda */
&gpio7 15 GPIO_ACTIVE_HIGH /* scl */
>;
i2c-gpio,delay-us = <5>;
};
/*
* I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA).
* A fallback to GPIO is provided.
*/
i2cexio1: i2c-12 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c1>, <&gpioi2c1>;
i2c-bus-name = "i2c-exio1";
#address-cells = <1>;
#size-cells = <0>;
};
};
&du {
......@@ -333,6 +358,11 @@ &pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
i2c2_pins: i2c2 {
groups = "i2c2";
function = "i2c2";
......@@ -499,6 +529,7 @@ &sdhi0 {
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
......@@ -581,6 +612,11 @@ pmic: pmic@0 {
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "i2c-exio1";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
......
arch/arm/boot/dts/r8a7791.dtsi
View file @ 9de194ff
......@@ -1485,6 +1485,11 @@ R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
};
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7791-sysc";
reg = <0 0xe6180000 0 0x0200>;
......
arch/arm/boot/dts/r8a7792.dtsi
View file @ 9de194ff
......@@ -120,6 +120,11 @@ IRQ_TYPE_LEVEL_LOW)>,
IRQ_TYPE_LEVEL_LOW)>;
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7792-sysc";
reg = <0 0xe6180000 0 0x0200>;
......
arch/arm/boot/dts/r8a7793.dtsi
View file @ 9de194ff
......@@ -1306,6 +1306,11 @@ R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
};
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7793-sysc";
reg = <0 0xe6180000 0 0x0200>;
......
arch/arm/boot/dts/r8a7794-alt.dts
View file @ 9de194ff
......@@ -18,6 +18,8 @@ / {
aliases {
serial0 = &scif2;
i2c10 = &gpioi2c4;
i2c12 = &i2cexio4;
};
chosen {
......@@ -135,6 +137,29 @@ x13_clk: x13-clock {
#clock-cells = <0>;
clock-frequency = <148500000>;
};
gpioi2c4: i2c-10 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
status = "disabled";
gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
&gpio4 8 GPIO_ACTIVE_HIGH /* scl */
>;
i2c-gpio,delay-us = <5>;
};
/*
* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
* A fallback to GPIO is provided.
*/
i2cexio4: i2c-14 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c4>, <&gpioi2c4>;
i2c-bus-name = "i2c-exio4";
#address-cells = <1>;
#size-cells = <0>;
};
};
&du {
......@@ -165,8 +190,8 @@ &pfc {
pinctrl-names = "default";
du_pins: du {
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
function = "du";
groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
function = "du1";
};
scif2_pins: scif2 {
......@@ -194,6 +219,11 @@ i2c1_pins: i2c1 {
function = "i2c1";
};
i2c4_pins: i2c4 {
groups = "i2c4";
function = "i2c4";
};
vin0_pins: vin0 {
groups = "vin0_data8", "vin0_clk";
function = "vin0";
......@@ -277,6 +307,7 @@ &sdhi0 {
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
......@@ -314,6 +345,11 @@ adv7180: endpoint {
};
};
&i2c4 {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "i2c-exio4";
};
&vin0 {
status = "okay";
pinctrl-0 = <&vin0_pins>;
......
arch/arm/boot/dts/r8a7794.dtsi
View file @ 9de194ff
......@@ -319,7 +319,7 @@ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
"ch12";
clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
#dma-cells = <1>;
dma-channels = <13>;
};
......@@ -1262,7 +1262,7 @@ mstp5_clks: mstp5_clks@e6150144 {
mstp7_clks: mstp7_clks@e615014c {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
clocks = <&mp_clk>, <&mp_clk>,
clocks = <&mp_clk>, <&hp_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&zx_clk>;
......@@ -1377,6 +1377,11 @@ R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
};
};
prr: chipid@ff000044 {
compatible = "renesas,prr";
reg = <0 0xff000044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7794-sysc";
reg = <0 0xe6180000 0 0x0200>;
......@@ -1485,7 +1490,7 @@ rcar_sound: sound@ec500000 {
"mix.0", "mix.1",
"dvc.0", "dvc.1",
"clk_a", "clk_b", "clk_c", "clk_i";
power-domains = <&cpg_clocks>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
status = "disabled";
......
include/dt-bindings/power/r8a7743-sysc.h 0 → 100644
View file @ 9de194ff
/*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_POWER_R8A7743_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7743_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7743_PD_CA15_CPU0 0
#define R8A7743_PD_CA15_CPU1 1
#define R8A7743_PD_CA15_SCU 12
#define R8A7743_PD_SGX 20
/* Always-on power area */
#define R8A7743_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7743_SYSC_H__ */
include/dt-bindings/power/r8a7745-sysc.h 0 → 100644
View file @ 9de194ff
/*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_POWER_R8A7745_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7745_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7745_PD_CA7_CPU0 5
#define R8A7745_PD_CA7_CPU1 6
#define R8A7745_PD_SGX 20
#define R8A7745_PD_CA7_SCU 21
/* Always-on power area */
#define R8A7745_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7745_SYSC_H__ */
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