Commit 9e53481e authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle

MIPS: Malta: Let PIIX4 respond to PCI special cycles

This patch enables the PIIX4 to respond to special cycles on the PCI
bus. One such special cycle must be used in order to enter a suspend
state, and if response to it is not enabled then the suspend state will
never be entered.
Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6904/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b6911bba
...@@ -68,6 +68,7 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev) ...@@ -68,6 +68,7 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
{ {
unsigned char reg_val; unsigned char reg_val;
u32 reg_val32; u32 reg_val32;
u16 reg_val16;
/* PIIX PIRQC[A:D] irq mappings */ /* PIIX PIRQC[A:D] irq mappings */
static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = { static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
0, 0, 0, 3, 0, 0, 0, 3,
...@@ -107,6 +108,11 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev) ...@@ -107,6 +108,11 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
/* Enable response to special cycles */
pci_read_config_word(pdev, PCI_COMMAND, &reg_val16);
pci_write_config_word(pdev, PCI_COMMAND,
reg_val16 | PCI_COMMAND_SPECIAL);
} }
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
......
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