Skip to content

L
linux
Commit 9ebcaa47 authored by Mike Frysinger's avatar Mike Frysinger
Browse files
Options

Blackfin: bf54x: add missing SIC_RVECT definition 

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 49e00edb
Hide whitespace changes
Inline Side-by-side
Showing with 3 additions and 0 deletions
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
View file @ 9ebcaa47
...@@ -40,6 +40,8 @@ ...@@ -40,6 +40,8 @@
/* SIC Registers */ /* SIC Registers */
#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
......
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
View file @ 9ebcaa47
...@@ -35,6 +35,7 @@ ...@@ -35,6 +35,7 @@
/* SIC Registers */ /* SIC Registers */
#define SIC_RVECT 0xffc00108
#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */ #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */ #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */ #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7