Commit 9f587fa2 authored by Horia Geant?'s avatar Horia Geant? Committed by Herbert Xu

crypto: caam - fix writing to JQCR_MS when using service interface

Most significant part of JQCR (Job Queue Control Register) contains
bits that control endianness: ILE - Immediate Little Endian,
DWS - Double Word Swap.
The bits are automatically set by the Job Queue Controller HW.

Unfortunately these bits are cleared in SW when submitting descriptors
via the register-based service interface.
>From LS1021A:
JQCR_MS = 08080100 - before writing: ILE | DWS | SRC (JR0)
JQCR_MS = 30000100 - after writing: WHL | FOUR | SRC (JR0)

This would cause problems on little endian caam for descriptors
containing immediata data or double-word pointers.
Currently there is no problem since the only descriptors ran through
this interface are the ones that (un)instantiate RNG.
Signed-off-by: default avatarHoria Geant? <horia.geanta@freescale.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent d4421c54
...@@ -139,7 +139,7 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, ...@@ -139,7 +139,7 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
flags |= DECO_JQCR_FOUR; flags |= DECO_JQCR_FOUR;
/* Instruct the DECO to execute it */ /* Instruct the DECO to execute it */
wr_reg32(&deco->jr_ctl_hi, flags); setbits32(&deco->jr_ctl_hi, flags);
timeout = 10000000; timeout = 10000000;
do { do {
......
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