Commit 9fd4781b authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher

drm/amd/pm: Use generic BACO function for smu11 ASICs

Remove ASIC specific functions for BACO support check. Use generic smu11
function instead.
Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 52a9fd7b
...@@ -2162,16 +2162,6 @@ static void arcturus_get_unique_id(struct smu_context *smu) ...@@ -2162,16 +2162,6 @@ static void arcturus_get_unique_id(struct smu_context *smu)
sprintf(adev->serial, "%llx", id); sprintf(adev->serial, "%llx", id);
} }
static bool arcturus_is_baco_supported(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
return false;
return true;
}
static int arcturus_set_df_cstate(struct smu_context *smu, static int arcturus_set_df_cstate(struct smu_context *smu,
enum pp_df_cstate state) enum pp_df_cstate state)
{ {
...@@ -2406,7 +2396,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = { ...@@ -2406,7 +2396,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.register_irq_handler = smu_v11_0_register_irq_handler, .register_irq_handler = smu_v11_0_register_irq_handler,
.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
.baco_is_support= arcturus_is_baco_supported, .baco_is_support = smu_v11_0_baco_is_support,
.baco_get_state = smu_v11_0_baco_get_state, .baco_get_state = smu_v11_0_baco_get_state,
.baco_set_state = smu_v11_0_baco_set_state, .baco_set_state = smu_v11_0_baco_set_state,
.baco_enter = smu_v11_0_baco_enter, .baco_enter = smu_v11_0_baco_enter,
......
...@@ -2257,16 +2257,6 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, ...@@ -2257,16 +2257,6 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
return 0; return 0;
} }
static bool navi10_is_baco_supported(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
return false;
return true;
}
static int navi10_set_default_od_settings(struct smu_context *smu) static int navi10_set_default_od_settings(struct smu_context *smu)
{ {
OverDriveTable_t *od_table = OverDriveTable_t *od_table =
...@@ -3102,7 +3092,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { ...@@ -3102,7 +3092,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.register_irq_handler = smu_v11_0_register_irq_handler, .register_irq_handler = smu_v11_0_register_irq_handler,
.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
.baco_is_support= navi10_is_baco_supported, .baco_is_support = smu_v11_0_baco_is_support,
.baco_get_state = smu_v11_0_baco_get_state, .baco_get_state = smu_v11_0_baco_get_state,
.baco_set_state = smu_v11_0_baco_set_state, .baco_set_state = smu_v11_0_baco_set_state,
.baco_enter = smu_v11_0_baco_enter, .baco_enter = smu_v11_0_baco_enter,
......
...@@ -2100,16 +2100,6 @@ static int sienna_cichlid_run_btc(struct smu_context *smu) ...@@ -2100,16 +2100,6 @@ static int sienna_cichlid_run_btc(struct smu_context *smu)
return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
} }
static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
return false;
return true;
}
static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu) static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
{ {
struct amdgpu_device *adev = smu->adev; struct amdgpu_device *adev = smu->adev;
...@@ -3882,7 +3872,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { ...@@ -3882,7 +3872,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.register_irq_handler = smu_v11_0_register_irq_handler, .register_irq_handler = smu_v11_0_register_irq_handler,
.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
.baco_is_support= sienna_cichlid_is_baco_supported, .baco_is_support = smu_v11_0_baco_is_support,
.baco_get_state = smu_v11_0_baco_get_state, .baco_get_state = smu_v11_0_baco_get_state,
.baco_set_state = smu_v11_0_baco_set_state, .baco_set_state = smu_v11_0_baco_set_state,
.baco_enter = smu_v11_0_baco_enter, .baco_enter = smu_v11_0_baco_enter,
......
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