Commit 9fee9db5 authored by Shannon Nelson's avatar Shannon Nelson Committed by Jeff Kirsher

i40e/i40evf: find partition_id in npar mode

When in NPAR mode the driver instance might be controlling the base
partition or one of the other "fake" PFs.  There are some things that
can only be done by the base partition, aka partition_id 1.  This code
does a bit of work to find how many partitions are there per port and
what is the current partition_id.

Change-ID: Iba427f020a1983d02147d86f121b3627e20ee21d
Signed-off-by: default avatarShannon Nelson <shannon.nelson@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent b2d4d905
...@@ -2034,6 +2034,43 @@ i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, ...@@ -2034,6 +2034,43 @@ i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
return status; return status;
} }
/**
* i40e_aq_debug_read_register
* @hw: pointer to the hw struct
* @reg_addr: register address
* @reg_val: register value
* @cmd_details: pointer to command details structure or NULL
*
* Read the register using the admin queue commands
**/
i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
u32 reg_addr, u64 *reg_val,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
struct i40e_aqc_debug_reg_read_write *cmd_resp =
(struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
i40e_status status;
if (reg_val == NULL)
return I40E_ERR_PARAM;
i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_debug_read_reg);
cmd_resp->address = cpu_to_le32(reg_addr);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
if (!status) {
*reg_val = ((u64)cmd_resp->value_high << 32) |
(u64)cmd_resp->value_low;
*reg_val = le64_to_cpu(*reg_val);
}
return status;
}
/** /**
* i40e_aq_debug_write_register * i40e_aq_debug_write_register
* @hw: pointer to the hw struct * @hw: pointer to the hw struct
...@@ -2292,6 +2329,7 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, ...@@ -2292,6 +2329,7 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
enum i40e_admin_queue_opc list_type_opc) enum i40e_admin_queue_opc list_type_opc)
{ {
struct i40e_aqc_list_capabilities_element_resp *cap; struct i40e_aqc_list_capabilities_element_resp *cap;
u32 valid_functions, num_functions;
u32 number, logical_id, phys_id; u32 number, logical_id, phys_id;
struct i40e_hw_capabilities *p; struct i40e_hw_capabilities *p;
u32 i = 0; u32 i = 0;
...@@ -2427,6 +2465,34 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, ...@@ -2427,6 +2465,34 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
if (p->npar_enable || p->mfp_mode_1) if (p->npar_enable || p->mfp_mode_1)
p->fcoe = false; p->fcoe = false;
/* count the enabled ports (aka the "not disabled" ports) */
hw->num_ports = 0;
for (i = 0; i < 4; i++) {
u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
u64 port_cfg = 0;
/* use AQ read to get the physical register offset instead
* of the port relative offset
*/
i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
hw->num_ports++;
}
valid_functions = p->valid_functions;
num_functions = 0;
while (valid_functions) {
if (valid_functions & 1)
num_functions++;
valid_functions >>= 1;
}
/* partition id is 1-based, and functions are evenly spread
* across the ports as partitions
*/
hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
hw->num_partitions = num_functions / hw->num_ports;
/* additional HW specific goodies that might /* additional HW specific goodies that might
* someday be HW version specific * someday be HW version specific
*/ */
......
...@@ -71,6 +71,9 @@ i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw, ...@@ -71,6 +71,9 @@ i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw, i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
u32 reg_addr, u64 reg_val, u32 reg_addr, u64 reg_val,
struct i40e_asq_cmd_details *cmd_details); struct i40e_asq_cmd_details *cmd_details);
i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
u32 reg_addr, u64 *reg_val,
struct i40e_asq_cmd_details *cmd_details);
i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
struct i40e_asq_cmd_details *cmd_details); struct i40e_asq_cmd_details *cmd_details);
i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id, i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
......
...@@ -431,7 +431,7 @@ struct i40e_hw { ...@@ -431,7 +431,7 @@ struct i40e_hw {
u8 __iomem *hw_addr; u8 __iomem *hw_addr;
void *back; void *back;
/* function pointer structs */ /* subsystem structs */
struct i40e_phy_info phy; struct i40e_phy_info phy;
struct i40e_mac_info mac; struct i40e_mac_info mac;
struct i40e_bus_info bus; struct i40e_bus_info bus;
...@@ -458,6 +458,11 @@ struct i40e_hw { ...@@ -458,6 +458,11 @@ struct i40e_hw {
u8 pf_id; u8 pf_id;
u16 main_vsi_seid; u16 main_vsi_seid;
/* for multi-function MACs */
u16 partition_id;
u16 num_partitions;
u16 num_ports;
/* Closest numa node to the device */ /* Closest numa node to the device */
u16 numa_node; u16 numa_node;
......
...@@ -425,7 +425,7 @@ struct i40e_hw { ...@@ -425,7 +425,7 @@ struct i40e_hw {
u8 __iomem *hw_addr; u8 __iomem *hw_addr;
void *back; void *back;
/* function pointer structs */ /* subsystem structs */
struct i40e_phy_info phy; struct i40e_phy_info phy;
struct i40e_mac_info mac; struct i40e_mac_info mac;
struct i40e_bus_info bus; struct i40e_bus_info bus;
...@@ -452,6 +452,11 @@ struct i40e_hw { ...@@ -452,6 +452,11 @@ struct i40e_hw {
u8 pf_id; u8 pf_id;
u16 main_vsi_seid; u16 main_vsi_seid;
/* for multi-function MACs */
u16 partition_id;
u16 num_partitions;
u16 num_ports;
/* Closest numa node to the device */ /* Closest numa node to the device */
u16 numa_node; u16 numa_node;
......
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