Skip to content

L
linux
Commit a06b9560 authored by Gatien Chevallier's avatar Gatien Chevallier Committed by Alexandre Torgue
Browse files
Options

ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards 

ETZPC is a firewall controller. Put all peripherals filtered by the
ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for
backward compatibility.
Signed-off-by: default avatarGatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@foss.st.com>
parent ad426352
Hide whitespace changes
Inline Side-by-side
Showing with 565 additions and 559 deletions
arch/arm/boot/dts/st/stm32mp131.dtsi
View file @ a06b9560
......@@ -745,340 +745,6 @@ dmamux1: dma-router@48002000 {
dma-channels = <16>;
};
adc_2: adc@48004000 {
compatible = "st,stm32mp13-adc-core";
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc ADC2>, <&rcc ADC2_K>;
clock-names = "bus", "adc";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
adc2: adc@0 {
compatible = "st,stm32mp13-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc_2>;
interrupts = <0>;
dmas = <&dmamux1 10 0x400 0x80000001>;
dma-names = "rx";
status = "disabled";
channel@13 {
reg = <13>;
label = "vrefint";
};
channel@14 {
reg = <14>;
label = "vddcore";
};
channel@16 {
reg = <16>;
label = "vddcpu";
};
channel@17 {
reg = <17>;
label = "vddq_ddr";
};
};
};
usbotg_hs: usb@49000000 {
compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x40000>;
clocks = <&rcc USBO_K>;
clock-names = "otg";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
dr_mode = "otg";
otg-rev = <0x200>;
usb33d-supply = <&scmi_usb33>;
status = "disabled";
};
usart1: serial@4c000000 {
compatible = "st,stm32h7-uart";
reg = <0x4c000000 0x400>;
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART1_K>;
resets = <&rcc USART1_R>;
wakeup-source;
dmas = <&dmamux1 41 0x400 0x5>,
<&dmamux1 42 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
usart2: serial@4c001000 {
compatible = "st,stm32h7-uart";
reg = <0x4c001000 0x400>;
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
resets = <&rcc USART2_R>;
wakeup-source;
dmas = <&dmamux1 43 0x400 0x5>,
<&dmamux1 44 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
i2s4: audio-controller@4c002000 {
compatible = "st,stm32h7-i2s";
reg = <0x4c002000 0x400>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmamux1 83 0x400 0x01>,
<&dmamux1 84 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
spi4: spi@4c002000 {
compatible = "st,stm32h7-spi";
reg = <0x4c002000 0x400>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI4_K>;
resets = <&rcc SPI4_R>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 83 0x400 0x01>,
<&dmamux1 84 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
spi5: spi@4c003000 {
compatible = "st,stm32h7-spi";
reg = <0x4c003000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI5_K>;
resets = <&rcc SPI5_R>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 85 0x400 0x01>,
<&dmamux1 86 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c3: i2c@4c004000 {
compatible = "st,stm32mp13-i2c";
reg = <0x4c004000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C3_K>;
resets = <&rcc I2C3_R>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 73 0x400 0x1>,
<&dmamux1 74 0x400 0x1>;
dma-names = "rx", "tx";
st,syscfg-fmp = <&syscfg 0x4 0x4>;
i2c-analog-filter;
status = "disabled";
};
i2c4: i2c@4c005000 {
compatible = "st,stm32mp13-i2c";
reg = <0x4c005000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C4_K>;
resets = <&rcc I2C4_R>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 75 0x400 0x1>,
<&dmamux1 76 0x400 0x1>;
dma-names = "rx", "tx";
st,syscfg-fmp = <&syscfg 0x4 0x8>;
i2c-analog-filter;
status = "disabled";
};
i2c5: i2c@4c006000 {
compatible = "st,stm32mp13-i2c";
reg = <0x4c006000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C5_K>;
resets = <&rcc I2C5_R>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 115 0x400 0x1>,
<&dmamux1 116 0x400 0x1>;
dma-names = "rx", "tx";
st,syscfg-fmp = <&syscfg 0x4 0x10>;
i2c-analog-filter;
status = "disabled";
};
timers12: timer@4c007000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c007000 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM12_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@11 {
compatible = "st,stm32h7-timer-trigger";
reg = <11>;
status = "disabled";
};
};
timers13: timer@4c008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c008000 0x400>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM13_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@12 {
compatible = "st,stm32h7-timer-trigger";
reg = <12>;
status = "disabled";
};
};
timers14: timer@4c009000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c009000 0x400>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM14_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@13 {
compatible = "st,stm32h7-timer-trigger";
reg = <13>;
status = "disabled";
};
};
timers15: timer@4c00a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c00a000 0x400>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM15_K>;
clock-names = "int";
dmas = <&dmamux1 105 0x400 0x1>,
<&dmamux1 106 0x400 0x1>,
<&dmamux1 107 0x400 0x1>,
<&dmamux1 108 0x400 0x1>;
dma-names = "ch1", "up", "trig", "com";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@14 {
compatible = "st,stm32h7-timer-trigger";
reg = <14>;
status = "disabled";
};
};
timers16: timer@4c00b000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c00b000 0x400>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM16_K>;
clock-names = "int";
dmas = <&dmamux1 109 0x400 0x1>,
<&dmamux1 110 0x400 0x1>;
dma-names = "ch1", "up";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@15 {
compatible = "st,stm32h7-timer-trigger";
reg = <15>;
status = "disabled";
};
};
timers17: timer@4c00c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c00c000 0x400>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM17_K>;
clock-names = "int";
dmas = <&dmamux1 111 0x400 0x1>,
<&dmamux1 112 0x400 0x1>;
dma-names = "ch1", "up";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@16 {
compatible = "st,stm32h7-timer-trigger";
reg = <16>;
status = "disabled";
};
};
rcc: rcc@50000000 {
compatible = "st,stm32mp13-rcc", "syscon";
reg = <0x50000000 0x1000>;
......@@ -1105,69 +771,6 @@ syscfg: syscon@50020000 {
clocks = <&rcc SYSCFG>;
};
lptimer2: timer@50021000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50021000 0x400>;
interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
trigger@1 {
compatible = "st,stm32-lptimer-trigger";
reg = <1>;
status = "disabled";
};
counter {
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
timer {
compatible = "st,stm32-lptimer-timer";
status = "disabled";
};
};
lptimer3: timer@50022000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50022000 0x400>;
interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
trigger@2 {
compatible = "st,stm32-lptimer-trigger";
reg = <2>;
status = "disabled";
};
timer {
compatible = "st,stm32-lptimer-timer";
status = "disabled";
};
};
lptimer4: timer@50023000 {
compatible = "st,stm32-lptimer";
reg = <0x50023000 0x400>;
......@@ -1210,25 +813,6 @@ timer {
};
};
hash: hash@54003000 {
compatible = "st,stm32mp13-hash";
reg = <0x54003000 0x400>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc HASH1>;
resets = <&rcc HASH1_R>;
dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>;
dma-names = "in";
status = "disabled";
};
rng: rng@54004000 {
compatible = "st,stm32mp13-rng";
reg = <0x54004000 0x400>;
clocks = <&rcc RNG1_K>;
resets = <&rcc RNG1_R>;
status = "disabled";
};
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
......@@ -1239,82 +823,6 @@ mdma: dma-controller@58000000 {
dma-requests = <48>;
};
fmc: memory-controller@58002000 {
compatible = "st,stm32mp1-fmc2-ebi";
reg = <0x58002000 0x1000>;
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
<4 0 0x80000000 0x10000000>; /* NAND */
#address-cells = <2>;
#size-cells = <1>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
nand-controller@4,0 {
compatible = "st,stm32mp1-fmc2-nfc";
reg = <4 0x00000000 0x1000>,
<4 0x08010000 0x1000>,
<4 0x08020000 0x1000>,
<4 0x01000000 0x1000>,
<4 0x09010000 0x1000>,
<4 0x09020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
<&mdma 24 0x2 0x12000a08 0x0 0x0>,
<&mdma 25 0x2 0x12000a0a 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
status = "disabled";
};
};
qspi: spi@58003000 {
compatible = "st,stm32f469-qspi";
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
<&mdma 26 0x2 0x10100008 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
status = "disabled";
};
sdmmc1: mmc@58005000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x20253180>;
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
status = "disabled";
};
sdmmc2: mmc@58007000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x20253180>;
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
status = "disabled";
};
crc1: crc@58009000 {
compatible = "st,stm32f7-crc";
reg = <0x58009000 0x400>;
......@@ -1349,29 +857,6 @@ iwdg2: watchdog@5a002000 {
status = "disabled";
};
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
compatible = "st,stm32mp1-usbphyc";
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
resets = <&rcc USBPHY_R>;
vdda1v1-supply = <&scmi_reg11>;
vdda1v8-supply = <&scmi_reg18>;
status = "disabled";
usbphyc_port0: usb-phy@0 {
#phy-cells = <0>;
reg = <0>;
};
usbphyc_port1: usb-phy@1 {
#phy-cells = <1>;
reg = <1>;
};
};
rtc: rtc@5c004000 {
compatible = "st,stm32mp1-rtc";
reg = <0x5c004000 0x400>;
......@@ -1400,6 +885,529 @@ ts_cal2: calib@5e {
};
};
etzpc: bus@5c007000 {
compatible = "simple-bus";
reg = <0x5c007000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
adc_2: adc@48004000 {
compatible = "st,stm32mp13-adc-core";
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc ADC2>, <&rcc ADC2_K>;
clock-names = "bus", "adc";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
adc2: adc@0 {
compatible = "st,stm32mp13-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc_2>;
interrupts = <0>;
dmas = <&dmamux1 10 0x400 0x80000001>;
dma-names = "rx";
status = "disabled";
channel@13 {
reg = <13>;
label = "vrefint";
};
channel@14 {
reg = <14>;
label = "vddcore";
};
channel@16 {
reg = <16>;
label = "vddcpu";
};
channel@17 {
reg = <17>;
label = "vddq_ddr";
};
};
};
usbotg_hs: usb@49000000 {
compatible = "st,stm32mp15-hsotg", "snps,dwc2";
reg = <0x49000000 0x40000>;
clocks = <&rcc USBO_K>;
clock-names = "otg";
resets = <&rcc USBO_R>;
reset-names = "dwc2";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
dr_mode = "otg";
otg-rev = <0x200>;
usb33d-supply = <&scmi_usb33>;
status = "disabled";
};
usart1: serial@4c000000 {
compatible = "st,stm32h7-uart";
reg = <0x4c000000 0x400>;
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART1_K>;
resets = <&rcc USART1_R>;
wakeup-source;
dmas = <&dmamux1 41 0x400 0x5>,
<&dmamux1 42 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
usart2: serial@4c001000 {
compatible = "st,stm32h7-uart";
reg = <0x4c001000 0x400>;
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
resets = <&rcc USART2_R>;
wakeup-source;
dmas = <&dmamux1 43 0x400 0x5>,
<&dmamux1 44 0x400 0x1>;
dma-names = "rx", "tx";
status = "disabled";
};
i2s4: audio-controller@4c002000 {
compatible = "st,stm32h7-i2s";
reg = <0x4c002000 0x400>;
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dmamux1 83 0x400 0x01>,
<&dmamux1 84 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
spi4: spi@4c002000 {
compatible = "st,stm32h7-spi";
reg = <0x4c002000 0x400>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI4_K>;
resets = <&rcc SPI4_R>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 83 0x400 0x01>,
<&dmamux1 84 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
spi5: spi@4c003000 {
compatible = "st,stm32h7-spi";
reg = <0x4c003000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SPI5_K>;
resets = <&rcc SPI5_R>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 85 0x400 0x01>,
<&dmamux1 86 0x400 0x01>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c3: i2c@4c004000 {
compatible = "st,stm32mp13-i2c";
reg = <0x4c004000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C3_K>;
resets = <&rcc I2C3_R>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 73 0x400 0x1>,
<&dmamux1 74 0x400 0x1>;
dma-names = "rx", "tx";
st,syscfg-fmp = <&syscfg 0x4 0x4>;
i2c-analog-filter;
status = "disabled";
};
i2c4: i2c@4c005000 {
compatible = "st,stm32mp13-i2c";
reg = <0x4c005000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C4_K>;
resets = <&rcc I2C4_R>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 75 0x400 0x1>,
<&dmamux1 76 0x400 0x1>;
dma-names = "rx", "tx";
st,syscfg-fmp = <&syscfg 0x4 0x8>;
i2c-analog-filter;
status = "disabled";
};
i2c5: i2c@4c006000 {
compatible = "st,stm32mp13-i2c";
reg = <0x4c006000 0x400>;
interrupt-names = "event", "error";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc I2C5_K>;
resets = <&rcc I2C5_R>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmamux1 115 0x400 0x1>,
<&dmamux1 116 0x400 0x1>;
dma-names = "rx", "tx";
st,syscfg-fmp = <&syscfg 0x4 0x10>;
i2c-analog-filter;
status = "disabled";
};
timers12: timer@4c007000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c007000 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM12_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@11 {
compatible = "st,stm32h7-timer-trigger";
reg = <11>;
status = "disabled";
};
};
timers13: timer@4c008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c008000 0x400>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM13_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@12 {
compatible = "st,stm32h7-timer-trigger";
reg = <12>;
status = "disabled";
};
};
timers14: timer@4c009000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c009000 0x400>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM14_K>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@13 {
compatible = "st,stm32h7-timer-trigger";
reg = <13>;
status = "disabled";
};
};
timers15: timer@4c00a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c00a000 0x400>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM15_K>;
clock-names = "int";
dmas = <&dmamux1 105 0x400 0x1>,
<&dmamux1 106 0x400 0x1>,
<&dmamux1 107 0x400 0x1>,
<&dmamux1 108 0x400 0x1>;
dma-names = "ch1", "up", "trig", "com";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@14 {
compatible = "st,stm32h7-timer-trigger";
reg = <14>;
status = "disabled";
};
};
timers16: timer@4c00b000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c00b000 0x400>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM16_K>;
clock-names = "int";
dmas = <&dmamux1 109 0x400 0x1>,
<&dmamux1 110 0x400 0x1>;
dma-names = "ch1", "up";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@15 {
compatible = "st,stm32h7-timer-trigger";
reg = <15>;
status = "disabled";
};
};
timers17: timer@4c00c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x4c00c000 0x400>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc TIM17_K>;
clock-names = "int";
dmas = <&dmamux1 111 0x400 0x1>,
<&dmamux1 112 0x400 0x1>;
dma-names = "ch1", "up";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@16 {
compatible = "st,stm32h7-timer-trigger";
reg = <16>;
status = "disabled";
};
};
lptimer2: timer@50021000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50021000 0x400>;
interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
trigger@1 {
compatible = "st,stm32-lptimer-trigger";
reg = <1>;
status = "disabled";
};
counter {
compatible = "st,stm32-lptimer-counter";
status = "disabled";
};
timer {
compatible = "st,stm32-lptimer-timer";
status = "disabled";
};
};
lptimer3: timer@50022000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x50022000 0x400>;
interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
wakeup-source;
status = "disabled";
pwm {
compatible = "st,stm32-pwm-lp";
#pwm-cells = <3>;
status = "disabled";
};
trigger@2 {
compatible = "st,stm32-lptimer-trigger";
reg = <2>;
status = "disabled";
};
timer {
compatible = "st,stm32-lptimer-timer";
status = "disabled";
};
};
hash: hash@54003000 {
compatible = "st,stm32mp13-hash";
reg = <0x54003000 0x400>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc HASH1>;
resets = <&rcc HASH1_R>;
dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>;
dma-names = "in";
status = "disabled";
};
rng: rng@54004000 {
compatible = "st,stm32mp13-rng";
reg = <0x54004000 0x400>;
clocks = <&rcc RNG1_K>;
resets = <&rcc RNG1_R>;
status = "disabled";
};
fmc: memory-controller@58002000 {
compatible = "st,stm32mp1-fmc2-ebi";
reg = <0x58002000 0x1000>;
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
<4 0 0x80000000 0x10000000>; /* NAND */
#address-cells = <2>;
#size-cells = <1>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
status = "disabled";
nand-controller@4,0 {
compatible = "st,stm32mp1-fmc2-nfc";
reg = <4 0x00000000 0x1000>,
<4 0x08010000 0x1000>,
<4 0x08020000 0x1000>,
<4 0x01000000 0x1000>,
<4 0x09010000 0x1000>,
<4 0x09020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
<&mdma 24 0x2 0x12000a08 0x0 0x0>,
<&mdma 25 0x2 0x12000a0a 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
status = "disabled";
};
};
qspi: spi@58003000 {
compatible = "st,stm32f469-qspi";
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
<&mdma 26 0x2 0x10100008 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
status = "disabled";
};
sdmmc1: mmc@58005000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x20253180>;
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
status = "disabled";
};
sdmmc2: mmc@58007000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x20253180>;
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <130000000>;
status = "disabled";
};
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
compatible = "st,stm32mp1-usbphyc";
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
resets = <&rcc USBPHY_R>;
vdda1v1-supply = <&scmi_reg11>;
vdda1v8-supply = <&scmi_reg18>;
status = "disabled";
usbphyc_port0: usb-phy@0 {
#phy-cells = <0>;
reg = <0>;
};
usbphyc_port1: usb-phy@1 {
#phy-cells = <1>;
reg = <1>;
};
};
};
/*
* Break node order to solve dependency probe issue between
* pinctrl and exti.
......
arch/arm/boot/dts/st/stm32mp133.dtsi
View file @ a06b9560
......@@ -33,35 +33,37 @@ m_can2: can@4400f000 {
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
};
};
};
adc_1: adc@48003000 {
compatible = "st,stm32mp13-adc-core";
reg = <0x48003000 0x400>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc ADC1>, <&rcc ADC1_K>;
clock-names = "bus", "adc";
interrupt-controller;
#interrupt-cells = <1>;
&etzpc {
adc_1: adc@48003000 {
compatible = "st,stm32mp13-adc-core";
reg = <0x48003000 0x400>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc ADC1>, <&rcc ADC1_K>;
clock-names = "bus", "adc";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
adc1: adc@0 {
compatible = "st,stm32mp13-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc_1>;
interrupts = <0>;
dmas = <&dmamux1 9 0x400 0x80000001>;
dma-names = "rx";
status = "disabled";
adc1: adc@0 {
compatible = "st,stm32mp13-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc_1>;
interrupts = <0>;
dmas = <&dmamux1 9 0x400 0x80000001>;
dma-names = "rx";
status = "disabled";
channel@18 {
reg = <18>;
label = "vrefint";
};
channel@18 {
reg = <18>;
label = "vrefint";
};
};
};
......
arch/arm/boot/dts/st/stm32mp13xc.dtsi
View file @ a06b9560
......@@ -4,15 +4,13 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
soc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
&etzpc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
};
arch/arm/boot/dts/st/stm32mp13xf.dtsi
View file @ a06b9560
......@@ -4,15 +4,13 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
soc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
&etzpc {
cryp: crypto@54002000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54002000 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
status = "disabled";
};
};
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7