Commit a0f95e35 authored by Jianqun's avatar Jianqun Committed by Arnd Bergmann

ARM: dts: add rk3288 i2s controller

Add dt for rk3288 i2s controller, since i2s clock pins and data pins
default to be GPIO, this patch also add pinctrl to mux them.

Tested on RK3288 board.
Signed-off-by: default avatarJianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 16529509
...@@ -469,6 +469,21 @@ wdt: watchdog@ff800000 { ...@@ -469,6 +469,21 @@ wdt: watchdog@ff800000 {
status = "disabled"; status = "disabled";
}; };
i2s: i2s@ff890000 {
compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
reg = <0xff890000 0x10000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
status = "disabled";
};
gic: interrupt-controller@ffc01000 { gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
interrupt-controller; interrupt-controller;
...@@ -661,6 +676,17 @@ i2c5_xfer: i2c5-xfer { ...@@ -661,6 +676,17 @@ i2c5_xfer: i2c5-xfer {
}; };
}; };
i2s0 {
i2s0_bus: i2s0-bus {
rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
<6 1 RK_FUNC_1 &pcfg_pull_none>,
<6 2 RK_FUNC_1 &pcfg_pull_none>,
<6 3 RK_FUNC_1 &pcfg_pull_none>,
<6 4 RK_FUNC_1 &pcfg_pull_none>,
<6 8 RK_FUNC_1 &pcfg_pull_none>;
};
};
sdmmc { sdmmc {
sdmmc_clk: sdmmc-clk { sdmmc_clk: sdmmc-clk {
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
......
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