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Commit a16b2ff6 authored by Ralf Bächle's avatar Ralf Bächle Committed by Linus Torvalds
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[PATCH] TX49xx update 

This adds support for Toshiba's TX49xx SOCs and an evaluation board with
the nice nae RBTX4927.
parent 5d3adbe2
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arch/mips/tx4927/common/Makefile 0 → 100644
View file @ a16b2ff6
#
# Makefile for common code for Toshiba TX4927 based systems
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
obj-y := tx4927_prom.o
obj-y += tx4927_setup.o
obj-y += tx4927_irq.o
obj-y += tx4927_irq_handler.o
obj-$(CONFIG_KGDB) += tx4927_dbgio.o
arch/mips/tx4927/common/tx4927_dbgio.c 0 → 100644
View file @ a16b2ff6
/*
* linux/arch/mips/tx4927/common/tx4927_dbgio.c
*
* kgdb interface for gdb
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/tx4927/tx4927_mips.h>
u8 getDebugChar(void)
{
extern u8 txx9_sio_kdbg_rd(void);
return (txx9_sio_kdbg_rd());
}
int putDebugChar(u8 byte)
{
extern int txx9_sio_kdbg_wr( u8 ch );
return (txx9_sio_kdbg_wr(byte));
}
arch/mips/tx4927/common/tx4927_irq.c 0 → 100644
View file @ a16b2ff6
/*
* Common tx4927 irq handler
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/irq.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/tx4927/tx4927.h>
/*
* DEBUG
*/
#define TX4927_IRQ_CHECK_CP0
#define TX4927_IRQ_CHECK_PIC
#undef TX4927_IRQ_DEBUG
#ifdef TX4927_IRQ_DEBUG
#define TX4927_IRQ_NONE 0x00000000
#define TX4927_IRQ_INFO ( 1 << 0 )
#define TX4927_IRQ_WARN ( 1 << 1 )
#define TX4927_IRQ_EROR ( 1 << 2 )
#define TX4927_IRQ_INIT ( 1 << 5 )
#define TX4927_IRQ_NEST1 ( 1 << 6 )
#define TX4927_IRQ_NEST2 ( 1 << 7 )
#define TX4927_IRQ_NEST3 ( 1 << 8 )
#define TX4927_IRQ_NEST4 ( 1 << 9 )
#define TX4927_IRQ_CP0_INIT ( 1 << 10 )
#define TX4927_IRQ_CP0_STARTUP ( 1 << 11 )
#define TX4927_IRQ_CP0_SHUTDOWN ( 1 << 12 )
#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 )
#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 )
#define TX4927_IRQ_CP0_MASK ( 1 << 15 )
#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 )
#define TX4927_IRQ_PIC_INIT ( 1 << 20 )
#define TX4927_IRQ_PIC_STARTUP ( 1 << 21 )
#define TX4927_IRQ_PIC_SHUTDOWN ( 1 << 22 )
#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 )
#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 )
#define TX4927_IRQ_PIC_MASK ( 1 << 25 )
#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 )
#define TX4927_IRQ_ALL 0xffffffff
#endif
#ifdef TX4927_IRQ_DEBUG
static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
| TX4927_IRQ_INFO
| TX4927_IRQ_WARN | TX4927_IRQ_EROR
// | TX4927_IRQ_CP0_INIT
// | TX4927_IRQ_CP0_STARTUP
// | TX4927_IRQ_CP0_SHUTDOWN
// | TX4927_IRQ_CP0_ENABLE
// | TX4927_IRQ_CP0_DISABLE
// | TX4927_IRQ_CP0_MASK
// | TX4927_IRQ_CP0_ENDIRQ
// | TX4927_IRQ_PIC_INIT
// | TX4927_IRQ_PIC_STARTUP
// | TX4927_IRQ_PIC_SHUTDOWN
// | TX4927_IRQ_PIC_ENABLE
// | TX4927_IRQ_PIC_DISABLE
// | TX4927_IRQ_PIC_MASK
// | TX4927_IRQ_PIC_ENDIRQ
// | TX4927_IRQ_INIT
// | TX4927_IRQ_NEST1
// | TX4927_IRQ_NEST2
// | TX4927_IRQ_NEST3
// | TX4927_IRQ_NEST4
);
#endif
#ifdef TX4927_IRQ_DEBUG
#define TX4927_IRQ_DPRINTK(flag,str...) \
if ( (tx4927_irq_debug_flag) & (flag) ) \
{ \
char tmp[100]; \
sprintf( tmp, str ); \
printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
}
#else
#define TX4927_IRQ_DPRINTK(flag,str...)
#endif
/*
* Forwad definitions for all pic's
*/
static unsigned int tx4927_irq_cp0_startup(unsigned int irq);
static void tx4927_irq_cp0_shutdown(unsigned int irq);
static void tx4927_irq_cp0_enable(unsigned int irq);
static void tx4927_irq_cp0_disable(unsigned int irq);
static void tx4927_irq_cp0_mask_and_ack(unsigned int irq);
static void tx4927_irq_cp0_end(unsigned int irq);
static unsigned int tx4927_irq_pic_startup(unsigned int irq);
static void tx4927_irq_pic_shutdown(unsigned int irq);
static void tx4927_irq_pic_enable(unsigned int irq);
static void tx4927_irq_pic_disable(unsigned int irq);
static void tx4927_irq_pic_mask_and_ack(unsigned int irq);
static void tx4927_irq_pic_end(unsigned int irq);
/*
* Kernel structs for all pic's
*/
static spinlock_t tx4927_cp0_lock = SPIN_LOCK_UNLOCKED;
static spinlock_t tx4927_pic_lock = SPIN_LOCK_UNLOCKED;
#define TX4927_CP0_NAME "TX4927-CP0"
static struct hw_interrupt_type tx4927_irq_cp0_type = {
typename: TX4927_CP0_NAME,
startup: tx4927_irq_cp0_startup,
shutdown: tx4927_irq_cp0_shutdown,
enable: tx4927_irq_cp0_enable,
disable: tx4927_irq_cp0_disable,
ack: tx4927_irq_cp0_mask_and_ack,
end: tx4927_irq_cp0_end,
set_affinity: NULL
};
#define TX4927_PIC_NAME "TX4927-PIC"
static struct hw_interrupt_type tx4927_irq_pic_type = {
typename: TX4927_PIC_NAME,
startup: tx4927_irq_pic_startup,
shutdown: tx4927_irq_pic_shutdown,
enable: tx4927_irq_pic_enable,
disable: tx4927_irq_pic_disable,
ack: tx4927_irq_pic_mask_and_ack,
end: tx4927_irq_pic_end,
set_affinity: NULL
};
#define TX4927_PIC_ACTION(s) { no_action, 0, 0, s, NULL, NULL }
static struct irqaction tx4927_irq_pic_action =
TX4927_PIC_ACTION(TX4927_PIC_NAME);
#define CCP0_STATUS 12
#define CCP0_CAUSE 13
/*
* Functions for cp0
*/
#define tx4927_irq_cp0_mask(irq) ( 1 << ( irq-TX4927_IRQ_CP0_BEG+8 ) )
static void
tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits)
{
unsigned long val = 0;
switch (cp0_reg) {
case CCP0_STATUS:
val = read_c0_status();
break;
case CCP0_CAUSE:
val = read_c0_cause();
break;
}
val &= (~clr_bits);
val |= (set_bits);
switch (cp0_reg) {
case CCP0_STATUS:{
write_c0_status(val);
break;
}
case CCP0_CAUSE:{
write_c0_cause(val);
break;
}
}
return;
}
static void __init tx4927_irq_cp0_init(void)
{
int i;
TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n",
TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END);
for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &tx4927_irq_cp0_type;
}
return;
}
static unsigned int tx4927_irq_cp0_startup(unsigned int irq)
{
TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_STARTUP, "irq=%d \n", irq);
#ifdef TX4927_IRQ_CHECK_CP0
{
if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
tx4927_irq_cp0_enable(irq);
return (0);
}
static void tx4927_irq_cp0_shutdown(unsigned int irq)
{
TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_SHUTDOWN, "irq=%d \n", irq);
#ifdef TX4927_IRQ_CHECK_CP0
{
if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
tx4927_irq_cp0_disable(irq);
return;
}
static void tx4927_irq_cp0_enable(unsigned int irq)
{
unsigned long flags;
TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq);
#ifdef TX4927_IRQ_CHECK_CP0
{
if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
spin_lock_irqsave(&tx4927_cp0_lock, flags);
tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq));
spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
return;
}
static void tx4927_irq_cp0_disable(unsigned int irq)
{
unsigned long flags;
TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq);
#ifdef TX4927_IRQ_CHECK_CP0
{
if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
spin_lock_irqsave(&tx4927_cp0_lock, flags);
tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
return;
}
static void tx4927_irq_cp0_mask_and_ack(unsigned int irq)
{
TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_MASK, "irq=%d \n", irq);
#ifdef TX4927_IRQ_CHECK_CP0
{
if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
tx4927_irq_cp0_disable(irq);
return;
}
static void tx4927_irq_cp0_end(unsigned int irq)
{
TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENDIRQ, "irq=%d \n", irq);
#ifdef TX4927_IRQ_CHECK_CP0
{
if (irq < TX4927_IRQ_CP0_BEG || irq > TX4927_IRQ_CP0_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
tx4927_irq_cp0_enable(irq);
}
return;
}
/*
* Functions for pic
*/
u32 tx4927_irq_pic_addr(int irq)
{
/* MVMCP -- need to formulize this */
irq -= TX4927_IRQ_PIC_BEG;
switch (irq) {
case 17:
case 16:
case 1:
case 0:
return (0xff1ff610);
case 19:
case 18:
case 3:
case 2:
return (0xff1ff614);
case 21:
case 20:
case 5:
case 4:
return (0xff1ff618);
case 23:
case 22:
case 7:
case 6:
return (0xff1ff61c);
case 25:
case 24:
case 9:
case 8:
return (0xff1ff620);
case 27:
case 26:
case 11:
case 10:
return (0xff1ff624);
case 29:
case 28:
case 13:
case 12:
return (0xff1ff628);
case 31:
case 30:
case 15:
case 14:
return (0xff1ff62c);
}
return (0);
}
u32 tx4927_irq_pic_mask(int irq)
{
/* MVMCP -- need to formulize this */
irq -= TX4927_IRQ_PIC_BEG;
switch (irq) {
case 31:
case 29:
case 27:
case 25:
case 23:
case 21:
case 19:
case 17:{
return (0x07000000);
}
case 30:
case 28:
case 26:
case 24:
case 22:
case 20:
case 18:
case 16:{
return (0x00070000);
}
case 15:
case 13:
case 11:
case 9:
case 7:
case 5:
case 3:
case 1:{
return (0x00000700);
}
case 14:
case 12:
case 10:
case 8:
case 6:
case 4:
case 2:
case 0:{
return (0x00000007);
}
}
return (0x00000000);
}
static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits,
unsigned set_bits)
{
unsigned long val = 0;
val = TX4927_RD(pic_reg);
val &= (~clr_bits);
val |= (set_bits);
TX4927_WR(pic_reg, val);
return;
}
static void __init tx4927_irq_pic_init(void)
{
unsigned long flags;
int i;
TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n",
TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END);
for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 2;
irq_desc[i].handler = &tx4927_irq_pic_type;
}
setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
spin_lock_irqsave(&tx4927_pic_lock, flags);
TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */
spin_unlock_irqrestore(&tx4927_pic_lock, flags);
return;
}
static unsigned int tx4927_irq_pic_startup(unsigned int irq)
{
TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_STARTUP, "irq=%d\n", irq);
#ifdef TX4927_IRQ_CHECK_PIC
{
if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
tx4927_irq_pic_enable(irq);
return (0);
}
static void tx4927_irq_pic_shutdown(unsigned int irq)
{
TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_SHUTDOWN, "irq=%d\n", irq);
#ifdef TX4927_IRQ_CHECK_PIC
{
if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
tx4927_irq_pic_disable(irq);
return;
}
static void tx4927_irq_pic_enable(unsigned int irq)
{
unsigned long flags;
TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq);
#ifdef TX4927_IRQ_CHECK_PIC
{
if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
spin_lock_irqsave(&tx4927_pic_lock, flags);
tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0,
tx4927_irq_pic_mask(irq));
spin_unlock_irqrestore(&tx4927_pic_lock, flags);
return;
}
static void tx4927_irq_pic_disable(unsigned int irq)
{
unsigned long flags;
TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq);
#ifdef TX4927_IRQ_CHECK_PIC
{
if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
spin_lock_irqsave(&tx4927_pic_lock, flags);
tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq),
tx4927_irq_pic_mask(irq), 0);
spin_unlock_irqrestore(&tx4927_pic_lock, flags);
return;
}
static void tx4927_irq_pic_mask_and_ack(unsigned int irq)
{
TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_MASK, "irq=%d\n", irq);
#ifdef TX4927_IRQ_CHECK_PIC
{
if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
tx4927_irq_pic_disable(irq);
return;
}
static void tx4927_irq_pic_end(unsigned int irq)
{
TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENDIRQ, "irq=%d\n", irq);
#ifdef TX4927_IRQ_CHECK_PIC
{
if (irq < TX4927_IRQ_PIC_BEG || irq > TX4927_IRQ_PIC_END) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_EROR,
"bad irq=%d \n", irq);
panic("\n");
}
}
#endif
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
tx4927_irq_pic_enable(irq);
}
return;
}
/*
* Main init functions
*/
void __init tx4927_irq_init(void)
{
extern asmlinkage void tx4927_irq_handler(void);
TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "-\n");
TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "=Calling tx4927_irq_cp0_init()\n");
tx4927_irq_cp0_init();
TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "=Calling tx4927_irq_pic_init()\n");
tx4927_irq_pic_init();
TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT,
"=Calling set_except_vector(tx4927_irq_handler)\n");
set_except_vector(0, tx4927_irq_handler);
TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n");
return;
}
int tx4927_irq_nested(void)
{
int sw_irq = 0;
u32 level2;
TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "-\n");
level2 = TX4927_RD(0xff1ff6a0);
TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=level2a=0x%x\n", level2);
if ((level2 & 0x10000) == 0) {
level2 &= 0x1f;
TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=level2b=0x%x\n", level2);
sw_irq = TX4927_IRQ_PIC_BEG + level2;
TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=sw_irq=%d\n", sw_irq);
if (sw_irq == 27) {
TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq-%d\n",
sw_irq);
#ifdef CONFIG_TOSHIBA_RBTX4927
{
sw_irq = toshiba_rbtx4927_irq_nested(sw_irq);
}
#endif
TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq+%d\n",
sw_irq);
}
}
TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=sw_irq=%d\n", sw_irq);
TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "+\n");
return (sw_irq);
}
arch/mips/tx4927/common/tx4927_irq_handler.S 0 → 100644
View file @ a16b2ff6
/*
* linux/arch/mips/tx4927/common/tx4927_irq_handler.S
*
* Primary interrupt handler for tx4927 based systems
*
* Author: MontaVista Software, Inc.
* Author: jsun@mvista.com or jsun@junsun.net
* source@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/tx4927/tx4927.h>
.align 5
NESTED(tx4927_irq_handler, PT_SIZE, sp)
SAVE_ALL
CLI
.set at
mfc0 t0, CP0_CAUSE
mfc0 t1, CP0_STATUS
and t0, t1
andi t1, t0, STATUSF_IP7 /* cpu timer */
bnez t1, ll_ip7
/* IP6..IP3 multiplexed -- do not use */
andi t1, t0, STATUSF_IP2 /* tx4927 pic */
bnez t1, ll_ip2
andi t1, t0, STATUSF_IP0 /* user line 0 */
bnez t1, ll_ip0
andi t1, t0, STATUSF_IP1 /* user line 1 */
bnez t1, ll_ip1
.set reorder
/* wrong alarm or masked ... */
j spurious_interrupt
nop
END(tx4927_irq_handler)
.align 5
ll_ip7:
li a0, TX4927_IRQ_CPU_TIMER
move a1, sp
jal do_IRQ
j ret_from_irq
ll_ip2:
jal tx4927_irq_nested
nop
beqz v0, goto_spurious_interrupt
nop
move a0, v0
move a1, sp
jal do_IRQ
j ret_from_irq
goto_spurious_interrupt:
j spurious_interrupt
nop
ll_ip1:
li a0, TX4927_IRQ_USER1
move a1, sp
jal do_IRQ
j ret_from_irq
ll_ip0:
li a0, TX4927_IRQ_USER0
move a1, sp
jal do_IRQ
j ret_from_irq
arch/mips/tx4927/common/tx4927_prom.c 0 → 100644
View file @ a16b2ff6
/*
* linux/arch/mips/tx4927/common/tx4927_prom.c
*
* common tx4927 memory interface
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/tx4927/tx4927.h>
static unsigned int __init tx4927_process_sdccr(u64 * addr)
{
u64 val;
unsigned int sdccr_ce;
unsigned int sdccr_bs;
unsigned int sdccr_rs;
unsigned int sdccr_cs;
unsigned int sdccr_mw;
unsigned int bs = 0;
unsigned int rs = 0;
unsigned int cs = 0;
unsigned int mw = 0;
unsigned int msize = 0;
val = (*((vu64 *) (addr)));
/* MVMCP -- need #defs for these bits masks */
sdccr_ce = ((val & (1 << 10)) >> 10);
sdccr_bs = ((val & (1 << 8)) >> 8);
sdccr_rs = ((val & (3 << 5)) >> 5);
sdccr_cs = ((val & (3 << 2)) >> 2);
sdccr_mw = ((val & (1 << 0)) >> 0);
if (sdccr_ce) {
switch (sdccr_bs) {
case 0:{
bs = 2;
break;
}
case 1:{
bs = 4;
break;
}
}
switch (sdccr_rs) {
case 0:{
rs = 2048;
break;
}
case 1:{
rs = 4096;
break;
}
case 2:{
rs = 8192;
break;
}
case 3:{
rs = 0;
break;
}
}
switch (sdccr_cs) {
case 0:{
cs = 256;
break;
}
case 1:{
cs = 512;
break;
}
case 2:{
cs = 1024;
break;
}
case 3:{
cs = 2048;
break;
}
}
switch (sdccr_mw) {
case 0:{
mw = 8;
break;
} /* 8 bytes = 64 bits */
case 1:{
mw = 4;
break;
} /* 4 bytes = 32 bits */
}
}
/* bytes per chip MB per chip num chips */
msize = (((rs * cs * mw) / (1024 * 1024)) * bs);
return (msize);
}
unsigned int __init tx4927_get_mem_size(void)
{
unsigned int c0;
unsigned int c1;
unsigned int c2;
unsigned int c3;
unsigned int total;
/* MVMCP -- need #defs for these registers */
c0 = tx4927_process_sdccr((u64 *) 0xff1f8000);
c1 = tx4927_process_sdccr((u64 *) 0xff1f8008);
c2 = tx4927_process_sdccr((u64 *) 0xff1f8010);
c3 = tx4927_process_sdccr((u64 *) 0xff1f8018);
total = c0 + c1 + c2 + c3;
return (total);
}
arch/mips/tx4927/common/tx4927_setup.c 0 → 100644
View file @ a16b2ff6
/*
* linux/arch/mips/tx4927/common/tx4927_setup.c
*
* common tx4927 setup stuff
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/irq.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/time.h>
#include <asm/tx4927/tx4927.h>
#undef DEBUG
void __init tx4927_setup(void);
void __init tx4927_time_init(void);
void __init tx4927_timer_setup(struct irqaction *irq);
void dump_cp0(char *key);
void (*__wbflush) (void);
static void tx4927_write_buffer_flush(void)
{
__asm__ __volatile__
("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
}
void __init tx4927_setup(void)
{
board_time_init = tx4927_time_init;
board_timer_setup = tx4927_timer_setup;
__wbflush = tx4927_write_buffer_flush;
#ifdef CONFIG_TOSHIBA_RBTX4927
{
extern void toshiba_rbtx4927_setup(void);
toshiba_rbtx4927_setup();
}
#endif
return;
}
void __init tx4927_time_init(void)
{
#ifdef CONFIG_TOSHIBA_RBTX4927
{
extern void toshiba_rbtx4927_time_init(void);
toshiba_rbtx4927_time_init();
}
#endif
#ifdef CONFIG_KGDB
{
printk("Calling breakpoint() -- start remote kgdb\n");
set_debug_traps();
breakpoint();
printk("Calling breakpoint() -- done\n");
}
#endif
return;
}
void __init tx4927_timer_setup(struct irqaction *irq)
{
u32 count;
u32 c1;
u32 c2;
setup_irq(TX4927_IRQ_CPU_TIMER, irq);
/* to generate the first timer interrupt */
c1 = read_c0_count();
count = c1 + (mips_counter_frequency / HZ);
write_c0_compare(count);
c2 = read_c0_count();
#ifdef CONFIG_TOSHIBA_RBTX4927
{
extern void toshiba_rbtx4927_timer_setup(struct irqaction
*irq);
toshiba_rbtx4927_timer_setup(irq);
}
#endif
return;
}
#ifdef DEBUG
void print_cp0(char *key, int num, char *name, u32 val)
{
printk("%s cp0:%02d:%s=0x%08x\n", key, num, name, val);
return;
}
indent: Standard input:25: Error:Unexpected end of file
void
dump_cp0(char *key)
{
if (key == NULL)
key = "";
print_cp0(key, 0, "INDEX ", read_c0_index());
print_cp0(key, 2, "ENTRYLO1", read_c0_entrylo0());
print_cp0(key, 3, "ENTRYLO2", read_c0_entrylo1());
print_cp0(key, 4, "CONTEXT ", read_c0_context());
print_cp0(key, 5, "PAGEMASK", read_c0_pagemask());
print_cp0(key, 6, "WIRED ", read_c0_wired());
//print_cp0(key, 8, "BADVADDR", read_c0_badvaddr());
print_cp0(key, 9, "COUNT ", read_c0_count());
print_cp0(key, 10, "ENTRYHI ", read_c0_entryhi());
print_cp0(key, 11, "COMPARE ", read_c0_compare());
print_cp0(key, 12, "STATUS ", read_c0_status());
print_cp0(key, 13, "CAUSE ", read_c0_cause() & 0xffff87ff);
print_cp0(key, 16, "CONFIG ", read_c0_config());
return;
}
void print_pic(char *key, u32 reg, char *name)
{
printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name,
TX4927_RD(reg));
return;
}
void dump_pic(char *key)
{
if (key == NULL)
key = "";
print_pic(key, 0xff1ff600, "IRDEN ");
print_pic(key, 0xff1ff604, "IRDM0 ");
print_pic(key, 0xff1ff608, "IRDM1 ");
print_pic(key, 0xff1ff610, "IRLVL0 ");
print_pic(key, 0xff1ff614, "IRLVL1 ");
print_pic(key, 0xff1ff618, "IRLVL2 ");
print_pic(key, 0xff1ff61c, "IRLVL3 ");
print_pic(key, 0xff1ff620, "IRLVL4 ");
print_pic(key, 0xff1ff624, "IRLVL5 ");
print_pic(key, 0xff1ff628, "IRLVL6 ");
print_pic(key, 0xff1ff62c, "IRLVL7 ");
print_pic(key, 0xff1ff640, "IRMSK ");
print_pic(key, 0xff1ff660, "IREDC ");
print_pic(key, 0xff1ff680, "IRPND ");
print_pic(key, 0xff1ff6a0, "IRCS ");
print_pic(key, 0xff1ff514, "IRFLAG1 "); /* don't read IRLAG0 -- it hangs system */
print_pic(key, 0xff1ff518, "IRPOL ");
print_pic(key, 0xff1ff51c, "IRRCNT ");
print_pic(key, 0xff1ff520, "IRMASKINT");
print_pic(key, 0xff1ff524, "IRMASKEXT");
return;
}
void print_addr(char *hdr, char *key, u32 addr)
{
printk("%s %s:0x%08x=0x%08x\n", hdr, key, addr, TX4927_RD(addr));
return;
}
void dump_180(char *key)
{
u32 i;
for (i = 0x80000180; i < 0x80000180 + 0x80; i += 4) {
print_addr("180", key, i);
}
return;
}
void dump_eh0(char *key)
{
int i;
extern unsigned long exception_handlers[];
for (i = (int) exception_handlers;
i < (int) (exception_handlers + 20); i += 4) {
print_addr("eh0", key, i);
}
return;
}
void pk0(void)
{
volatile u32 val;
__asm__ __volatile__("ori %0, $26, 0":"=r"(val)
);
printk("k0=[0x%08x]\n", val);
}
#endif
arch/mips/tx4927/toshiba_rbtx4927/Makefile 0 → 100644
View file @ a16b2ff6
obj-y += toshiba_rbtx4927_prom.o
obj-y += toshiba_rbtx4927_setup.o
obj-y += toshiba_rbtx4927_irq.o
obj-$(CONFIG_PCI) += toshiba_rbtx4927_pci_fixup.o
obj-$(CONFIG_PCI) += toshiba_rbtx4927_pci_ops.o
EXTRA_AFLAGS := $(CFLAGS)
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c 0 → 100644
View file @ a16b2ff6
/*
* linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
*
* Toshiba RBTX4927 specific interrupt handlers
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
IRQ Device
00 RBTX4927-ISA/00
01 RBTX4927-ISA/01 PS2/Keyboard
02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
03 RBTX4927-ISA/03
04 RBTX4927-ISA/04
05 RBTX4927-ISA/05
06 RBTX4927-ISA/06
07 RBTX4927-ISA/07
08 RBTX4927-ISA/08
09 RBTX4927-ISA/09
10 RBTX4927-ISA/10
11 RBTX4927-ISA/11
12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
13 RBTX4927-ISA/13
14 RBTX4927-ISA/14 IDE
15 RBTX4927-ISA/15
16 TX4927-CP0/00 Software 0
17 TX4927-CP0/01 Software 1
18 TX4927-CP0/02 Cascade TX4927-CP0
19 TX4927-CP0/03 Multiplexed -- do not use
20 TX4927-CP0/04 Multiplexed -- do not use
21 TX4927-CP0/05 Multiplexed -- do not use
22 TX4927-CP0/06 Multiplexed -- do not use
23 TX4927-CP0/07 CPU TIMER
24 TX4927-PIC/00
25 TX4927-PIC/01
26 TX4927-PIC/02
27 TX4927-PIC/03 Cascade RBTX4927-IOC
28 TX4927-PIC/04
29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
30 TX4927-PIC/06
31 TX4927-PIC/07
32 TX4927-PIC/08 TX4927 SerialIO Channel 0
33 TX4927-PIC/09 TX4927 SerialIO Channel 1
34 TX4927-PIC/10
35 TX4927-PIC/11
36 TX4927-PIC/12
37 TX4927-PIC/13
38 TX4927-PIC/14
39 TX4927-PIC/15
40 TX4927-PIC/16 TX4927 PCI PCI-C
41 TX4927-PIC/17
42 TX4927-PIC/18
43 TX4927-PIC/19
44 TX4927-PIC/20
45 TX4927-PIC/21
46 TX4927-PIC/22 TX4927 PCI PCI-ERR
47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
48 TX4927-PIC/24
49 TX4927-PIC/25
50 TX4927-PIC/26
51 TX4927-PIC/27
52 TX4927-PIC/28
53 TX4927-PIC/29
54 TX4927-PIC/30
55 TX4927-PIC/31
56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4]
57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5]
58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6]
60 RBTX4927-IOC/04
61 RBTX4927-IOC/05
62 RBTX4927-IOC/06
63 RBTX4927-IOC/07
NOTES:
SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
SouthBridge/ISA/pin=0 no pci irq used by this device
SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
SouthBridge/PMC/pin=0 no pci irq used by this device
SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/timex.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <linux/version.h>
#include <linux/bootmem.h>
#include <linux/blk.h>
#ifdef CONFIG_RTC_DS1742
#include <asm/rtc_ds1742.h>
#endif
#ifdef CONFIG_TOSHIBA_FPCIB0
#include <asm/smsc_fdc37m81x.h>
#endif
#include <asm/tx4927/toshiba_rbtx4927.h>
#undef TOSHIBA_RBTX4927_IRQ_DEBUG
#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
#define TOSHIBA_RBTX4927_IRQ_NONE 0x00000000
#define TOSHIBA_RBTX4927_IRQ_INFO ( 1 << 0 )
#define TOSHIBA_RBTX4927_IRQ_WARN ( 1 << 1 )
#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 )
#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
#define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP ( 1 << 11 )
#define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN ( 1 << 12 )
#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
#define TOSHIBA_RBTX4927_IRQ_IOC_MASK ( 1 << 15 )
#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 )
#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
#define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP ( 1 << 21 )
#define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN ( 1 << 22 )
#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
#define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ( 1 << 26 )
#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
#endif
#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
static const u32 toshiba_rbtx4927_irq_debug_flag =
(TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
// | TOSHIBA_RBTX4927_IRQ_IOC_MASK
// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
);
#endif
#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
{ \
char tmp[100]; \
sprintf( tmp, str ); \
printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
}
#else
#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...)
#endif
#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7
#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
#define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
#define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
#define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
extern int tx4927_using_backplane;
#ifdef CONFIG_TOSHIBA_FPCIB0
extern void enable_8259A_irq(unsigned int irq);
extern void disable_8259A_irq(unsigned int irq);
extern void mask_and_ack_8259A(unsigned int irq);
#endif
static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq);
static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq);
static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq);
static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
#ifdef CONFIG_TOSHIBA_FPCIB0
static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq);
static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq);
static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
#endif
static spinlock_t toshiba_rbtx4927_ioc_lock = SPIN_LOCK_UNLOCKED;
#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
static struct hw_interrupt_type toshiba_rbtx4927_irq_ioc_type = {
typename:TOSHIBA_RBTX4927_IOC_NAME,
startup:toshiba_rbtx4927_irq_ioc_startup,
shutdown:toshiba_rbtx4927_irq_ioc_shutdown,
enable:toshiba_rbtx4927_irq_ioc_enable,
disable:toshiba_rbtx4927_irq_ioc_disable,
ack:toshiba_rbtx4927_irq_ioc_mask_and_ack,
end:toshiba_rbtx4927_irq_ioc_end,
set_affinity:NULL
};
#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
#ifdef CONFIG_TOSHIBA_FPCIB0
#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
static struct hw_interrupt_type toshiba_rbtx4927_irq_isa_type = {
typename:TOSHIBA_RBTX4927_ISA_NAME,
startup:toshiba_rbtx4927_irq_isa_startup,
shutdown:toshiba_rbtx4927_irq_isa_shutdown,
enable:toshiba_rbtx4927_irq_isa_enable,
disable:toshiba_rbtx4927_irq_isa_disable,
ack:toshiba_rbtx4927_irq_isa_mask_and_ack,
end:toshiba_rbtx4927_irq_isa_end,
set_affinity:NULL
};
#endif
u32 bit2num(u32 num)
{
u32 i;
for (i = 0; i < (sizeof(num) * 8); i++) {
if (num & (1 << i)) {
return (i);
}
}
return (0);
}
int toshiba_rbtx4927_irq_nested(int sw_irq)
{
u32 level3;
u32 level4;
u32 level5;
level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
if (level3) {
sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
goto RETURN;
}
}
#ifdef CONFIG_TOSHIBA_FPCIB0
{
if (tx4927_using_backplane) {
outb(0x0A, 0x20);
level4 = inb(0x20) & 0xff;
if (level4) {
sw_irq =
TOSHIBA_RBTX4927_IRQ_ISA_BEG +
bit2num(level4);
if (sw_irq !=
TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
goto RETURN;
}
}
outb(0x0A, 0xA0);
level5 = inb(0xA0) & 0xff;
if (level5) {
sw_irq =
TOSHIBA_RBTX4927_IRQ_ISA_MID +
bit2num(level5);
goto RETURN;
}
}
}
#endif
RETURN:
return (sw_irq);
}
//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, 0, s, NULL, NULL }
#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, SA_SHIRQ, 0, s, NULL, NULL }
static struct irqaction toshiba_rbtx4927_irq_ioc_action =
TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
#ifdef CONFIG_TOSHIBA_FPCIB0
static struct irqaction toshiba_rbtx4927_irq_isa_master =
TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
static struct irqaction toshiba_rbtx4927_irq_isa_slave =
TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
#endif
/**********************************************************************************/
/* Functions for ioc */
/**********************************************************************************/
static void __init toshiba_rbtx4927_irq_ioc_init(void)
{
int i;
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
"beg=%d end=%d\n",
TOSHIBA_RBTX4927_IRQ_IOC_BEG,
TOSHIBA_RBTX4927_IRQ_IOC_END);
for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 3;
irq_desc[i].handler = &toshiba_rbtx4927_irq_ioc_type;
}
setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
&toshiba_rbtx4927_irq_ioc_action);
return;
}
static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
toshiba_rbtx4927_irq_ioc_enable(irq);
return (0);
}
static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
toshiba_rbtx4927_irq_ioc_disable(irq);
return;
}
static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
{
unsigned long flags;
volatile unsigned char v;
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
return;
}
static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
{
unsigned long flags;
volatile unsigned char v;
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
return;
}
static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
toshiba_rbtx4927_irq_ioc_disable(irq);
return;
}
static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
toshiba_rbtx4927_irq_ioc_enable(irq);
}
return;
}
/**********************************************************************************/
/* Functions for isa */
/**********************************************************************************/
#ifdef CONFIG_TOSHIBA_FPCIB0
static void __init toshiba_rbtx4927_irq_isa_init(void)
{
int i;
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
"beg=%d end=%d\n",
TOSHIBA_RBTX4927_IRQ_ISA_BEG,
TOSHIBA_RBTX4927_IRQ_ISA_END);
for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth =
((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
irq_desc[i].handler = &toshiba_rbtx4927_irq_isa_type;
}
setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
&toshiba_rbtx4927_irq_isa_master);
setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
&toshiba_rbtx4927_irq_isa_slave);
/* make sure we are looking at IRR (not ISR) */
outb(0x0A, 0x20);
outb(0x0A, 0xA0);
return;
}
#endif
#ifdef CONFIG_TOSHIBA_FPCIB0
static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
toshiba_rbtx4927_irq_isa_enable(irq);
return (0);
}
#endif
#ifdef CONFIG_TOSHIBA_FPCIB0
static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
toshiba_rbtx4927_irq_isa_disable(irq);
return;
}
#endif
#ifdef CONFIG_TOSHIBA_FPCIB0
static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
enable_8259A_irq(irq);
return;
}
#endif
#ifdef CONFIG_TOSHIBA_FPCIB0
static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
disable_8259A_irq(irq);
return;
}
#endif
#ifdef CONFIG_TOSHIBA_FPCIB0
static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
mask_and_ack_8259A(irq);
return;
}
#endif
#ifdef CONFIG_TOSHIBA_FPCIB0
static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
{
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ,
"irq=%d\n", irq);
if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
|| irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
"bad irq=%d\n", irq);
panic("\n");
}
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
toshiba_rbtx4927_irq_isa_enable(irq);
}
return;
}
#endif
void __init init_IRQ(void)
{
extern void tx4927_irq_init(void);
cli();
tx4927_irq_init();
toshiba_rbtx4927_irq_ioc_init();
#ifdef CONFIG_TOSHIBA_FPCIB0
{
if (tx4927_using_backplane) {
toshiba_rbtx4927_irq_isa_init();
}
}
#endif
#ifdef CONFIG_PCI
{
extern void toshiba_rbtx4927_pci_irq_init(void);
toshiba_rbtx4927_pci_irq_init();
}
#endif
wbflush();
return;
}
void toshiba_rbtx4927_irq_dump(char *key)
{
#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
{
u32 i, j = 0;
for (i = 0; i < NR_IRQS; i++) {
if (strcmp(irq_desc[i].handler->typename, "none")
== 0)
continue;
if ((i >= 1)
&& (irq_desc[i - 1].handler->typename ==
irq_desc[i].handler->typename)) {
j++;
} else {
j = 0;
}
TOSHIBA_RBTX4927_IRQ_DPRINTK
(TOSHIBA_RBTX4927_IRQ_INFO,
"%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
key, i, i, irq_desc[i].status,
(u32) irq_desc[i].handler,
(u32) irq_desc[i].action,
(u32) (irq_desc[i].action ? irq_desc[i].
action->handler : 0),
irq_desc[i].depth,
irq_desc[i].handler->typename, j);
}
}
#endif
return;
}
void toshiba_rbtx4927_irq_dump_pics(char *s)
{
u32 level0_m;
u32 level0_s;
u32 level1_m;
u32 level1_s;
u32 level2;
u32 level2_p;
u32 level2_s;
u32 level3_m;
u32 level3_s;
u32 level4_m;
u32 level4_s;
u32 level5_m;
u32 level5_s;
if (s == NULL)
s = "null";
level0_m = (read_c0_status() & 0x0000ff00) >> 8;
level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
level1_m = level0_m;
level1_s = level0_s & 0x87;
level2 = TX4927_RD(0xff1ff6a0);
level2_p = (((level2 & 0x10000)) ? 0 : 1);
level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
level4_m = inb(0x21);
outb(0x0A, 0x20);
level4_s = inb(0x20);
level5_m = inb(0xa1);
outb(0x0A, 0xa0);
level5_s = inb(0xa0);
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
"dump_raw_pic() ");
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
"cp0:m=0x%02x/s=0x%02x ", level0_m,
level0_s);
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
"cp0:m=0x%02x/s=0x%02x ", level1_m,
level1_s);
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
"pic:e=0x%02x/s=0x%02x ", level2_p,
level2_s);
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
"ioc:m=0x%02x/s=0x%02x ", level3_m,
level3_s);
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
"sbm:m=0x%02x/s=0x%02x ", level4_m,
level4_s);
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
"sbs:m=0x%02x/s=0x%02x ", level5_m,
level5_s);
TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
s);
return;
}
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_pci_fixup.c 0 → 100644
View file @ a16b2ff6
/*
*
* BRIEF MODULE DESCRIPTION
* Board specific pci fixups for the Toshiba rbtx4927
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/tx4927/tx4927.h>
#include <asm/tx4927/tx4927_pci.h>
#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
void __init pcibios_fixup_resources(struct pci_dev *dev)
{
/* will need to fixup IO resources */
}
void __init pcibios_fixup(void)
{
/* nothing to do here */
}
/* look up table for backplane pci irq for slots 17-20 by pin # */
static unsigned char backplane_pci_irq[4][4] = {
/* PJ6 SLOT: 17, PIN: 1 */ {TX4927_IRQ_IOC_PCIA,
/* PJ6 SLOT: 17, PIN: 2 */
TX4927_IRQ_IOC_PCIB,
/* PJ6 SLOT: 17, PIN: 3 */
TX4927_IRQ_IOC_PCIC,
/* PJ6 SLOT: 17, PIN: 4 */
TX4927_IRQ_IOC_PCID},
/* SB SLOT: 18, PIN: 1 */ {TX4927_IRQ_IOC_PCIB,
/* SB SLOT: 18, PIN: 2 */
TX4927_IRQ_IOC_PCIC,
/* SB SLOT: 18, PIN: 3 */
TX4927_IRQ_IOC_PCID,
/* SB SLOT: 18, PIN: 4 */
TX4927_IRQ_IOC_PCIA},
/* PJ5 SLOT: 19, PIN: 1 */ {TX4927_IRQ_IOC_PCIC,
/* PJ5 SLOT: 19, PIN: 2 */
TX4927_IRQ_IOC_PCID,
/* PJ5 SLOT: 19, PIN: 3 */
TX4927_IRQ_IOC_PCIA,
/* PJ5 SLOT: 19, PIN: 4 */
TX4927_IRQ_IOC_PCIB},
/* PJ4 SLOT: 20, PIN: 1 */ {TX4927_IRQ_IOC_PCID,
/* PJ4 SLOT: 20, PIN: 2 */
TX4927_IRQ_IOC_PCIA,
/* PJ4 SLOT: 20, PIN: 3 */
TX4927_IRQ_IOC_PCIB,
/* PJ4 SLOT: 20, PIN: 4 */
TX4927_IRQ_IOC_PCIC}
};
int pci_get_irq(struct pci_dev *dev, int pin)
{
unsigned char irq = pin;
DBG("pci_get_irq: pin is %d\n", pin);
/* IRQ rotation */
irq--; /* 0-3 */
if (dev->bus->parent == NULL &&
PCI_SLOT(dev->devfn) == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
printk("Onboard PCI_SLOT(dev->devfn) is %d\n",
PCI_SLOT(dev->devfn));
/* IDSEL=A23 is tx4927 onboard pci slot */
irq = (irq + PCI_SLOT(dev->devfn)) % 4;
irq++; /* 1-4 */
DBG("irq is now %d\n", irq);
switch (irq) {
case 1:
irq = TX4927_IRQ_IOC_PCIA;
break;
case 2:
irq = TX4927_IRQ_IOC_PCIB;
break;
case 3:
irq = TX4927_IRQ_IOC_PCIC;
break;
case 4:
irq = TX4927_IRQ_IOC_PCID;
break;
}
} else {
/* PCI Backplane */
DBG("PCI Backplane PCI_SLOT(dev->devfn) is %d\n",
PCI_SLOT(dev->devfn));
irq = backplane_pci_irq[PCI_SLOT(dev->devfn) - 17][irq];
}
DBG("assigned irq %d\n", irq);
return irq;
}
#ifdef TX4927_SUPPORT_PCI_66
extern int tx4927_pci66;
extern void tx4927_pci66_setup(void);
#endif
extern void tx4927_pci_setup(void);
#ifdef TX4927_SUPPORT_PCI_66
int tx4927_pci66_check(void)
{
struct pci_dev *dev;
unsigned short stat;
int cap66 = 1;
if (tx4927_pci66 < 0)
return 0;
/* check 66MHz capability */
pci_for_each_dev(dev) {
if (cap66) {
pci_read_config_word(dev, PCI_STATUS, &stat);
if (!(stat & PCI_STATUS_66MHZ)) {
printk(KERN_INFO
"PCI: %02x:%02x not 66MHz capable.\n",
dev->bus->number, dev->devfn);
cap66 = 0;
}
}
}
return cap66;
}
#endif
#ifdef DEBUG
void do_it(u32 offset, u32 reg)
{
volatile u32 a1;
volatile u32 a2;
volatile u32 v1;
volatile u32 v2;
a1 = 0xff1f0000 + offset + reg;
a2 = a1 + 4;
v1 = *(volatile u32 *) a1;
v2 = *(volatile u32 *) a2;
if (v1)
printk("TX4927 0x%08x 0x%08x\n", a1, v1);
if (v2)
printk("TX4927 0x%08x 0x%08x\n", a2, v2);
}
void do_it1(u32 base, u32 r)
{
do_it(base, r);
}
void do_it2(u32 base, u32 start, u32 stop)
{
u32 r;
for (r = start; r <= stop; r += 8) {
do_it(base, r);
}
}
void dump_config(void)
{
unsigned long id;
unsigned long j;
struct pci_dev *dev;
printk("----------------------pci\n");
pci_for_each_dev(dev) {
for (j = 0; j < 64; j++) {
pci_read_config_dword(dev, j * 4, &id);
if (id == 0)
continue;
printk
("dev 0x%02x 0x%02x:0x%02x -- 0x%02x-0x%02x 0x%08x\n",
dev->devfn, PCI_SLOT(dev->devfn),
PCI_FUNC(dev->devfn), (j * 4) + 3, (j * 4),
id);
}
printk("dev 0x%02x \n", dev->devfn);
}
printk("----------------------sdram\n");
do_it2(0x8000, 0x00, 0x18);
do_it1(0x8000, 0x40);
do_it1(0x8000, 0x58);
printk("----------------------ebus\n");
do_it2(0x9000, 0x00, 0x38);
printk("----------------------ecc\n");
do_it2(0xa000, 0x00, 0x08);
printk("----------------------dmac\n");
do_it2(0xb000, 0x00, 0xf8);
/* b1xx */
printk("----------------------pci\n");
/* d */
printk("----------------------cfg\n");
do_it2(0xe000, 0x00, 0x20);
do_it1(0xe000, 0x30);
do_it1(0xe000, 0x48);
printk("----------------------timers\n");
do_it2(0xf000, 0x00, 0xf0);
do_it2(0xf100, 0x00, 0xf0);
do_it2(0xf200, 0x00, 0xf0);
printk("----------------------serial\n");
do_it2(0xf300, 0x00, 0x20);
do_it2(0xf400, 0x00, 0x20);
printk("----------------------parallel\n");
do_it2(0xf500, 0x00, 0x0c);
printk("----------------------pic\n");
do_it2(0xf500, 0x10, 0x24);
do_it2(0xf600, 0x00, 0x2c);
do_it1(0xf600, 0x40);
do_it1(0xf600, 0x60);
do_it1(0xf600, 0x80);
do_it1(0xf600, 0xa0);
printk("----------------------aclink\n");
do_it2(0xf700, 0x00, 0xfc);
printk("----------------------done\n");
}
#endif
void __init pcibios_fixup_irqs(void)
{
unsigned char pin;
unsigned char irq;
struct pci_dev *dev;
unsigned int id;
#ifdef TX4927_SUPPORT_PCI_66
{
if (tx4927_pci66_check()) {
tx4927_pci66_setup();
tx4927_pci_setup(); /* Reinitialize PCIC */
}
}
#endif
pci_for_each_dev(dev) {
DBG("FIXUP:\n");
DBG(" devfn=0x%02x (0x%02x:0x%02x)\n",
dev->devfn, PCI_SLOT(dev->devfn),
PCI_FUNC(dev->devfn));
pci_read_config_dword(dev, PCI_VENDOR_ID, &id);
DBG(" id=0x%08x\n", id);
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
DBG(" line=0x%02x/%d\n", irq, irq);
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
DBG(" pin=%d\n", pin);
#ifdef DEBUG
{
unsigned int tmp;
pci_read_config_dword(dev, 0x10, &tmp);
DBG(" bar0:0x10=0x%08x\n", tmp);
pci_read_config_dword(dev, 0x14, &tmp);
DBG(" bar1:0x14=0x%08x\n", tmp);
pci_read_config_dword(dev, 0x1c, &tmp);
DBG(" bar2:0x1c=0x%08x\n", tmp);
pci_read_config_dword(dev, 0x20, &tmp);
DBG(" bar3:0x20=0x%08x\n", tmp);
pci_read_config_dword(dev, 0x24, &tmp);
DBG(" bar4:0x24=0x%08x\n", tmp);
}
#endif
irq = 0;
if (id == 0x91301055) { /* ide */
irq = 14;
}
if (pin == 0) {
DBG(" auto irq (now=%d) -- skipping pin=0\n", irq);
} else if (irq) {
DBG(" auto irq (now=%d) -- skipping hardcoded irq\n", irq);
} else {
DBG(" auto irq (was=%d)\n", irq);
irq = pci_get_irq(dev, pin);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
irq);
dev->irq = irq;
DBG(" auto irq (now=%d)\n", irq);
}
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
printk(KERN_INFO
"PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n",
dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn),
PCI_FUNC(dev->devfn), irq);
}
}
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_pci_ops.c 0 → 100644
View file @ a16b2ff6
/*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
*
* Define the pci_ops for the Toshiba rbtx4927
*
* Much of the code is derived from the original DDB5074 port by
* Geert Uytterhoeven <geert@sonycom.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/addrspace.h>
#include <asm/pci_channel.h>
#include <asm/tx4927/tx4927_pci.h>
#include <asm/debug.h>
/* initialize in setup */
struct resource pci_io_resource = {
"pci IO space",
(PCIBIOS_MIN_IO),
((PCIBIOS_MIN_IO) + (TX4927_PCIIO_SIZE)) - 1,
IORESOURCE_IO
};
/* initialize in setup */
struct resource pci_mem_resource = {
"pci memory space",
TX4927_PCIMEM,
TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1,
IORESOURCE_MEM
};
extern struct pci_ops tx4927_pci_ops;
struct pci_channel mips_pci_channels[] = {
/* h/w only supports devices 0x00 to 0x14 */
{&tx4927_pci_ops, &pci_io_resource, &pci_mem_resource,
PCI_DEVFN(0x00, 0), PCI_DEVFN(0x14, 7)},
{NULL, NULL, NULL, 0, 0}
};
unsigned int pcibios_assign_all_busses(void)
{
return 1;
}
static int
mkaddr(unsigned char bus, unsigned char dev_fn, unsigned char where,
int *flagsp)
{
if (bus > 0) {
/* Type 1 configuration */
tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
} else {
if (dev_fn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
return -1;
/* Type 0 configuration */
tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
((dev_fn & 0xff) << 0x08) | (where & 0xfc);
}
/* clear M_ABORT and Disable M_ABORT Int. */
tx4927_pcicptr->pcistatus =
(tx4927_pcicptr->pcistatus & 0x0000ffff) |
(PCI_STATUS_REC_MASTER_ABORT << 16);
tx4927_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
return 0;
}
static int check_abort(int flags)
{
int code = PCIBIOS_SUCCESSFUL;
if (tx4927_pcicptr->
pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
tx4927_pcicptr->pcistatus =
(tx4927_pcicptr->
pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
<< 16);
tx4927_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
code = PCIBIOS_DEVICE_NOT_FOUND;
// printk("returning PCIBIOS_DEVICE_NOT_FOUND\n");
}
return code;
}
/*
* We can't address 8 and 16 bit words directly. Instead we have to
* read/write a 32bit word and mask/modify the data we actually want.
*/
static int tx4927_pcibios_read_config_byte(struct pci_dev *dev,
int where, unsigned char *val)
{
int flags, retval;
unsigned char bus, func_num;
db_assert((where & 3) == 0);
db_assert(where < (1 << 8));
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
db_assert(bus != 0);
} else {
bus = 0;
}
func_num = PCI_FUNC(dev->devfn);
if (mkaddr(bus, dev->devfn, where, &flags))
return -1;
#ifdef __BIG_ENDIAN
*val =
*(volatile u8 *) ((ulong) & tx4927_pcicptr->
g2pcfgdata | ((where & 3) ^ 3));
#else
*val =
*(volatile u8 *) ((ulong) & tx4927_pcicptr->
g2pcfgdata | (where & 3));
#endif
retval = check_abort(flags);
if (retval == PCIBIOS_DEVICE_NOT_FOUND)
*val = 0xff;
//printk("CFG R1 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, *val );
return retval;
}
static int tx4927_pcibios_read_config_word(struct pci_dev *dev,
int where, unsigned short *val)
{
int flags, retval;
unsigned char bus, func_num;
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
db_assert((where & 3) == 0);
db_assert(where < (1 << 8));
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
db_assert(bus != 0);
} else {
bus = 0;
}
func_num = PCI_FUNC(dev->devfn);
if (mkaddr(bus, dev->devfn, where, &flags))
return -1;
#ifdef __BIG_ENDIAN
*val =
*(volatile u16 *) ((ulong) & tx4927_pcicptr->
g2pcfgdata | ((where & 3) ^ 2));
#else
*val =
*(volatile u16 *) ((ulong) & tx4927_pcicptr->
g2pcfgdata | (where & 3));
#endif
retval = check_abort(flags);
if (retval == PCIBIOS_DEVICE_NOT_FOUND)
*val = 0xffff;
//printk("CFG R2 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, *val );
return retval;
}
static int tx4927_pcibios_read_config_dword(struct pci_dev *dev,
int where, unsigned int *val)
{
int flags, retval;
unsigned char bus, func_num;
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
db_assert((where & 3) == 0);
db_assert(where < (1 << 8));
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
db_assert(bus != 0);
} else {
bus = 0;
}
func_num = PCI_FUNC(dev->devfn);
if (mkaddr(bus, dev->devfn, where, &flags))
return -1;
*val = tx4927_pcicptr->g2pcfgdata;
retval = check_abort(flags);
if (retval == PCIBIOS_DEVICE_NOT_FOUND)
*val = 0xffffffff;
//printk("CFG R4 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, *val );
return retval;
}
static int tx4927_pcibios_write_config_byte(struct pci_dev *dev,
int where, unsigned char val)
{
int flags;
unsigned char bus, func_num;
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
db_assert(bus != 0);
} else {
bus = 0;
}
func_num = PCI_FUNC(dev->devfn);
if (mkaddr(bus, dev->devfn, where, &flags))
return -1;
#ifdef __BIG_ENDIAN
*(volatile u8 *) ((ulong) & tx4927_pcicptr->
g2pcfgdata | ((where & 3) ^ 3)) = val;
#else
*(volatile u8 *) ((ulong) & tx4927_pcicptr->
g2pcfgdata | (where & 3)) = val;
#endif
//printk("CFG W1 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, val );
return check_abort(flags);
}
static int tx4927_pcibios_write_config_word(struct pci_dev *dev,
int where, unsigned short val)
{
int flags;
unsigned char bus, func_num;
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
db_assert(bus != 0);
} else {
bus = 0;
}
func_num = PCI_FUNC(dev->devfn);
if (mkaddr(bus, dev->devfn, where, &flags))
return -1;
#ifdef __BIG_ENDIAN
*(volatile u16 *) ((ulong) & tx4927_pcicptr->
g2pcfgdata | ((where & 3) ^ 2)) = val;
#else
*(volatile u16 *) ((ulong) & tx4927_pcicptr->
g2pcfgdata | (where & 3)) = val;
#endif
//printk("CFG W2 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, val );
return check_abort(flags);
}
static int tx4927_pcibios_write_config_dword(struct pci_dev *dev,
int where, unsigned int val)
{
int flags;
unsigned char bus, func_num;
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
db_assert(bus != 0);
} else {
bus = 0;
}
func_num = PCI_FUNC(dev->devfn);
if (mkaddr(bus, dev->devfn, where, &flags))
return -1;
tx4927_pcicptr->g2pcfgdata = val;
//printk("CFG W4 0x%02x 0x%02x 0x%08x\n", dev->devfn, where, val );
return check_abort(flags);
}
struct pci_ops tx4927_pci_ops = {
tx4927_pcibios_read_config_byte,
tx4927_pcibios_read_config_word,
tx4927_pcibios_read_config_dword,
tx4927_pcibios_write_config_byte,
tx4927_pcibios_write_config_word,
tx4927_pcibios_write_config_dword
};
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c 0 → 100644
View file @ a16b2ff6
/*
* rbtx4927 specific prom routines
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/tx4927/tx4927.h>
#ifndef COMMAND_LINE_SIZE
#define COMMAND_LINE_SIZE CL_SIZE
#endif
char arcs_cmdline[COMMAND_LINE_SIZE] = "console=ttyS0,38400 ip=any root=nfs rw";
void __init prom_init_cmdline(int argc, char **argv)
{
int i; /* Always ignore the "-c" at argv[0] */
/* ignore all built-in args if any f/w args given */
if (argc > 1) {
*arcs_cmdline = '\0';
}
for (i = 1; i < argc; i++) {
if (i != 1) {
strcat(arcs_cmdline, " ");
}
strcat(arcs_cmdline, argv[i]);
}
}
void __init prom_init(int argc, char **argv, char **envp, int *pvec)
{
extern int tx4927_get_mem_size(void);
int msize;
const char* toshiba_name_list[] = GROUP_TOSHIBA_NAMES;
extern char* toshiba_name;
prom_init_cmdline(argc, argv);
mips_machgroup = MACH_GROUP_TOSHIBA;
if ((read_c0_prid() & 0xff) == PRID_REV_TX4927)
mips_machtype = MACH_TOSHIBA_RBTX4927;
else
mips_machtype = MACH_TOSHIBA_RBTX4937;
toshiba_name = toshiba_name_list[mips_machtype];
msize = tx4927_get_mem_size();
add_memory_region(0, msize << 20, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
}
const char *get_system_type(void)
{
return "Toshiba RBTX4927/RBTX4937";
}
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c 0 → 100644
View file @ a16b2ff6
/*
* Toshiba rbtx4927 specific setup
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* Copyright (C) 1996, 1997, 2001 Ralf Baechle
* Copyright (C) 2000 RidgeRun, Inc.
* Author: RidgeRun, Inc.
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* Copyright 2002 MontaVista Software Inc.
* Author: Michael Pruznick, michael_pruznick@mvista.com
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/timex.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <linux/version.h>
#include <linux/bootmem.h>
#include <linux/blk.h>
#include <linux/console.h>
#ifdef CONFIG_RTC_DS1742
#include <asm/rtc_ds1742.h>
#endif
#ifdef CONFIG_TOSHIBA_FPCIB0
#include <asm/smsc_fdc37m81x.h>
#endif
#include <asm/tx4927/toshiba_rbtx4927.h>
#ifdef CONFIG_PCI
#include <asm/tx4927/tx4927_pci.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/pci_channel.h>
#endif
#ifdef CONFIG_PC_KEYB
#include <asm/keyboard.h>
#endif
#ifdef CONFIG_BLK_DEV_IDEPCI
#include <linux/hdreg.h>
#include <asm/ptrace.h>
#include <linux/ide.h>
extern struct ide_ops std_ide_ops;
#endif
#undef TOSHIBA_RBTX4927_SETUP_DEBUG
#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
#define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000
#define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 )
#define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 )
#define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 )
#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
#define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 )
#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
#define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 )
#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
#endif
#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
static const u32 toshiba_rbtx4927_setup_debug_flag =
(TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
| TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
#endif
#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
{ \
char tmp[100]; \
sprintf( tmp, str ); \
printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
}
#else
#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
#endif
/* These functions are used for rebooting or halting the machine*/
extern void toshiba_rbtx4927_restart(char *command);
extern void toshiba_rbtx4927_halt(void);
extern void toshiba_rbtx4927_power_off(void);
int tx4927_using_backplane = 0;
extern void gt64120_time_init(void);
extern void toshiba_rbtx4927_irq_setup(void);
#ifdef CONFIG_PCI
#define CONFIG_TX4927BUG_WORKAROUND
#undef TX4927_SUPPORT_COMMAND_IO
#undef TX4927_SUPPORT_PCI_66
int tx4927_cpu_clock = 100000000; /* 100MHz */
unsigned long mips_pci_io_base;
unsigned long mips_pci_io_size;
unsigned long mips_pci_mem_base;
unsigned long mips_pci_mem_size;
/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
unsigned long mips_pci_io_pciaddr = 0;
unsigned long mips_memory_upper;
static int tx4927_ccfg_toeon = 1;
static int tx4927_pcic_trdyto = 0; /* default: disabled */
unsigned long tx4927_ce_base[8];
void tx4927_pci_setup(void);
void tx4927_reset_pci_pcic(void);
#ifdef TX4927_SUPPORT_PCI_66
void tx4927_pci66_setup(void);
extern int tx4927_pci66_check(void);
#endif
int tx4927_pci66 = 0; /* 0:auto */
#endif
char *toshiba_name = "";
#ifdef CONFIG_PCI
void tx4927_dump_pcic_settings(void)
{
printk("%s pcic settings:",toshiba_name);
{
int i;
unsigned long *preg = (unsigned long *) tx4927_pcicptr;
for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4) {
if (i % 32 == 0)
printk("\n%04x:", i);
if (preg == &tx4927_pcicptr->g2pintack
|| preg == &tx4927_pcicptr->g2pspc
#ifdef CONFIG_TX4927BUG_WORKAROUND
|| preg == &tx4927_pcicptr->g2pcfgadrs
|| preg == &tx4927_pcicptr->g2pcfgdata
#endif
) {
printk(" XXXXXXXX");
preg++;
continue;
}
printk(" %08lx", *preg++);
if (preg == &tx4927_pcicptr->g2pcfgadrs)
break;
}
printk("\n");
}
}
static void tx4927_pcierr_interrupt(int irq, void *dev_id,
struct pt_regs *regs)
{
extern void tx4927_dump_pcic_settings(void);
#ifdef CONFIG_BLK_DEV_IDEPCI
/* ignore MasterAbort for ide probing... */
if (irq == TX4927_IRQ_IRC_PCIERR &&
((tx4927_pcicptr->pcistatus >> 16) & 0xf900) ==
PCI_STATUS_REC_MASTER_ABORT) {
tx4927_pcicptr->pcistatus =
(tx4927_pcicptr->
pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
<< 16);
return;
}
#endif
printk("PCI error interrupt (irq 0x%x).\n", irq);
printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
(unsigned short) (tx4927_pcicptr->pcistatus >> 16),
tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus);
printk("ccfg:%08lx, tear:%02lx_%08lx\n",
(unsigned long) tx4927_ccfgptr->ccfg,
(unsigned long) (tx4927_ccfgptr->tear >> 32),
(unsigned long) tx4927_ccfgptr->tear);
show_regs(regs);
//tx4927_dump_pcic_settings();
panic("PCI error at PC:%08lx.", regs->cp0_epc);
}
static struct irqaction pcic_action = {
tx4927_pcierr_interrupt, 0, 0, "PCI-C", NULL, NULL
};
static struct irqaction pcierr_action = {
tx4927_pcierr_interrupt, 0, 0, "PCI-ERR", NULL, NULL
};
void __init toshiba_rbtx4927_pci_irq_init(void)
{
setup_irq(TX4927_IRQ_IRC_PCIC, &pcic_action);
setup_irq(TX4927_IRQ_IRC_PCIERR, &pcierr_action);
return;
}
void tx4927_reset_pci_pcic(void)
{
/* Reset PCI Bus */
*tx4927_pcireset_ptr = 1;
/* Reset PCIC */
tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST;
udelay(10000);
/* clear PCIC reset */
tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
*tx4927_pcireset_ptr = 0;
}
#endif /* CONFIG_PCI */
#ifdef CONFIG_PCI
#ifdef TX4927_SUPPORT_PCI_66
void tx4927_pci66_setup(void)
{
int pciclk, pciclkin = 1;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI66,
"-\n");
if (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66)
return;
tx4927_reset_pci_pcic();
/* Assert M66EN */
tx4927_ccfgptr->ccfg |= TX4927_CCFG_PCI66;
/* set PCICLK 66MHz */
if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
unsigned int pcidivmode = 0;
pcidivmode =
(unsigned long) tx4927_ccfgptr->
ccfg & TX4927_CCFG_PCIDIVMODE_MASK;
if (tx4927_cpu_clock >= 170000000) {
/* CPU 200MHz */
pcidivmode = TX4927_CCFG_PCIDIVMODE_3;
pciclk = tx4927_cpu_clock / 3;
} else {
/* CPU 166MHz */
pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5;
pciclk = tx4927_cpu_clock * 2 / 5;
}
tx4927_ccfgptr->ccfg =
(tx4927_ccfgptr->ccfg & ~TX4927_CCFG_PCIDIVMODE_MASK)
| pcidivmode;
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCI66,
":PCICLK: ccfg:0x%08lx\n",
(unsigned long) tx4927_ccfgptr->ccfg);
} else {
int pciclk_setting = *tx4927_pci_clk_ptr;
pciclkin = 0;
pciclk = 66666666;
pciclk_setting &= ~TX4927_PCI_CLK_MASK;
pciclk_setting |= TX4927_PCI_CLK_66;
*tx4927_pci_clk_ptr = pciclk_setting;
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCI66,
"PCICLK: pci_clk:%02x\n", *tx4927_pci_clk_ptr);
}
udelay(10000);
/* clear PCIC reset */
tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
/* clear PCI reset */
*tx4927_pcireset_ptr = 0;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI66,
"+\n");
return;
}
#endif /* TX4927_SUPPORT_PCI_66 */
void print_pci_status(void)
{
printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus);
printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus);
}
static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
int top_bus, int busnr, int devfn)
{
static struct pci_dev dev;
static struct pci_bus bus;
dev.bus = &bus;
dev.sysdata = hose;
dev.devfn = devfn;
bus.number = busnr;
bus.ops = hose->pci_ops;
if (busnr != top_bus)
/* Fake a parent bus structure. */
bus.parent = &bus;
else
bus.parent = NULL;
return &dev;
}
#define EARLY_PCI_OP(rw, size, type) \
static int early_##rw##_config_##size(struct pci_channel *hose, \
int top_bus, int bus, int devfn, int offset, type value) \
{ \
return pci_##rw##_config_##size( \
fake_pci_dev(hose, top_bus, bus, devfn), \
offset, value); \
}
EARLY_PCI_OP(read, byte, u8 *)
EARLY_PCI_OP(read, word, u16 *)
EARLY_PCI_OP(read, dword, u32 *)
EARLY_PCI_OP(write, byte, u8)
EARLY_PCI_OP(write, word, u16)
EARLY_PCI_OP(write, dword, u32)
static int __init tx4927_pcibios_init(int busno, struct pci_channel *hose)
{
u32 pci_devfn;
int devfn_start = 0;
int devfn_stop = 0xff;
unsigned int id;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
"-\n");
if (hose->first_devfn)
devfn_start = hose->first_devfn;
if (hose->last_devfn)
devfn_stop = hose->last_devfn;
for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
early_read_config_dword(hose, busno, busno, pci_devfn,
PCI_VENDOR_ID, &id);
if (id == 0xffffffff) {
continue;
}
if (id == 0x94601055) {
u8 v08_64;
u32 v32_b0;
u8 v08_e1;
char *s = " sb/isa --";
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
s);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x64, &v08_64);
early_read_config_dword(hose, busno, busno,
pci_devfn, 0xb0, &v32_b0);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0xe1, &v08_e1);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x64 = 0x%02x\n", s, v08_64);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
/* serial irq control */
v08_64 = 0xd0;
/* serial irq pin */
v32_b0 |= 0x00010000;
/* ide irq on isa14 */
v08_e1 &= 0xf0;
v08_e1 |= 0x0d;
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x64 = 0x%02x\n", s, v08_64);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x64, v08_64);
early_write_config_dword(hose, busno, busno,
pci_devfn, 0xb0, v32_b0);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0xe1, v08_e1);
#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
{
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x64,
&v08_64);
early_read_config_dword(hose, busno, busno,
pci_devfn, 0xb0,
&v32_b0);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0xe1,
&v08_e1);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x64 = 0x%02x\n", s, v08_64);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0xb0 = 0x%02x\n", s, v32_b0);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0xe1 = 0x%02x\n", s, v08_e1);
}
#endif
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
s);
}
if (id == 0x91301055) {
u8 v08_04;
u8 v08_09;
u8 v08_41;
u8 v08_43;
u8 v08_5c;
char *s = " sb/ide --";
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
s);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x04, &v08_04);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x09, &v08_09);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x41, &v08_41);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x43, &v08_43);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x5c, &v08_5c);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x04 = 0x%02x\n", s, v08_04);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x09 = 0x%02x\n", s, v08_09);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x41 = 0x%02x\n", s, v08_41);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x43 = 0x%02x\n", s, v08_43);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x5c = 0x%02x\n", s, v08_5c);
/* enable ide master/io */
v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
/* enable ide native mode */
v08_09 |= 0x05;
/* enable primary ide */
v08_41 |= 0x80;
/* enable secondary ide */
v08_43 |= 0x80;
/*
* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
*
* This line of code is intended to provide the user with a work
* around solution to the anomalies cited in SMSC's anomaly sheet
* entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
*
* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
*/
v08_5c |= 0x01;
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x04 = 0x%02x\n", s, v08_04);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x09 = 0x%02x\n", s, v08_09);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x41 = 0x%02x\n", s, v08_41);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x43 = 0x%02x\n", s, v08_43);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x5c = 0x%02x\n", s, v08_5c);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x5c, v08_5c);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x04, v08_04);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x09, v08_09);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x41, v08_41);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x43, v08_43);
#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
{
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x04,
&v08_04);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x09,
&v08_09);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x41,
&v08_41);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x43,
&v08_43);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x5c,
&v08_5c);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x04 = 0x%02x\n", s, v08_04);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x09 = 0x%02x\n", s, v08_09);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x41 = 0x%02x\n", s, v08_41);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x43 = 0x%02x\n", s, v08_43);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x5c = 0x%02x\n", s, v08_5c);
}
#endif
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
s);
}
}
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
"+\n");
return (busno);
}
extern struct resource pci_io_resource;
extern struct resource pci_mem_resource;
void tx4927_pci_setup(void)
{
static int called = 0;
extern unsigned int tx4927_get_mem_size(void);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
#ifndef TX4927_SUPPORT_PCI_66
if (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66)
printk("PCI 66 current unsupported\n");
#endif
mips_memory_upper = tx4927_get_mem_size() << 20;
mips_memory_upper += KSEG0;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=mips_memory_upper\n",
mips_memory_upper);
mips_pci_io_base = TX4927_PCIIO;
mips_pci_io_size = TX4927_PCIIO_SIZE;
mips_pci_mem_base = TX4927_PCIMEM;
mips_pci_mem_size = TX4927_PCIMEM_SIZE;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=mips_pci_io_base\n",
mips_pci_io_base);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=mips_pci_io_size\n",
mips_pci_io_size);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=mips_pci_mem_base\n",
mips_pci_mem_base);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=mips_pci_mem_size\n",
mips_pci_mem_size);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=pci_io_resource.start\n",
pci_io_resource.start);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=pci_io_resource.end\n",
pci_io_resource.end);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=pci_mem_resource.start\n",
pci_mem_resource.start);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=pci_mem_resource.end\n",
pci_mem_resource.end);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"0x%08lx=mips_io_port_base",
mips_io_port_base);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"setup pci_io_resource to 0x%08lx 0x%08lx\n",
pci_io_resource.start,
pci_io_resource.end);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
"setup pci_mem_resource to 0x%08lx 0x%08lx\n",
pci_mem_resource.start,
pci_mem_resource.end);
if (!called) {
printk
("TX4927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
(unsigned short) (tx4927_pcicptr->pciid >> 16),
(unsigned short) (tx4927_pcicptr->pciid & 0xffff),
(unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
(!(tx4927_ccfgptr->
ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
"Internal");
called = 1;
}
printk("%s PCIC --%s PCICLK:",toshiba_name,
(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
int pciclk = 0;
switch ((unsigned long) tx4927_ccfgptr->
ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
case TX4927_CCFG_PCIDIVMODE_2_5:
pciclk = tx4927_cpu_clock * 2 / 5;
break;
case TX4927_CCFG_PCIDIVMODE_3:
pciclk = tx4927_cpu_clock / 3;
break;
case TX4927_CCFG_PCIDIVMODE_5:
pciclk = tx4927_cpu_clock / 5;
break;
case TX4927_CCFG_PCIDIVMODE_6:
pciclk = tx4927_cpu_clock / 6;
break;
}
printk("Internal(%dMHz)", pciclk / 1000000);
} else {
int pciclk = 0;
int pciclk_setting = *tx4927_pci_clk_ptr;
switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
case TX4927_PCI_CLK_33:
pciclk = 33333333;
break;
case TX4927_PCI_CLK_25:
pciclk = 25000000;
break;
case TX4927_PCI_CLK_66:
pciclk = 66666666;
break;
case TX4927_PCI_CLK_50:
pciclk = 50000000;
break;
}
printk("External(%dMHz)", pciclk / 1000000);
}
printk("\n");
/* GB->PCI mappings */
tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
tx4927_pcicptr->g2piogbase = mips_pci_io_base |
#ifdef __BIG_ENDIAN
TX4927_PCIC_G2PIOGBASE_ECHG
#else
TX4927_PCIC_G2PIOGBASE_BSDIS
#endif
;
tx4927_pcicptr->g2piopbase = 0;
tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
#ifdef __BIG_ENDIAN
TX4927_PCIC_G2PMnGBASE_ECHG
#else
TX4927_PCIC_G2PMnGBASE_BSDIS
#endif
;
tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
tx4927_pcicptr->g2pmmask[1] = 0;
tx4927_pcicptr->g2pmgbase[1] = 0;
tx4927_pcicptr->g2pmpbase[1] = 0;
tx4927_pcicptr->g2pmmask[2] = 0;
tx4927_pcicptr->g2pmgbase[2] = 0;
tx4927_pcicptr->g2pmpbase[2] = 0;
/* PCI->GB mappings (I/O 256B) */
tx4927_pcicptr->p2giopbase = 0; /* 256B */
#ifdef TX4927_SUPPORT_COMMAND_IO
tx4927_pcicptr->p2giogbase = 0 | TX4927_PCIC_P2GIOGBASE_TIOEN |
#ifdef __BIG_ENDIAN
TX4927_PCIC_P2GIOGBASE_TECHG
#else
TX4927_PCIC_P2GIOGBASE_TBSDIS
#endif
;
#else
tx4927_pcicptr->p2giogbase = 0;
#endif
/* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
tx4927_pcicptr->p2gm0plbase = 0;
tx4927_pcicptr->p2gm0pubase = 0;
tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
#ifdef __BIG_ENDIAN
TX4927_PCIC_P2GMnGBASE_TECHG
#else
TX4927_PCIC_P2GMnGBASE_TBSDIS
#endif
;
/* PCI->GB mappings (MEM 16MB) -not used */
tx4927_pcicptr->p2gm1plbase = 0xffffffff;
#ifdef CONFIG_TX4927BUG_WORKAROUND
/*
* TX4927-PCIC-BUG: P2GM1PUBASE must be 0
* if P2GM0PUBASE was 0.
*/
tx4927_pcicptr->p2gm1pubase = 0;
#else
tx4927_pcicptr->p2gm1pubase = 0xffffffff;
#endif
tx4927_pcicptr->p2gmgbase[1] = 0;
/* PCI->GB mappings (MEM 1MB) -not used */
tx4927_pcicptr->p2gm2pbase = 0xffffffff;
tx4927_pcicptr->p2gmgbase[2] = 0;
/* Enable Initiator Memory 0 Space, I/O Space, Config */
tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
tx4927_pcicptr->pciccfg |=
TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
/* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
tx4927_pcicptr->pcicfg1 = 0;
if (tx4927_pcic_trdyto >= 0) {
tx4927_pcicptr->g2ptocnt &= ~0xff;
tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
//printk("%s PCIC -- TRDYTO:%02lx\n",toshiba_name,
// tx4927_pcicptr->g2ptocnt & 0xff);
}
/* Clear All Local Bus Status */
tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
/* Enable All Local Bus Interrupts */
tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
/* Clear All Initiator Status */
tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
/* Enable All Initiator Interrupts */
tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
/* Clear All PCI Status Error */
tx4927_pcicptr->pcistatus =
(tx4927_pcicptr->pcistatus & 0x0000ffff) |
(TX4927_PCIC_PCISTATUS_ALL << 16);
/* Enable All PCI Status Error Interrupts */
tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
/* PCIC Int => IRC IRQ16 */
tx4927_pcicptr->pcicfg2 =
(tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
/* XXX */
} else {
/* Reset Bus Arbiter */
tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
/* Enable Bus Arbiter */
tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
}
tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY |
#ifdef TX4927_SUPPORT_COMMAND_IO
PCI_COMMAND_IO |
#endif
PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
":pci setup complete:\n");
//tx4927_dump_pcic_settings();
{
struct pci_channel *p;
int busno;
busno = 0;
for (p = mips_pci_channels; p->pci_ops != NULL; p++) {
busno = tx4927_pcibios_init(busno, p) + 1;
}
}
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
}
#endif /* CONFIG_PCI */
void toshiba_rbtx4927_restart(char *command)
{
printk(KERN_NOTICE "System Rebooting...\n");
/* enable the s/w reset register */
reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
/* wait for enable to be seen */
while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
/* do a s/w reset */
reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
/* do something passive while waiting for reset */
cli();
while (1)
asm_wait();
/* no return */
}
void toshiba_rbtx4927_halt(void)
{
printk(KERN_NOTICE "System Halted\n");
cli();
while (1) {
asm_wait();
}
/* no return */
}
void toshiba_rbtx4927_power_off(void)
{
toshiba_rbtx4927_halt();
/* no return */
}
void __init toshiba_rbtx4927_setup(void)
{
vu32 cp0_config;
printk("CPU is %s\n", toshiba_name);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
"-\n");
/* f/w leaves this on at startup */
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
":Clearing STO_ERL.\n");
clear_c0_status(ST0_ERL);
/* enable caches -- HCP5 does this, pmon does not */
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
cp0_config = read_c0_config();
cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
write_c0_config(cp0_config);
#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
{
extern void dump_cp0(char *);
dump_cp0("toshiba_rbtx4927_early_fw_fixup");
}
#endif
/* setup irq stuff */
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
":Setting up tx4927 pic.\n");
TX4927_WR(0xff1ff604, 0x00000400); /* irq trigger */
TX4927_WR(0xff1ff608, 0x00000000); /* irq trigger */
/* setup serial stuff */
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
":Setting up tx4927 sio.\n");
TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
"+\n");
mips_io_port_base = KSEG1 + TBTX4927_ISA_IO_OFFSET;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
":mips_io_port_base=0x%08lx\n",
mips_io_port_base);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
":Resource\n");
ioport_resource.start = 0;
ioport_resource.end = 0xffffffff;
iomem_resource.start = 0;
iomem_resource.end = 0xffffffff;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
":ResetRoutines\n");
_machine_restart = toshiba_rbtx4927_restart;
_machine_halt = toshiba_rbtx4927_halt;
_machine_power_off = toshiba_rbtx4927_power_off;
#ifdef CONFIG_BLK_DEV_IDEPCI
{
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":ide_ops=&std_ide_ops(modified)\n");
ide_ops = &std_ide_ops;
}
#else
{
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":ide_ops=<NOT_CONFIG>\n");
}
#endif
#ifdef CONFIG_FB
{
conswitchp = &dummy_con;
}
#endif
#ifdef CONFIG_PCI
/* PCIC */
/*
* ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
* PCIDIVMODE[12:11]'s initial value are given by S9[4:3] (ON:0, OFF:1).
* CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
* CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
* CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
* CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
* i.e. S9[3]: ON (83MHz), OFF (100MHz)
*/
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
"ccfg is %lx, DIV is %x\n",
(unsigned long) tx4927_ccfgptr->
ccfg, TX4927_CCFG_PCIDIVMODE_MASK);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
"PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
(unsigned long) tx4927_ccfgptr->
ccfg & TX4927_CCFG_PCI66,
(unsigned long) tx4927_ccfgptr->
ccfg & TX4927_CCFG_PCIMIDE,
(unsigned long) tx4927_ccfgptr->
ccfg & TX4927_CCFG_PCIXARB);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
"PCIDIVMODE is %lx\n",
(unsigned long) tx4927_ccfgptr->
ccfg & TX4927_CCFG_PCIDIVMODE_MASK);
switch ((unsigned long) tx4927_ccfgptr->
ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
case TX4927_CCFG_PCIDIVMODE_2_5:
case TX4927_CCFG_PCIDIVMODE_5:
tx4927_cpu_clock = 166000000; /* 166MHz */
break;
default:
tx4927_cpu_clock = 200000000; /* 200MHz */
}
/* CCFG */
/* enable Timeout BusError */
if (tx4927_ccfg_toeon)
tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
/* SDRAMC fixup */
#ifdef CONFIG_TX4927BUG_WORKAROUND
/*
* TX4927-BUG: INF 01-01-18/ BUG 01-01-22
* G-bus timeout error detection is incorrect
*/
if (tx4927_ccfg_toeon)
tx4927_sdramcptr->tr |= 0x02000000; /* RCD:3tck */
#endif
#ifdef TX4927_SUPPORT_PCI_66
tx4927_pci66_setup();
#endif
tx4927_pci_setup();
#endif
{
u32 id = 0;
early_read_config_dword(&mips_pci_channels[0], 0, 0, 0x90,
PCI_VENDOR_ID, &id);
if (id == 0x94601055) {
tx4927_using_backplane = 1;
printk("backplane board IS installed\n");
} else {
printk("backplane board NOT installed\n");
}
}
/* this is only done if backplane board installed, so must wait for pci */
#ifdef CONFIG_PC_KEYB
{
if (tx4927_using_backplane) {
extern struct kbd_ops std_kbd_ops;
kbd_ops = &std_kbd_ops;
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":kbd_ops=&std_kbd_ops\n");
} else {
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":kbd_ops=<NO_BACKPLANE>\n");
}
}
#else
{
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":kbd_ops=<NOT_CONFIG>\n");
}
#endif
/* this is on ISA bus behind PCI bus, so need PCI up first */
#ifdef CONFIG_TOSHIBA_FPCIB0
{
if (tx4927_using_backplane) {
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":fpcibo=yes\n");
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":smsc_fdc37m81x_init()\n");
smsc_fdc37m81x_init(0x3f0);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":smsc_fdc37m81x_config_beg()\n");
smsc_fdc37m81x_config_beg();
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":smsc_fdc37m81x_config_set(KBD)\n");
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
SMSC_FDC37M81X_KBD);
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
1);
smsc_fdc37m81x_config_end();
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":smsc_fdc37m81x_config_end()\n");
} else {
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP,
":fpcibo=not_found\n");
}
}
#else
{
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
}
#endif
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
"+\n");
}
void __init
toshiba_rbtx4927_time_init(void)
{
u32 c1;
u32 c2;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
#ifdef CONFIG_RTC_DS1742
rtc_get_time = rtc_ds1742_get_time;
rtc_set_time = rtc_ds1742_set_time;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
":rtc_ds1742_init()-\n");
rtc_ds1742_init(0xbc010000);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
":rtc_ds1742_init()+\n");
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
":Calibrate mips_counter_frequency-\n");
rtc_ds1742_wait();
/* get the count */
c1 = read_c0_count();
/* wait for the seconds to change again */
rtc_ds1742_wait();
/* get the count again */
c2 = read_c0_count();
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
":Calibrate mips_counter_frequency+\n");
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
":c1=%12u\n", c1);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
":c2=%12u\n", c2);
/* this diff is as close as we are going to get to counter ticks per sec */
mips_counter_frequency = abs(c2 - c1);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
":f1=%12u\n", mips_counter_frequency);
/* round to 1/10th of a MHz */
mips_counter_frequency /= (100 * 1000);
mips_counter_frequency *= (100 * 1000);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
":f2=%12u\n", mips_counter_frequency);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO,
":mips_counter_frequency=%uHz (%uMHz)\n",
mips_counter_frequency,
mips_counter_frequency / 1000000);
#else
mips_counter_frequency = 100000000;
#endif
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
}
void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
{
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
"-\n");
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
"+\n");
}
include/asm-mips/tx4927/toshiba_rbtx4927.h 0 → 100644
View file @ a16b2ff6
/*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H
#define __ASM_TX4927_TOSHIBA_RBTX4927_H
#include <asm/tx4927/tx4927.h>
#include <asm/tx4927/tx4927_mips.h>
#ifdef CONFIG_PCI
#include <asm/tx4927/tx4927_pci.h>
#endif
#define TOSHIBA_RBTX4927_WR08(a,b) do { TX4927_WR08(a,b); wbflush(); } while ( 0 )
#ifdef CONFIG_PCI
#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO
#else
#define TBTX4927_ISA_IO_OFFSET 0
#endif
#define RBTX4927_SW_RESET_DO 0xbc00f000
#define RBTX4927_SW_RESET_DO_SET 0x01
#define RBTX4927_SW_RESET_ENABLE 0xbc00f002
#define RBTX4927_SW_RESET_ENABLE_SET 0x01
#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
#define RBTX4927_RTL_8019_IRQ (29)
#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */
include/asm-mips/tx4927/tx4927.h 0 → 100644
View file @ a16b2ff6
/*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_TX4927_TX4927_H
#define __ASM_TX4927_TX4927_H
#include <asm/tx4927/tx4927_mips.h>
/*
This register naming came from the intergrate cpu/controoler name TX4927
followed by the device name from table 4.2.2 on page 4-3 and then followed
by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul
used is "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001".
*/
#define TX4927_SIO_0_BASE
/* TX4927 controller */
#define TX4927_BASE 0xfff1f0000
#define TX4927_BASE 0xfff1f0000
#define TX4927_LIMIT 0xfff1fffff
/* TX4927 SDRAM controller (64-bit registers) */
#define TX4927_SDRAMC_BASE 0x8000
#define TX4927_SDRAMC_SDCCR0 0x8000
#define TX4927_SDRAMC_SDCCR1 0x8008
#define TX4927_SDRAMC_SDCCR2 0x8010
#define TX4927_SDRAMC_SDCCR3 0x8018
#define TX4927_SDRAMC_SDCTR 0x8040
#define TX4927_SDRAMC_SDCMD 0x8058
#define TX4927_SDRAMC_LIMIT 0x8fff
/* TX4927 external bus controller (64-bit registers) */
#define TX4927_EBUSC_BASE 0x9000
#define TX4927_EBUSC_EBCCR0 0x9000
#define TX4927_EBUSC_EBCCR1 0x9008
#define TX4927_EBUSC_EBCCR2 0x9010
#define TX4927_EBUSC_EBCCR3 0x9018
#define TX4927_EBUSC_EBCCR4 0x9020
#define TX4927_EBUSC_EBCCR5 0x9028
#define TX4927_EBUSC_EBCCR6 0x9030
#define TX4927_EBUSC_EBCCR7 0x9008
#define TX4927_EBUSC_LIMIT 0x9fff
/* TX4927 SDRRAM Error Check Correction (64-bit registers) */
#define TX4927_ECC_BASE 0xa000
#define TX4927_ECC_ECCCR 0xa000
#define TX4927_ECC_ECCSR 0xa008
#define TX4927_ECC_LIMIT 0xafff
/* TX4927 DMA Controller (64-bit registers) */
#define TX4927_DMAC_BASE 0xb000
#define TX4927_DMAC_TBD 0xb000
#define TX4927_DMAC_LIMIT 0xbfff
/* TX4927 PCI Controller (32-bit registers) */
#define TX4927_PCIC_BASE 0xd000
#define TX4927_PCIC_TBD 0xb000
#define TX4927_PCIC_LIMIT 0xdfff
/* TX4927 Configuration registers (64-bit registers) */
#define TX4927_CONFIG_BASE 0xe300
#define TX4927_CONFIG_CCFG 0xe300
#define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42
#define TX4927_CONFIG_CCFG_WDRST BM_41_41
#define TX4927_CONFIG_CCFG_WDREXEN BM_40_40
#define TX4927_CONFIG_CCFG_BCFG BM_39_32
#define TX4927_CONFIG_CCFG_RESERVED_27_31 BM_31_27
#define TX4927_CONFIG_CCFG_GTOT BM_26_25
#define TX4927_CONFIG_CCFG_GTOT_4096 BM_26_25
#define TX4927_CONFIG_CCFG_GTOT_2048 BM_26_26
#define TX4927_CONFIG_CCFG_GTOT_1024 BM_25_25
#define TX4927_CONFIG_CCFG_GTOT_0512 (~BM_26_25)
#define TX4927_CONFIG_CCFG_TINTDIS BM_24_24
#define TX4927_CONFIG_CCFG_PCI66 BM_23_23
#define TX4927_CONFIG_CCFG_PCIMODE BM_22_22
#define TX4927_CONFIG_CCFG_RESERVED_20_21 BM_21_20
#define TX4927_CONFIG_CCFG_DIVMODE BM_19_17
#define TX4927_CONFIG_CCFG_DIVMODE_2_0 BM_19_19
#define TX4927_CONFIG_CCFG_DIVMODE_3_0 (BM_19_19|BM_17_17)
#define TX4927_CONFIG_CCFG_DIVMODE_4_0 BM_19_18
#define TX4927_CONFIG_CCFG_DIVMODE_2_5 BM_19_17
#define TX4927_CONFIG_CCFG_DIVMODE_8_0 (~BM_19_17)
#define TX4927_CONFIG_CCFG_DIVMODE_12_0 BM_17_17
#define TX4927_CONFIG_CCFG_DIVMODE_16_0 BM_18_18
#define TX4927_CONFIG_CCFG_DIVMODE_10_0 BM_18_17
#define TX4927_CONFIG_CCFG_BEOW BM_16_16
#define TX4927_CONFIG_CCFG_WR BM_15_15
#define TX4927_CONFIG_CCFG_TOE BM_14_14
#define TX4927_CONFIG_CCFG_PCIARB BM_13_13
#define TX4927_CONFIG_CCFG_PCIDIVMODE BM_12_11
#define TX4927_CONFIG_CCFG_RESERVED_08_10 BM_10_08
#define TX4927_CONFIG_CCFG_SYSSP BM_07_06
#define TX4927_CONFIG_CCFG_RESERVED_03_05 BM_05_03
#define TX4927_CONFIG_CCFG_ENDIAN BM_02_02
#define TX4927_CONFIG_CCFG_ARMODE BM_01_01
#define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00
#define TX4927_CONFIG_REVID 0xe308
#define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63
#define TX4927_CONFIG_REVID_PCODE BM_16_31
#define TX4927_CONFIG_REVID_MJERREV BM_12_15
#define TX4927_CONFIG_REVID_MINEREV BM_08_11
#define TX4927_CONFIG_REVID_MJREV BM_04_07
#define TX4927_CONFIG_REVID_MINREV BM_00_03
#define TX4927_CONFIG_PCFG 0xe310
#define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63
#define TX4927_CONFIG_PCFG_DRVDATA BM_56_56
#define TX4927_CONFIG_PCFG_DRVCB BM_55_55
#define TX4927_CONFIG_PCFG_DRVDQM BM_54_54
#define TX4927_CONFIG_PCFG_DRVADDR BM_53_53
#define TX4927_CONFIG_PCFG_DRVCKE BM_52_52
#define TX4927_CONFIG_PCFG_DRVRAS BM_51_51
#define TX4927_CONFIG_PCFG_DRVCAS BM_50_50
#define TX4927_CONFIG_PCFG_DRVWE BM_49_49
#define TX4927_CONFIG_PCFG_DRVCS3 BM_48_48
#define TX4927_CONFIG_PCFG_DRVCS2 BM_47_47
#define TX4927_CONFIG_PCFG_DRVCS1 BM_46_4k
#define TX4927_CONFIG_PCFG_DRVCS0 BM_45_45
#define TX4927_CONFIG_PCFG_DRVCK3 BM_44_44
#define TX4927_CONFIG_PCFG_DRVCK2 BM_43_43
#define TX4927_CONFIG_PCFG_DRVCK1 BM_42_42
#define TX4927_CONFIG_PCFG_DRVCK0 BM_41_41
#define TX4927_CONFIG_PCFG_DRVCKIN BM_40_40
#define TX4927_CONFIG_PCFG_RESERVED_33_39 BM_33_39
#define TX4927_CONFIG_PCFG_BYPASS_PLL BM_32_32
#define TX4927_CONFIG_PCFG_RESERVED_30_31 BM_30_31
#define TX4927_CONFIG_PCFG_SDCLKDLY BM_28_29
#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1 (~BM_28_29)
#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2 BM_28_28
#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3 BM_29_29
#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4 BM_28_29
#define TX4927_CONFIG_PCFG_SYSCLKEN BM_27_27
#define TX4927_CONFIG_PCFG_SDCLKEN3 BM_26_26
#define TX4927_CONFIG_PCFG_SDCLKEN2 BM_25_25
#define TX4927_CONFIG_PCFG_SDCLKEN1 BM_24_24
#define TX4927_CONFIG_PCFG_SDCLKEN0 BM_23_23
#define TX4927_CONFIG_PCFG_SDCLKINEN BM_22_22
#define TX4927_CONFIG_PCFG_PCICLKEN5 BM_21_21
#define TX4927_CONFIG_PCFG_PCICLKEN4 BM_20_20
#define TX4927_CONFIG_PCFG_PCICLKEN3 BM_19_19
#define TX4927_CONFIG_PCFG_PCICLKEN2 BM_18_18
#define TX4927_CONFIG_PCFG_PCICLKEN1 BM_17_17
#define TX4927_CONFIG_PCFG_PCICLKEN0 BM_16_16
#define TX4927_CONFIG_PCFG_RESERVED_10_15 BM_10_15
#define TX4927_CONFIG_PCFG_SEL2 BM_09_09
#define TX4927_CONFIG_PCFG_SEL1 BM_08_08
#define TX4927_CONFIG_PCFG_DMASEL3 BM_06_07
#define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3 (~BM_06_07)
#define TX4927_CONFIG_PCFG_DMASEL3_SIO0 BM_06_06
#define TX4927_CONFIG_PCFG_DMASEL3_ACLC3 BM_07_07
#define TX4927_CONFIG_PCFG_DMASEL3_ACLC1 BM_06_07
#define TX4927_CONFIG_PCFG_DMASEL2 BM_06_07
#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2 (~BM_06_07)
#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0 BM_06_06
#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10 BM_07_07
#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11 BM_06_07
#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1 (~BM_06_07)
#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0 BM_06_06
#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2 BM_07_07
#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0 BM_06_07
#define TX4927_CONFIG_PCFG_DMASEL1 BM_02_03
#define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1 (~BM_02_03)
#define TX4927_CONFIG_PCFG_DMASEL1_SIO1 BM_02_02
#define TX4927_CONFIG_PCFG_DMASEL1_ACLC1 BM_03_03
#define TX4927_CONFIG_PCFG_DMASEL1_ACLC3 BM_02_03
#define TX4927_CONFIG_PCFG_DMASEL0 BM_00_01
#define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0 (~BM_00_01)
#define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00
#define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01
#define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01
#define TX4927_CONFIG_TOEA 0xe318
#define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63
#define TX4927_CONFIG_TOEA_TOEA BM_00_35
#define TX4927_CONFIG_CLKCTR 0xe320
#define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63
#define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25
#define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24
#define TX4927_CONFIG_CLKCTR_DMACKD BM_23_23
#define TX4927_CONFIG_CLKCTR_PCICKD BM_22_22
#define TX4927_CONFIG_CLKCTR_SET_21 BM_21_21
#define TX4927_CONFIG_CLKCTR_TM0CKD BM_20_20
#define TX4927_CONFIG_CLKCTR_TM1CKD BM_19_19
#define TX4927_CONFIG_CLKCTR_TM2CKD BM_18_18
#define TX4927_CONFIG_CLKCTR_SIO0CKD BM_17_17
#define TX4927_CONFIG_CLKCTR_SIO1CKD BM_16_16
#define TX4927_CONFIG_CLKCTR_RESERVED_10_15 BM_10_15
#define TX4927_CONFIG_CLKCTR_ACLRST BM_09_09
#define TX4927_CONFIG_CLKCTR_PIORST BM_08_08
#define TX4927_CONFIG_CLKCTR_DMARST BM_07_07
#define TX4927_CONFIG_CLKCTR_PCIRST BM_06_06
#define TX4927_CONFIG_CLKCTR_RESERVED_05_05 BM_05_05
#define TX4927_CONFIG_CLKCTR_TM0RST BM_04_04
#define TX4927_CONFIG_CLKCTR_TM1RST BM_03_03
#define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02
#define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01
#define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00
#define TX4927_CONFIG_GARBC 0xe330
#define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63
#define TX4927_CONFIG_GARBC_SET_09 BM_09_09
#define TX4927_CONFIG_GARBC_ARBMD BM_08_08
#define TX4927_CONFIG_GARBC_RESERVED_06_07 BM_06_07
#define TX4927_CONFIG_GARBC_PRIORITY_H1 BM_04_05
#define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI (~BM_04_05)
#define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC BM_04_04
#define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC BM_05_05
#define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE BM_04_05
#define TX4927_CONFIG_GARBC_PRIORITY_H2 BM_02_03
#define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI (~BM_02_03)
#define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC BM_02_02
#define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC BM_03_03
#define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE BM_02_03
#define TX4927_CONFIG_GARBC_PRIORITY_H3 BM_00_01
#define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI (~BM_00_01)
#define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00
#define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01
#define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01
#define TX4927_CONFIG_RAMP 0xe348
#define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63
#define TX4927_CONFIG_RAMP_RAMP BM_00_19
#define TX4927_CONFIG_LIMIT 0xefff
/* TX4927 Timer 0 (32-bit registers) */
#define TX4927_TMR0_BASE 0xf000
#define TX4927_TMR0_TMTCR0 0xf004
#define TX4927_TMR0_TMTISR0 0xf008
#define TX4927_TMR0_TMCPRA0 0xf008
#define TX4927_TMR0_TMCPRB0 0xf00c
#define TX4927_TMR0_TMITMR0 0xf010
#define TX4927_TMR0_TMCCDR0 0xf020
#define TX4927_TMR0_TMPGMR0 0xf030
#define TX4927_TMR0_TMTRR0 0xf0f0
#define TX4927_TMR0_LIMIT 0xf0ff
/* TX4927 Timer 1 (32-bit registers) */
#define TX4927_TMR1_BASE 0xf100
#define TX4927_TMR1_TMTCR1 0xf104
#define TX4927_TMR1_TMTISR1 0xf108
#define TX4927_TMR1_TMCPRA1 0xf108
#define TX4927_TMR1_TMCPRB1 0xf10c
#define TX4927_TMR1_TMITMR1 0xf110
#define TX4927_TMR1_TMCCDR1 0xf120
#define TX4927_TMR1_TMPGMR1 0xf130
#define TX4927_TMR1_TMTRR1 0xf1f0
#define TX4927_TMR1_LIMIT 0xf1ff
/* TX4927 Timer 2 (32-bit registers) */
#define TX4927_TMR2_BASE 0xf200
#define TX4927_TMR2_TMTCR2 0xf104
#define TX4927_TMR2_TMTISR2 0xf208
#define TX4927_TMR2_TMCPRA2 0xf208
#define TX4927_TMR2_TMCPRB2 0xf20c
#define TX4927_TMR2_TMITMR2 0xf210
#define TX4927_TMR2_TMCCDR2 0xf220
#define TX4927_TMR2_TMPGMR2 0xf230
#define TX4927_TMR2_TMTRR2 0xf2f0
#define TX4927_TMR2_LIMIT 0xf2ff
/* TX4927 serial port 0 (32-bit registers) */
#define TX4927_SIO0_BASE 0xf300
#define TX4927_SIO0_SILCR0 0xf300
#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31
#define TX4927_SIO0_SILCR0_RWUB BM_15_15
#define TX4927_SIO0_SILCR0_TWUB BM_14_14
#define TX4927_SIO0_SILCR0_UODE BM_13_13
#define TX4927_SIO0_SILCR0_RESERVED_07_12 BM_07_12
#define TX4927_SIO0_SILCR0_SCS BM_05_06
#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC (~BM_05_06)
#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG BM_05_05
#define TX4927_SIO0_SILCR0_SCS_SCLK_EC BM_06_06
#define TX4927_SIO0_SILCR0_SCS_SCLK_BRG BM_05_06
#define TX4927_SIO0_SILCR0_UEPS BM_04_04
#define TX4927_SIO0_SILCR0_UPEN BM_03_03
#define TX4927_SIO0_SILCR0_USBL BM_02_02
#define TX4927_SIO0_SILCR0_UMODE BM_00_01
#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT BM_00_01
#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01)
#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01
#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01
#define TX4927_SIO0_SIDICR0 0xf304
#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31
#define TX4927_SIO0_SIDICR0_TDE BM_15_15
#define TX4927_SIO0_SIDICR0_RDE BM_14_14
#define TX4927_SIO0_SIDICR0_TIE BM_13_13
#define TX4927_SIO0_SIDICR0_RIE BM_12_12
#define TX4927_SIO0_SIDICR0_SPIE BM_11_11
#define TX4927_SIO0_SIDICR0_CTSAC BM_09_10
#define TX4927_SIO0_SIDICR0_CTSAC_NONE (~BM_09_10)
#define TX4927_SIO0_SIDICR0_CTSAC_RISE BM_09_09
#define TX4927_SIO0_SIDICR0_CTSAC_FALL BM_10_10
#define TX4927_SIO0_SIDICR0_CTSAC_BOTH BM_09_10
#define TX4927_SIO0_SIDICR0_RESERVED_06_08 BM_06_08
#define TX4927_SIO0_SIDICR0_STIE BM_00_05
#define TX4927_SIO0_SIDICR0_STIE_NONE (~BM_00_05)
#define TX4927_SIO0_SIDICR0_STIE_OERS BM_05_05
#define TX4927_SIO0_SIDICR0_STIE_CTSAC BM_04_04
#define TX4927_SIO0_SIDICR0_STIE_RBRKD BM_03_03
#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02
#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01
#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00
#define TX4927_SIO0_SIDISR0 0xf308
#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31
#define TX4927_SIO0_SIDISR0_UBRK BM_15_15
#define TX4927_SIO0_SIDISR0_UVALID BM_14_14
#define TX4927_SIO0_SIDISR0_UFER BM_13_13
#define TX4927_SIO0_SIDISR0_UPER BM_12_12
#define TX4927_SIO0_SIDISR0_UOER BM_11_11
#define TX4927_SIO0_SIDISR0_ERI BM_10_10
#define TX4927_SIO0_SIDISR0_TOUT BM_09_09
#define TX4927_SIO0_SIDISR0_TDIS BM_08_08
#define TX4927_SIO0_SIDISR0_RDIS BM_07_07
#define TX4927_SIO0_SIDISR0_STIS BM_06_06
#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05
#define TX4927_SIO0_SIDISR0_RFDN BM_00_04
#define TX4927_SIO0_SISCISR0 0xf30c
#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31
#define TX4927_SIO0_SISCISR0_OERS BM_05_05
#define TX4927_SIO0_SISCISR0_CTSS BM_04_04
#define TX4927_SIO0_SISCISR0_RBRKD BM_03_03
#define TX4927_SIO0_SISCISR0_TRDY BM_02_02
#define TX4927_SIO0_SISCISR0_TXALS BM_01_01
#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00
#define TX4927_SIO0_SIFCR0 0xf310
#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31
#define TX4927_SIO0_SIFCR0_SWRST BM_16_31
#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14
#define TX4927_SIO0_SIFCR0_RDIL BM_16_31
#define TX4927_SIO0_SIFCR0_RDIL_BYTES_1 (~BM_07_08)
#define TX4927_SIO0_SIFCR0_RDIL_BYTES_4 BM_07_07
#define TX4927_SIO0_SIFCR0_RDIL_BYTES_8 BM_08_08
#define TX4927_SIO0_SIFCR0_RDIL_BYTES_12 BM_07_08
#define TX4927_SIO0_SIFCR0_RESERVED_05_06 BM_05_06
#define TX4927_SIO0_SIFCR0_TDIL BM_03_04
#define TX4927_SIO0_SIFCR0_TDIL_BYTES_1 (~BM_03_04)
#define TX4927_SIO0_SIFCR0_TDIL_BYTES_4 BM_03_03
#define TX4927_SIO0_SIFCR0_TDIL_BYTES_8 BM_04_04
#define TX4927_SIO0_SIFCR0_TDIL_BYTES_0 BM_03_04
#define TX4927_SIO0_SIFCR0_TFRST BM_02_02
#define TX4927_SIO0_SIFCR0_RFRST BM_01_01
#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00
#define TX4927_SIO0_SIFLCR0 0xf314
#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31
#define TX4927_SIO0_SIFLCR0_RCS BM_12_12
#define TX4927_SIO0_SIFLCR0_TES BM_11_11
#define TX4927_SIO0_SIFLCR0_RESERVED_10_10 BM_10_10
#define TX4927_SIO0_SIFLCR0_RTSSC BM_09_09
#define TX4927_SIO0_SIFLCR0_RSDE BM_08_08
#define TX4927_SIO0_SIFLCR0_TSDE BM_07_07
#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06
#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04
#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00
#define TX4927_SIO0_SIBGR0 0xf318
#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31
#define TX4927_SIO0_SIBGR0_BCLK BM_08_09
#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09)
#define TX4927_SIO0_SIBGR0_BCLK_T2 BM_08_08
#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09
#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09
#define TX4927_SIO0_SIBGR0_BRD BM_00_07
#define TX4927_SIO0_SITFIF00 0xf31c
#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31
#define TX4927_SIO0_SITFIF00_TXD BM_00_07
#define TX4927_SIO0_SIRFIFO0 0xf320
#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31
#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07
#define TX4927_SIO0_SIRFIFO0 0xf320
#define TX4927_SIO0_LIMIT 0xf3ff
/* TX4927 serial port 1 (32-bit registers) */
#define TX4927_SIO1_BASE 0xf400
#define TX4927_SIO1_SILCR1 0xf400
#define TX4927_SIO1_SIDICR1 0xf404
#define TX4927_SIO1_SIDISR1 0xf408
#define TX4927_SIO1_SISCISR1 0xf40c
#define TX4927_SIO1_SIFCR1 0xf410
#define TX4927_SIO1_SIFLCR1 0xf414
#define TX4927_SIO1_SIBGR1 0xf418
#define TX4927_SIO1_SITFIF01 0xf41c
#define TX4927_SIO1_SIRFIFO1 0xf420
#define TX4927_SIO1_LIMIT 0xf4ff
/* TX4927 parallel port (32-bit registers) */
#define TX4927_PIO_BASE 0xf500
#define TX4927_PIO_PIOD0 0xf500
#define TX4927_PIO_PIODI 0xf504
#define TX4927_PIO_PIODIR 0xf508
#define TX4927_PIO_PIOOD 0xf50c
#define TX4927_PIO_LIMIT 0xf50f
/* TX4927 Interrupt Controller (32-bit registers) */
#define TX4927_IRC_BASE 0xf510
#define TX4927_IRC_IRFLAG0 0xf510
#define TX4927_IRC_IRFLAG1 0xf514
#define TX4927_IRC_IRPOL 0xf518
#define TX4927_IRC_IRRCNT 0xf51c
#define TX4927_IRC_IRMASKINT 0xf520
#define TX4927_IRC_IRMASKEXT 0xf524
#define TX4927_IRC_IRDEN 0xf600
#define TX4927_IRC_IRDM0 0xf604
#define TX4927_IRC_IRDM1 0xf608
#define TX4927_IRC_IRLVL0 0xf610
#define TX4927_IRC_IRLVL1 0xf614
#define TX4927_IRC_IRLVL2 0xf618
#define TX4927_IRC_IRLVL3 0xf61c
#define TX4927_IRC_IRLVL4 0xf620
#define TX4927_IRC_IRLVL5 0xf624
#define TX4927_IRC_IRLVL6 0xf628
#define TX4927_IRC_IRLVL7 0xf62c
#define TX4927_IRC_IRMSK 0xf640
#define TX4927_IRC_IREDC 0xf660
#define TX4927_IRC_IRPND 0xf680
#define TX4927_IRC_IRCS 0xf6a0
#define TX4927_IRC_LIMIT 0xf6ff
/* TX4927 AC-link controller (32-bit registers) */
#define TX4927_ACLC_BASE 0xf700
#define TX4927_ACLC_ACCTLEN 0xf700
#define TX4927_ACLC_ACCTLDIS 0xf704
#define TX4927_ACLC_ACREGACC 0xf708
#define TX4927_ACLC_ACINTSTS 0xf710
#define TX4927_ACLC_ACINTMSTS 0xf714
#define TX4927_ACLC_ACINTEN 0xf718
#define TX4927_ACLC_ACINTDIS 0xfR71c
#define TX4927_ACLC_ACSEMAPH 0xf720
#define TX4927_ACLC_ACGPIDAT 0xf740
#define TX4927_ACLC_ACGPODAT 0xf744
#define TX4927_ACLC_ACSLTEN 0xf748
#define TX4927_ACLC_ACSLTDIS 0xf74c
#define TX4927_ACLC_ACFIFOSTS 0xf750
#define TX4927_ACLC_ACDMASTS 0xf780
#define TX4927_ACLC_ACDMASEL 0xf784
#define TX4927_ACLC_ACAUDODAT 0xf7a0
#define TX4927_ACLC_ACSURRDAT 0xf7a4
#define TX4927_ACLC_ACCENTDAT 0xf7a8
#define TX4927_ACLC_ACLFEDAT 0xf7ac
#define TX4927_ACLC_ACAUDIDAT 0xf7b0
#define TX4927_ACLC_ACMODODAT 0xf7b8
#define TX4927_ACLC_ACMODIDAT 0xf7bc
#define TX4927_ACLC_ACREVID 0xf7fc
#define TX4927_ACLC_LIMIT 0xf7ff
#define TX4927_REG(x) ((TX4927_BASE)+(x))
#define TX4927_RD08( reg ) (*(vu08*)(reg))
#define TX4927_WR08( reg, val ) ((*(vu08*)(reg))=(val))
#define TX4927_RD16( reg ) (*(vu16*)(reg))
#define TX4927_WR16( reg, val ) ((*(vu16*)(reg))=(val))
#define TX4927_RD32( reg ) (*(vu32*)(reg))
#define TX4927_WR32( reg, val ) ((*(vu32*)(reg))=(val))
#define TX4927_RD64( reg ) (*(vu64*)(reg))
#define TX4927_WR64( reg, val ) ((*(vu64*)(reg))=(val))
#define TX4927_RD( reg ) TX4927_RD32( reg )
#define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */
#define MI8259_IRQ_ISA_RAW_END 15
#define TX4927_IRQ_CP0_RAW_BEG 0 /* tx4927 cpu built-in cp0 */
#define TX4927_IRQ_CP0_RAW_END 7
#define TX4927_IRQ_PIC_RAW_BEG 0 /* tx4927 cpu build-in pic */
#define TX4927_IRQ_PIC_RAW_END 31
#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */
#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */
#define TX4927_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG) /* 16 */
#define TX4927_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END) /* 23 */
#define TX4927_IRQ_PIC_BEG ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG) /* 24 */
#define TX4927_IRQ_PIC_END ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END) /* 55 */
#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1)
#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2)
#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7)
#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3)
#endif /* __ASM_TX4927_TX4927_H */
include/asm-mips/tx4927/tx4927_mips.h 0 → 100644
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include/asm-mips/tx4927/tx4927_pci.h 0 → 100644
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000-2001 Toshiba Corporation
*/
#ifndef __ASM_TX4927_TX4927_PCI_H
#define __ASM_TX4927_TX4927_PCI_H
#define TX4927_CCFG_TOE 0x00004000
#define TX4927_PCIMEM 0x08000000
#define TX4927_PCIMEM_SIZE 0x08000000
#define TX4927_PCIIO 0x16000000
#define TX4927_PCIIO_SIZE 0x01000000
#define TX4927_SDRAMC_REG 0xff1f8000
#define TX4927_EBUSC_REG 0xff1f9000
#define TX4927_PCIC_REG 0xff1fd000
#define TX4927_CCFG_REG 0xff1fe000
#define TX4927_IRC_REG 0xff1ff600
#define TX4927_CE3 0x17f00000 /* 1M */
#define TX4927_PCIRESET_ADDR 0x1c00f006
#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
#define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
#define tx4927_imstat_ptr(n) \
((volatile unsigned char *)TX4927_IMSTAT_ADDR(n))
/* bits for ISTAT3/IMASK3/IMSTAT3 */
#define TX4927_INT3B_PCID 0
#define TX4927_INT3B_PCIC 1
#define TX4927_INT3B_PCIB 2
#define TX4927_INT3B_PCIA 3
#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
/* bits for PCI_CLK (S6) */
#define TX4927_PCI_CLK_HOST 0x80
#define TX4927_PCI_CLK_MASK (0x0f << 3)
#define TX4927_PCI_CLK_33 (0x01 << 3)
#define TX4927_PCI_CLK_25 (0x04 << 3)
#define TX4927_PCI_CLK_66 (0x09 << 3)
#define TX4927_PCI_CLK_50 (0x0c << 3)
#define TX4927_PCI_CLK_ACK 0x04
#define TX4927_PCI_CLK_ACE 0x02
#define TX4927_PCI_CLK_ENDIAN 0x01
#define TX4927_NR_IRQ_LOCAL (8+16)
#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
#define TX4927_IR_PCIC 16
#define TX4927_IR_PCIERR 22
#define TX4927_IR_PCIPMA 23
#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
#ifdef _LANGUAGE_ASSEMBLY
#define _CONST64(c) c
#else
#define _CONST64(c) c##ull
#include <asm/byteorder.h>
#define tx4927_pcireset_ptr \
((volatile unsigned char *)TX4927_PCIRESET_ADDR)
#define tx4927_pci_clk_ptr \
((volatile unsigned char *)TX4927_PCI_CLK_ADDR)
struct tx4927_sdramc_reg {
volatile unsigned long long cr[4];
volatile unsigned long long unused0[4];
volatile unsigned long long tr;
volatile unsigned long long unused1[2];
volatile unsigned long long cmd;
};
struct tx4927_ebusc_reg {
volatile unsigned long long cr[8];
};
struct tx4927_ccfg_reg {
volatile unsigned long long ccfg;
volatile unsigned long long crir;
volatile unsigned long long pcfg;
volatile unsigned long long tear;
volatile unsigned long long clkctr;
volatile unsigned long long unused0;
volatile unsigned long long garbc;
volatile unsigned long long unused1;
volatile unsigned long long unused2;
volatile unsigned long long ramp;
};
struct tx4927_irc_reg {
volatile unsigned long cer;
volatile unsigned long cr[2];
volatile unsigned long unused0;
volatile unsigned long ilr[8];
volatile unsigned long unused1[4];
volatile unsigned long imr;
volatile unsigned long unused2[7];
volatile unsigned long scr;
volatile unsigned long unused3[7];
volatile unsigned long ssr;
volatile unsigned long unused4[7];
volatile unsigned long csr;
};
struct tx4927_pcic_reg {
volatile unsigned long pciid;
volatile unsigned long pcistatus;
volatile unsigned long pciccrev;
volatile unsigned long pcicfg1;
volatile unsigned long p2gm0plbase; /* +10 */
volatile unsigned long p2gm0pubase;
volatile unsigned long p2gm1plbase;
volatile unsigned long p2gm1pubase;
volatile unsigned long p2gm2pbase; /* +20 */
volatile unsigned long p2giopbase;
volatile unsigned long unused0;
volatile unsigned long pcisid;
volatile unsigned long unused1; /* +30 */
volatile unsigned long pcicapptr;
volatile unsigned long unused2;
volatile unsigned long pcicfg2;
volatile unsigned long g2ptocnt; /* +40 */
volatile unsigned long unused3[15];
volatile unsigned long g2pstatus; /* +80 */
volatile unsigned long g2pmask;
volatile unsigned long pcisstatus;
volatile unsigned long pcimask;
volatile unsigned long p2gcfg; /* +90 */
volatile unsigned long p2gstatus;
volatile unsigned long p2gmask;
volatile unsigned long p2gccmd;
volatile unsigned long unused4[24]; /* +a0 */
volatile unsigned long pbareqport; /* +100 */
volatile unsigned long pbacfg;
volatile unsigned long pbastatus;
volatile unsigned long pbamask;
volatile unsigned long pbabm; /* +110 */
volatile unsigned long pbacreq;
volatile unsigned long pbacgnt;
volatile unsigned long pbacstate;
volatile unsigned long long g2pmgbase[3]; /* +120 */
volatile unsigned long long g2piogbase;
volatile unsigned long g2pmmask[3]; /* +140 */
volatile unsigned long g2piomask;
volatile unsigned long long g2pmpbase[3]; /* +150 */
volatile unsigned long long g2piopbase;
volatile unsigned long pciccfg; /* +170 */
volatile unsigned long pcicstatus;
volatile unsigned long pcicmask;
volatile unsigned long unused5;
volatile unsigned long long p2gmgbase[3]; /* +180 */
volatile unsigned long long p2giogbase;
volatile unsigned long g2pcfgadrs; /* +1a0 */
volatile unsigned long g2pcfgdata;
volatile unsigned long unused6[8];
volatile unsigned long g2pintack;
volatile unsigned long g2pspc;
volatile unsigned long unused7[12]; /* +1d0 */
volatile unsigned long long pdmca; /* +200 */
volatile unsigned long long pdmga;
volatile unsigned long long pdmpa;
volatile unsigned long long pdmcut;
volatile unsigned long long pdmcnt; /* +220 */
volatile unsigned long long pdmsts;
volatile unsigned long long unused8[2];
volatile unsigned long long pdmdb[4]; /* +240 */
volatile unsigned long long pdmtdh; /* +260 */
volatile unsigned long long pdmdms;
};
#endif /* _LANGUAGE_ASSEMBLY */
/* IRCSR : Int. Current Status */
#define TX4927_IRCSR_IF 0x00010000
#define TX4927_IRCSR_ILV_MASK 0x00000700
#define TX4927_IRCSR_IVL_MASK 0x0000001f
/*
* PCIC
*/
/* bits for G2PSTATUS/G2PMASK */
#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
/* bits for PBACFG */
#define TX4927_PCIC_PBACFG_RPBA 0x00000004
#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
/* bits for G2PMnGBASE */
#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
/* bits for G2PIOGBASE */
#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
/* bits for PCICSTATUS/PCICMASK */
#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
/* bits for PCICCFG */
#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
#define TX4927_PCIC_PCICCFG_HRST 0x00000800
#define TX4927_PCIC_PCICCFG_SRST 0x00000400
#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
#define TX4927_PCIC_PCICCFG_IISE 0x00000020
#define TX4927_PCIC_PCICCFG_ATR 0x00000010
#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
/* bits for P2GMnGBASE */
#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
/* bits for P2GIOGBASE */
#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
/*
* CCFG
*/
/* CCFG : Chip Configuration */
#define TX4927_CCFG_PCI66 0x00800000
#define TX4927_CCFG_PCIMIDE 0x00400000
#define TX4927_CCFG_PCIXARB 0x00002000
#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
/* PCFG : Pin Configuration */
#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
/* CLKCTR : Clock Control */
#define TX4927_CLKCTR_PCICKD 0x00400000
#define TX4927_CLKCTR_PCIRST 0x00000040
#ifndef _LANGUAGE_ASSEMBLY
#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
#define tx4927_ircptr ((struct tx4927_irc_reg *)TX4927_IRC_REG)
#endif /* _LANGUAGE_ASSEMBLY */
#endif /* __ASM_TX4927_TX4927_PCI_H */
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