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Commit a1b53446 authored by Michael Ellerman's avatar Michael Ellerman
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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into next 

Freescale updates from Scott:

"Highlights include 8xx optimizations, 32-bit checksum optimizations,
86xx consolidation, e5500/e6500 cpu hotplug, more fman and other dt
bits, and minor fixes/cleanup."
parents d8c0282f fba4e9f9
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Documentation/devicetree/bindings/powerpc/fsl/fman.txt
View file @ a1b53446
......@@ -315,6 +315,16 @@ PROPERTIES
Value type: <phandle>
Definition: A phandle for 1EEE1588 timer.
- pcsphy-handle
Usage required for "fsl,fman-memac" MACs
Value type: <phandle>
Definition: A phandle for pcsphy.
- tbi-handle
Usage required for "fsl,fman-dtsec" MACs
Value type: <phandle>
Definition: A phandle for tbiphy.
EXAMPLE
fman1_tx28: port@a8000 {
......@@ -340,6 +350,7 @@ ethernet@e0000 {
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
ptp-timer = <&ptp-timer>;
tbi-handle = <&tbi0>;
};
============================================================================
......@@ -415,6 +426,13 @@ PROPERTIES
The settings and programming routines for internal/external
MDIO are different. Must be included for internal MDIO.
For internal PHY device on internal mdio bus, a PHY node should be created.
See the definition of the PHY node in booting-without-of.txt for an
example of how to define a PHY (Internal PHY has no interrupt line).
- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
PCS PHY addr must be '0'.
EXAMPLE
Example for FMan v2 external MDIO:
......@@ -425,12 +443,29 @@ mdio@f1000 {
interrupts = <101 2 0 0>;
};
Example for FMan v2 internal MDIO:
mdio@e3120 {
compatible = "fsl,fman-mdio";
reg = <0xe3120 0xee0>;
fsl,fman-internal-mdio;
tbi1: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
Example for FMan v3 internal MDIO:
mdio@f1000 {
compatible = "fsl,fman-memac-mdio";
reg = <0xf1000 0x1000>;
fsl,fman-internal-mdio;
pcsphy6: ethernet-phy@0 {
reg = <0x0>;
};
};
=============================================================================
......@@ -568,6 +603,7 @@ fman@400000 {
cell-index = <0>;
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
tbi-handle = <&tbi5>;
};
ethernet@e2000 {
......@@ -575,6 +611,7 @@ fman@400000 {
cell-index = <1>;
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
tbi-handle = <&tbi6>;
};
ethernet@e4000 {
......@@ -582,6 +619,7 @@ fman@400000 {
cell-index = <2>;
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
tbi-handle = <&tbi7>;
};
ethernet@e6000 {
......@@ -589,6 +627,7 @@ fman@400000 {
cell-index = <3>;
reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
tbi-handle = <&tbi8>;
};
ethernet@e8000 {
......@@ -596,6 +635,7 @@ fman@400000 {
cell-index = <4>;
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
tbi-handle = <&tbi9>;
ethernet@f0000 {
cell-index = <8>;
......
Documentation/devicetree/bindings/soc/fsl/rcpm.txt 0 → 100644
View file @ a1b53446
* Run Control and Power Management
-------------------------------------------
The RCPM performs all device-level tasks associated with device run control
and power management.
Required properites:
- reg : Offset and length of the register set of the RCPM block.
- fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
fsl,rcpm-wakeup property.
- compatible : Must contain a chip-specific RCPM block compatible string
and (if applicable) may contain a chassis-version RCPM compatible
string. Chip-specific strings are of the form "fsl,<chip>-rcpm",
such as:
* "fsl,p2041-rcpm"
* "fsl,p5020-rcpm"
* "fsl,t4240-rcpm"
Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>",
such as:
* "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
* "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
* "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version Example Chips
--------------- -------------------------------
1.0 p4080, p5020, p5040, p2041, p3041
2.0 t4240, b4860, b4420
2.1 t1040, ls1021
Example:
The RCPM node for T4240:
rcpm: global-utilities@e2000 {
compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
reg = <0xe2000 0x1000>;
fsl,#rcpm-wakeup-cells = <2>;
};
* Freescale RCPM Wakeup Source Device Tree Bindings
-------------------------------------------
Required fsl,rcpm-wakeup property should be added to a device node if the device
can be used as a wakeup source.
- fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR
register cells. The number of IPPDEXPCR register cells is defined in
"fsl,#rcpm-wakeup-cells" in the rcpm node. The first register cell is
the bit mask that should be set in IPPDEXPCR0, and the second register
cell is for IPPDEXPCR1, and so on.
Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a
mechanism for keeping certain blocks awake during STANDBY and MEM, in
order to use them as wake-up sources.
Example:
lpuart0: serial@2950000 {
compatible = "fsl,ls1021a-lpuart";
reg = <0x0 0x2950000 0x0 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
clock-names = "ipg";
fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>;
};
Documentation/kernel-parameters.txt
View file @ a1b53446
......@@ -2582,7 +2582,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
nolapic_timer [X86-32,APIC] Do not use the local APIC timer.
noltlbs [PPC] Do not use large page/tlb entries for kernel
lowmem mapping on PPC40x.
lowmem mapping on PPC40x and PPC8xx
nomca [IA-64] Disable machine check abort handling
......
arch/powerpc/Kconfig
View file @ a1b53446
......@@ -408,7 +408,7 @@ config SWIOTLB
config HOTPLUG_CPU
bool "Support for enabling/disabling CPUs"
depends on SMP && (PPC_PSERIES || \
PPC_PMAC || PPC_POWERNV || (PPC_85xx && !PPC_E500MC))
PPC_PMAC || PPC_POWERNV || FSL_SOC_BOOKE)
---help---
Say Y here to be able to disable and re-enable individual
CPUs at runtime on SMP machines.
......
arch/powerpc/Makefile
View file @ a1b53446
......@@ -325,6 +325,16 @@ corenet64_smp_defconfig:
$(call merge_into_defconfig,corenet_basic_defconfig,\
85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw)
PHONY += mpc86xx_defconfig
mpc86xx_defconfig:
$(call merge_into_defconfig,mpc86xx_basic_defconfig,\
86xx-hw fsl-emb-nonhw)
PHONY += mpc86xx_smp_defconfig
mpc86xx_smp_defconfig:
$(call merge_into_defconfig,mpc86xx_basic_defconfig,\
86xx-smp 86xx-hw fsl-emb-nonhw)
define archhelp
@echo '* zImage - Build default images selected by kernel config'
@echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
......
arch/powerpc/boot/dts/fsl/b4860qds.dts
View file @ a1b53446
/*
* B4860DS Device Tree Source
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -39,12 +39,69 @@ / {
model = "fsl,B4860QDS";
compatible = "fsl,B4860QDS";
aliases {
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xaui_slot1 = &phy_xaui_slot1;
phy_xaui_slot2 = &phy_xaui_slot2;
};
ifc: localbus@ffe124000 {
board-control@3,0 {
compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
};
};
soc@ffe000000 {
fman@400000 {
ethernet@e8000 {
phy-handle = <&phy_sgmii_1e>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&phy_sgmii_1f>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xaui_slot1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&phy_xaui_slot2>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
status = "disabled";
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
status = "disabled";
};
};
mdio@fd000 {
phy_xaui_slot1: xaui-phy@slot1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x7>;
status = "disabled";
};
phy_xaui_slot2: xaui-phy@slot2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x6>;
status = "disabled";
};
};
};
};
rio: rapidio@ffe0c0000 {
reg = <0xf 0xfe0c0000 0 0x11000>;
......@@ -55,7 +112,6 @@ port2 {
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
};
};
};
/include/ "b4860si-post.dtsi"
arch/powerpc/boot/dts/fsl/b4qds.dtsi
View file @ a1b53446
/*
* B4420DS Device Tree Source
*
* Copyright 2012 - 2014 Freescale Semiconductor, Inc.
* Copyright 2012 - 2015 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -39,6 +39,13 @@ / {
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
phy_sgmii_10 = &phy_sgmii_10;
phy_sgmii_11 = &phy_sgmii_11;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
};
ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
......@@ -135,7 +142,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25wf040";
compatible = "sst,sst25wf040", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
};
......@@ -210,6 +217,47 @@ usb@210000 {
phy_type = "ulpi";
};
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_10>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_11>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_1c>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_sgmii_1d>;
phy-connection-type = "sgmii";
};
mdio@fc000 {
phy_sgmii_10: ethernet-phy@10 {
reg = <0x10>;
};
phy_sgmii_11: ethernet-phy@11 {
reg = <0x11>;
};
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
status = "disabled";
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
status = "disabled";
};
};
};
};
pci0: pcie@ffe200000 {
......@@ -226,7 +274,6 @@ pcie@0 {
0 0x00010000>;
};
};
};
/include/ "b4si-post.dtsi"
arch/powerpc/boot/dts/fsl/bsc9131rdb.dtsi
View file @ a1b53446
......@@ -53,7 +53,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
......
arch/powerpc/boot/dts/fsl/bsc9132qds.dtsi
View file @ a1b53446
......@@ -55,7 +55,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <30000000>;
};
......
arch/powerpc/boot/dts/fsl/c293pcie.dts
View file @ a1b53446
......@@ -167,7 +167,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
......
arch/powerpc/boot/dts/gef_ppc9a.dts → arch/powerpc/boot/dts/fsl/gef_ppc9a.dts
View file @ a1b53446
......@@ -18,62 +18,19 @@
* Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
*/
/dts-v1/;
/include/ "mpc8641si-pre.dtsi"
/ {
model = "GEF_PPC9A";
compatible = "gef,ppc9a";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot
};
localbus@fef05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
lbc: localbus@fef05000 {
reg = <0xfef05000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xe8000000 0x08000000 // Paged Flash 0
......@@ -150,9 +107,7 @@ gef_pic: pic@4,4000 {
interrupt-controller;
compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
reg = <0x4 0x4000 0x20>;
interrupts = <0x8
0x9>;
interrupt-parent = <&mpic>;
interrupts = <0x8 0x9 0 0>;
};
gef_gpio: gpio@7,14000 {
......@@ -163,37 +118,10 @@ gef_gpio: gpio@7,14000 {
};
};
soc@fef00000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "fsl,mpc8641-soc", "simple-bus";
soc: soc@fef00000 {
ranges = <0x0 0xfef00000 0x00100000>;
bus-frequency = <33333333>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c1: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
i2c@3000 {
hwmon@48 {
compatible = "national,lm92";
reg = <0x48>;
......@@ -215,204 +143,65 @@ eti@6b {
};
};
i2c2: i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
};
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
mdio@24520 {
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet1: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
mdio@26520 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <0x1c 0x2>;
interrupt-parent = <&mpic>;
enet2: ethernet@25000 {
status = "disabled";
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
mdio@25520 {
status = "disabled";
};
msi@41600 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
enet3: ethernet@27000 {
status = "disabled";
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
mdio@27520 {
status = "disabled";
};
};
pci0: pcie@fef08000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef08000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <0x18 0x2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000
0x0 0x40000000
......@@ -423,3 +212,5 @@ pcie@0 {
};
};
};
/include/ "mpc8641si-post.dtsi"
arch/powerpc/boot/dts/gef_sbc310.dts → arch/powerpc/boot/dts/fsl/gef_sbc310.dts
View file @ a1b53446
......@@ -18,63 +18,23 @@
* Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
*/
/dts-v1/;
/include/ "mpc8641si-pre.dtsi"
/ {
model = "GEF_SBC310";
compatible = "gef,sbc310";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot
};
localbus@fef05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
lbc: localbus@fef05000 {
reg = <0xfef05000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xe0000000 0x08000000 // Paged Flash 0
......@@ -148,9 +108,7 @@ gef_pic: pic@4,4000 {
interrupt-controller;
compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
reg = <0x4 0x4000 0x20>;
interrupts = <0x8
0x9>;
interrupt-parent = <&mpic>;
interrupts = <0x8 0x9 0 0>;
};
gef_gpio: gpio@4,8000 {
......@@ -161,52 +119,17 @@ gef_gpio: gpio@4,8000 {
};
};
soc@fef00000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "fsl,mpc8641-soc", "simple-bus";
soc: soc@fef00000 {
ranges = <0x0 0xfef00000 0x00100000>;
bus-frequency = <33333333>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c1: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
i2c@3000 {
rtc@51 {
compatible = "epson,rx8581";
reg = <0x00000051>;
};
};
i2c2: i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
i2c@3100 {
hwmon@48 {
compatible = "national,lm92";
reg = <0x48>;
......@@ -223,181 +146,63 @@ eti@6b {
};
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
};
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
mdio@24520 {
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet1: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
mdio@26520 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <0x1c 0x2>;
interrupt-parent = <&mpic>;
enet2: ethernet@25000 {
status = "disabled";
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
mdio@25520 {
status = "disabled";
};
msi@41600 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
enet3: ethernet@27000 {
status = "disabled";
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
mdio@27520 {
status = "disabled";
};
};
pci0: pcie@fef08000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef08000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <0x18 0x2>;
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
......@@ -407,10 +212,6 @@ pci0: pcie@fef08000 {
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000
0x0 0x40000000
......@@ -424,16 +225,14 @@ pcie@0 {
pci1: pcie@fef09000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef09000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <0x19 0x2>;
clock-frequency = <100000000>;
interrupts = <0x19 0x2 0 0>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
......@@ -457,3 +256,5 @@ pcie@0 {
};
};
};
/include/ "mpc8641si-post.dtsi"
arch/powerpc/boot/dts/gef_sbc610.dts → arch/powerpc/boot/dts/fsl/gef_sbc610.dts
View file @ a1b53446
......@@ -18,62 +18,19 @@
* Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
*/
/dts-v1/;
/include/ "mpc8641si-pre.dtsi"
/ {
model = "GEF_SBC610";
compatible = "gef,sbc610";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot
};
localbus@fef05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
lbc: localbus@fef05000 {
reg = <0xfef05000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xe8000000 0x08000000 // Paged Flash 0
......@@ -148,9 +105,7 @@ gef_pic: pic@4,4000 {
interrupt-controller;
compatible = "gef,fpga-pic";
reg = <0x4 0x4000 0x20>;
interrupts = <0x8
0x9>;
interrupt-parent = <&mpic>;
interrupts = <0x8 0x9 0 0>;
};
gef_gpio: gpio@7,14000 {
......@@ -161,37 +116,10 @@ gef_gpio: gpio@7,14000 {
};
};
soc@fef00000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "simple-bus";
soc: soc@fef00000 {
ranges = <0x0 0xfef00000 0x00100000>;
bus-frequency = <33333333>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c1: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
i2c@3000 {
hwmon@48 {
compatible = "national,lm92";
reg = <0x48>;
......@@ -213,204 +141,65 @@ eti@6b {
};
};
i2c2: i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
};
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
mdio@24520 {
phy0: ethernet-phy@0 {
interrupt-parent = <&gef_pic>;
interrupts = <0x9 0x4>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&gef_pic>;
interrupts = <0x8 0x4>;
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet1: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "gmii";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
mdio@26520 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <0x1c 0x2>;
interrupt-parent = <&mpic>;
enet2: ethernet@25000 {
status = "disabled";
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
mdio@25520 {
status = "disabled";
};
msi@41600 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
enet3: ethernet@27000 {
status = "disabled";
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
mdio@27520 {
status = "disabled";
};
};
pci0: pcie@fef08000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef08000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <0x18 0x2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000
0x0 0x40000000
......@@ -421,3 +210,5 @@ pcie@0 {
};
};
};
/include/ "mpc8641si-post.dtsi"
arch/powerpc/boot/dts/fsl/kmcoge4.dts
View file @ a1b53446
......@@ -63,7 +63,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl256s1";
compatible = "spansion,s25fl256s1", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>; /* input clock */
};
......@@ -77,7 +77,7 @@ network_clock@1 {
flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,m25p32";
compatible = "micron,m25p32", "jedec,spi-nor";
reg = <2>;
spi-max-frequency = <15000000>;
};
......
arch/powerpc/boot/dts/fsl/mpc8536ds.dtsi
View file @ a1b53446
......@@ -142,7 +142,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
partition@u-boot {
......@@ -166,17 +166,17 @@ partition@fs {
};
};
flash@1 {
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <40000000>;
};
flash@2 {
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <2>;
spi-max-frequency = <40000000>;
};
flash@3 {
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <3>;
spi-max-frequency = <40000000>;
};
......
arch/powerpc/boot/dts/fsl/mpc8641si-post.dtsi 0 → 100644
View file @ a1b53446
/*
* MPC8641 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
&lbc {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
interrupts = <19 2 0 0>;
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8641-soc", "simple-bus";
bus-frequency = <0>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2 0 0>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-duart-0.dtsi"
serial@4600 {
interrupts = <28 2 0 0>;
};
/include/ "pq3-dma-0.dtsi"
dma@21300 {
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
};
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
};
/include/ "pq3-etsec1-0.dtsi"
ethernet@24000 {
model = "TSEC";
};
/include/ "pq3-etsec1-1.dtsi"
ethernet@25000 {
model = "TSEC";
};
/include/ "pq3-etsec1-2.dtsi"
ethernet@26000 {
model = "TSEC";
};
/include/ "pq3-etsec1-3.dtsi"
ethernet@27000 {
model = "TSEC";
};
/include/ "qoriq-mpic.dtsi"
msi@41600 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
};
msi@41800 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
};
msi@41a00 {
compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
&pci0 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
clock-frequency = <100000000>;
interrupts = <24 2 0 0>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
};
};
arch/powerpc/boot/dts/fsl/mpc8641si-pre.dtsi 0 → 100644
View file @ a1b53446
/*
* MPC8641 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&mpic>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
};
arch/powerpc/boot/dts/fsl/mvme2500.dts
View file @ a1b53446
......@@ -70,12 +70,12 @@ spi0: spi@7000 {
fsl,espi-num-chipselects = <2>;
flash@0 {
compatible = "atmel,at25df641";
compatible = "atmel,at25df641", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
};
flash@1 {
compatible = "atmel,at25df641";
compatible = "atmel,at25df641", "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <10000000>;
};
......
arch/powerpc/boot/dts/fsl/p1010rdb.dtsi
View file @ a1b53446
......@@ -110,7 +110,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
......
arch/powerpc/boot/dts/fsl/p1020rdb-pc.dtsi
View file @ a1b53446
......@@ -151,7 +151,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p1020rdb-pd.dts
View file @ a1b53446
......@@ -155,7 +155,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
/* input clock */
spi-max-frequency = <40000000>;
......
arch/powerpc/boot/dts/fsl/p1020rdb.dtsi
View file @ a1b53446
......@@ -148,7 +148,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p1021mds.dts
View file @ a1b53446
......@@ -123,7 +123,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p1021rdb-pc.dtsi
View file @ a1b53446
......@@ -150,7 +150,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p1022ds.dtsi
View file @ a1b53446
......@@ -160,7 +160,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p1022rdk.dts
View file @ a1b53446
......@@ -86,7 +86,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80";
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <1000000>;
partition@0 {
......
arch/powerpc/boot/dts/fsl/p1024rdb.dtsi
View file @ a1b53446
......@@ -129,7 +129,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80";
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
......
arch/powerpc/boot/dts/fsl/p1025rdb.dtsi
View file @ a1b53446
......@@ -137,7 +137,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
......
arch/powerpc/boot/dts/fsl/p2020rdb-pc.dtsi
View file @ a1b53446
......@@ -151,7 +151,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80";
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
......
arch/powerpc/boot/dts/fsl/p2020rdb.dts
View file @ a1b53446
......@@ -155,7 +155,7 @@ spi@7000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
......
arch/powerpc/boot/dts/fsl/p2041rdb.dts
View file @ a1b53446
/*
* P2041RDB Device Tree Source
*
* Copyright 2011 - 2014 Freescale Semiconductor Inc.
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -41,6 +41,19 @@ / {
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_2 = &phy_sgmii_2;
phy_sgmii_3 = &phy_sgmii_3;
phy_sgmii_4 = &phy_sgmii_4;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_2 = &phy_xgmii_2;
};
memory {
device_type = "memory";
};
......@@ -83,7 +96,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@u-boot {
......@@ -137,6 +150,83 @@ eeprom@50 {
usb1: usb@211000 {
dr_mode = "host";
};
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@e1120 {
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
phy_sgmii_2: ethernet-phy@2 {
reg = <0x2>;
};
phy_sgmii_3: ethernet-phy@3 {
reg = <0x3>;
};
phy_sgmii_4: ethernet-phy@4 {
reg = <0x4>;
};
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_3>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_4>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_2>;
phy-connection-type = "xgmii";
};
mdio@f1000 {
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
};
rio: rapidio@ffe0c0000 {
......
arch/powerpc/boot/dts/fsl/p3041ds.dts
View file @ a1b53446
/*
* P3041DS Device Tree Source
*
* Copyright 2010 - 2014 Freescale Semiconductor Inc.
* Copyright 2010 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -41,6 +41,20 @@ / {
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases{
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_1 = &phy_xgmii_1;
phy_xgmii_2 = &phy_xgmii_2;
emi1_rgmii = &hydra_mdio_rgmii;
emi1_sgmii = &hydra_mdio_sgmii;
emi2_xgmii = &hydra_mdio_xgmii;
};
memory {
device_type = "memory";
};
......@@ -83,7 +97,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <35000000>; /* input clock */
partition@u-boot {
......@@ -150,6 +164,52 @@ adt7461@4c {
reg = <0x4c>;
};
};
fman@400000{
ethernet@e0000 {
phy-handle = <&phy_sgmii_1c>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_1d>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_1e>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_sgmii_1f>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_1>;
phy-connection-type = "xgmii";
};
hydra_mdio_xgmii: mdio@f1000 {
status = "disabled";
phy_xgmii_1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
};
rio: rapidio@ffe0c0000 {
......@@ -215,8 +275,58 @@ partition@1f000000 {
};
board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
ranges = <0 3 0 0x30>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_mdio_rgmii: rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_mdio_sgmii: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
};
};
......
arch/powerpc/boot/dts/fsl/p4080ds.dts
View file @ a1b53446
/*
* P4080DS Device Tree Source
*
* Copyright 2009 - 2014 Freescale Semiconductor Inc.
* Copyright 2009 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -41,6 +41,20 @@ / {
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
phy_rgmii = &phyrgmii;
phy5_slot3 = &phy5slot3;
phy6_slot3 = &phy6slot3;
phy7_slot3 = &phy7slot3;
phy8_slot3 = &phy8slot3;
emi1_slot3 = &p4080mdio2;
emi1_slot4 = &p4080mdio1;
emi1_slot5 = &p4080mdio3;
emi1_rgmii = &p4080mdio0;
emi2_slot4 = &p4080xmdio1;
emi2_slot5 = &p4080xmdio3;
};
memory {
device_type = "memory";
};
......@@ -84,7 +98,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@u-boot {
......@@ -137,6 +151,60 @@ usb1: usb@211000 {
dr_mode = "host";
phy_type = "ulpi";
};
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy1>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy2>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy3>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy10>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-handle = <&phy5>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy6>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy7>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy8>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy11>;
phy-connection-type = "xgmii";
};
};
};
rio: rapidio@ffe0c0000 {
......@@ -213,6 +281,120 @@ pcie@0 {
};
};
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-gpio", "mdio-mux";
mdio-parent-bus = <&mdio0>;
gpios = <&gpio0 1 0>, <&gpio0 0 0>;
p4080mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phyrgmii: ethernet-phy@0 {
reg = <0x0>;
};
};
p4080mdio1: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phy5: ethernet-phy@1c {
reg = <0x1c>;
};
phy6: ethernet-phy@1d {
reg = <0x1d>;
};
phy7: ethernet-phy@1e {
reg = <0x1e>;
};
phy8: ethernet-phy@1f {
reg = <0x1f>;
};
};
p4080mdio2: mdio@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
phy5slot3: ethernet-phy@1c {
reg = <0x1c>;
};
phy6slot3: ethernet-phy@1d {
reg = <0x1d>;
};
phy7slot3: ethernet-phy@1e {
reg = <0x1e>;
};
phy8slot3: ethernet-phy@1f {
reg = <0x1f>;
};
};
p4080mdio3: mdio@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
phy0: ethernet-phy@1c {
reg = <0x1c>;
};
phy1: ethernet-phy@1d {
reg = <0x1d>;
};
phy2: ethernet-phy@1e {
reg = <0x1e>;
};
phy3: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
mdio-mux-emi2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-gpio", "mdio-mux";
mdio-parent-bus = <&xmdio0>;
gpios = <&gpio0 3 0>, <&gpio0 2 0>;
p4080xmdio1: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phy11: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
p4080xmdio3: mdio@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
phy10: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
};
};
};
/include/ "p4080si-post.dtsi"
arch/powerpc/boot/dts/fsl/p5020ds.dts
View file @ a1b53446
/*
* P5020DS Device Tree Source
*
* Copyright 2010 - 2014 Freescale Semiconductor Inc.
* Copyright 2010 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -41,6 +41,20 @@ / {
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_1 = &phy_xgmii_1;
phy_xgmii_2 = &phy_xgmii_2;
emi1_rgmii = &hydra_mdio_rgmii;
emi1_sgmii = &hydra_mdio_sgmii;
emi2_xgmii = &hydra_mdio_xgmii;
};
memory {
device_type = "memory";
};
......@@ -83,7 +97,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@u-boot {
......@@ -150,6 +164,52 @@ adt7461@4c {
reg = <0x4c>;
};
};
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_1c>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_1d>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_1e>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_sgmii_1f>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_1>;
phy-connection-type = "xgmii";
};
hydra_mdio_xgmii: mdio@f1000 {
status = "disabled";
phy_xgmii_1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
};
rio: rapidio@ffe0c0000 {
......@@ -215,8 +275,58 @@ partition@1f000000 {
};
board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
ranges = <0 3 0 0x30>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_mdio_rgmii: rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_mdio_sgmii: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
};
};
......
arch/powerpc/boot/dts/fsl/p5040ds.dts
View file @ a1b53446
/*
* P5040DS Device Tree Source
*
* Copyright 2012 - 2014 Freescale Semiconductor Inc.
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -41,6 +41,32 @@ / {
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases{
phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
hydra_rg = &hydra_rg;
hydra_sg_slot2 = &hydra_sg_slot2;
hydra_sg_slot3 = &hydra_sg_slot3;
hydra_sg_slot5 = &hydra_sg_slot5;
hydra_sg_slot6 = &hydra_sg_slot6;
hydra_xg_slot1 = &hydra_xg_slot1;
hydra_xg_slot2 = &hydra_xg_slot2;
};
memory {
device_type = "memory";
};
......@@ -83,7 +109,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl12801";
compatible = "spansion,s25sl12801", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
partition@u-boot {
......@@ -147,6 +173,62 @@ adt7461@4c {
reg = <0x4c>;
};
};
fman@400000 {
ethernet@e0000 {
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_slot_2>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_slot_1>;
phy-connection-type = "xgmii";
};
};
};
lbc: localbus@ffe124000 {
......@@ -200,8 +282,158 @@ partition@1f000000 {
};
board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x40>;
ranges = <0 3 0 0x40>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_rg:rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_sg_slot2: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_slot2_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot2_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot2_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot2_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot3: sgmii-mdio@68 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x68>;
status = "disabled";
phy_sgmii_slot3_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot3_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot3_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot3_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot5: sgmii-mdio@38 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x38>;
status = "disabled";
phy_sgmii_slot5_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot5_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot5_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot5_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot6: sgmii-mdio@48 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x48>;
status = "disabled";
phy_sgmii_slot6_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot6_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot6_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot6_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
mdio-mux-emi2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&xmdio0>;
reg = <9 1>;
mux-mask = <0x06>;
hydra_xg_slot1: hydra-xg-slot1@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
phy_xgmii_slot_1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <4>;
};
};
hydra_xg_slot2: hydra-xg-slot2@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
phy_xgmii_slot_2: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
};
};
};
};
......
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
View file @ a1b53446
......@@ -420,6 +420,7 @@ crypto@300000 {
fsl,iommu-parent = <&pamu4>;
};
/include/ "qoriq-raid1.0-0.dtsi"
/include/ "qoriq-qman1.dtsi"
/include/ "qoriq-bman1.dtsi"
......
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
View file @ a1b53446
......@@ -73,6 +73,12 @@ aliases {
rtic_d = &rtic_d;
sec_mon = &sec_mon;
raideng = &raideng;
raideng_jr0 = &raideng_jr0;
raideng_jr1 = &raideng_jr1;
raideng_jr2 = &raideng_jr2;
raideng_jr3 = &raideng_jr3;
fman0 = &fman0;
fman1 = &fman1;
ethernet0 = &enet0;
......
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
View file @ a1b53446
......@@ -55,6 +55,7 @@ ethernet@e0000 {
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy0>;
};
mdio@e1000 {
......@@ -62,5 +63,9 @@ mdio@e1000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>;
pcsphy0: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
View file @ a1b53446
......@@ -52,6 +52,7 @@ ethernet@f0000 {
compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
pcsphy-handle = <&pcsphy6>;
};
mdio@f1000 {
......@@ -59,5 +60,9 @@ mdio@f1000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf1000 0x1000>;
pcsphy6: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
View file @ a1b53446
......@@ -55,6 +55,7 @@ ethernet@e2000 {
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy1>;
};
mdio@e3000 {
......@@ -62,5 +63,9 @@ mdio@e3000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>;
pcsphy1: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
View file @ a1b53446
......@@ -52,6 +52,7 @@ ethernet@f2000 {
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
pcsphy-handle = <&pcsphy7>;
};
mdio@f3000 {
......@@ -59,5 +60,9 @@ mdio@f3000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf3000 0x1000>;
pcsphy7: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@e0000 {
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy0>;
};
mdio@e1000 {
......@@ -58,5 +59,9 @@ mdio@e1000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>;
pcsphy0: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@e2000 {
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy1>;
};
mdio@e3000 {
......@@ -58,5 +59,9 @@ mdio@e3000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>;
pcsphy1: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@e4000 {
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy2>;
};
mdio@e5000 {
......@@ -58,5 +59,9 @@ mdio@e5000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe5000 0x1000>;
pcsphy2: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@e6000 {
reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy3>;
};
mdio@e7000 {
......@@ -58,5 +59,9 @@ mdio@e7000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe7000 0x1000>;
pcsphy3: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@e8000 {
reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy4>;
};
mdio@e9000 {
......@@ -58,5 +59,9 @@ mdio@e9000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe9000 0x1000>;
pcsphy4: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@ea000 {
reg = <0xea000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy5>;
};
mdio@eb000 {
......@@ -58,5 +59,9 @@ mdio@eb000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xeb000 0x1000>;
pcsphy5: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi
View file @ a1b53446
......@@ -52,6 +52,7 @@ ethernet@f0000 {
compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
pcsphy-handle = <&pcsphy14>;
};
mdio@f1000 {
......@@ -59,5 +60,9 @@ mdio@f1000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf1000 0x1000>;
pcsphy14: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi
View file @ a1b53446
......@@ -52,6 +52,7 @@ ethernet@f2000 {
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>;
pcsphy-handle = <&pcsphy15>;
};
mdio@f3000 {
......@@ -59,5 +60,9 @@ mdio@f3000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf3000 0x1000>;
pcsphy15: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@e0000 {
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy8>;
};
mdio@e1000 {
......@@ -58,5 +59,9 @@ mdio@e1000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>;
pcsphy8: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@e2000 {
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy9>;
};
mdio@e3000 {
......@@ -58,5 +59,9 @@ mdio@e3000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>;
pcsphy9: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@e4000 {
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy10>;
};
mdio@e5000 {
......@@ -58,5 +59,9 @@ mdio@e5000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe5000 0x1000>;
pcsphy10: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@e6000 {
reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy11>;
};
mdio@e7000 {
......@@ -58,5 +59,9 @@ mdio@e7000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe7000 0x1000>;
pcsphy11: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@e8000 {
reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy12>;
};
mdio@e9000 {
......@@ -58,5 +59,9 @@ mdio@e9000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe9000 0x1000>;
pcsphy12: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi
View file @ a1b53446
......@@ -51,6 +51,7 @@ ethernet@ea000 {
reg = <0xea000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy13>;
};
mdio@eb000 {
......@@ -58,5 +59,9 @@ mdio@eb000 {
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xeb000 0x1000>;
pcsphy13: ethernet-phy@0 {
reg = <0x0>;
};
};
};
arch/powerpc/boot/dts/sbc8641d.dts → arch/powerpc/boot/dts/fsl/sbc8641d.dts
View file @ a1b53446
......@@ -13,65 +13,23 @@
* option) any later version.
*/
/dts-v1/;
/include/ "mpc8641si-pre.dtsi"
/ {
model = "SBC8641D";
compatible = "wind,sbc8641";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>; // L1
i-cache-size = <32768>; // L1
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; // 512M at 0x0
};
localbus@f8005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8641-localbus", "simple-bus";
lbc: localbus@f8005000 {
reg = <0xf8005000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
1 0 0xf0000000 0x00010000 // 64KB EEPROM
......@@ -120,283 +78,81 @@ epld@2,0 {
};
};
soc@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
soc: soc@f8000000 {
ranges = <0x00000000 0xf8000000 0x00100000>;
bus-frequency = <0>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8641-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
enet0: ethernet@24000 {
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
mdio@24520 {
phy0: ethernet-phy@1f {
reg = <0x1f>;
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
phy1: ethernet-phy@0 {
reg = <0>;
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
phy2: ethernet-phy@1 {
reg = <1>;
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
phy3: ethernet-phy@2 {
reg = <2>;
};
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@1f {
reg = <0x1f>;
};
phy1: ethernet-phy@0 {
reg = <0>;
};
phy2: ethernet-phy@1 {
reg = <1>;
};
phy3: ethernet-phy@2 {
reg = <2>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
mdio@25520 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet2: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
};
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
mdio@26520 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet3: ethernet@27000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <3>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi3>;
phy-handle = <&phy3>;
phy-connection-type = "rgmii-id";
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <28 2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
mdio@27520 {
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
pci0: pcie@f8008000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf8008000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
interrupt-map-mask = <0xff00 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0x0000 0 0 1 &mpic 0 1
0x0000 0 0 2 &mpic 1 1
0x0000 0 0 3 &mpic 2 1
0x0000 0 0 4 &mpic 3 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000
0x0 0x20000000
......@@ -411,16 +167,14 @@ pcie@0 {
pci1: pcie@f8009000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf8009000 0x1000>;
bus-range = <0 0xff>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
clock-frequency = <100000000>;
interrupts = <25 2 0 0>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
......@@ -445,3 +199,5 @@ pcie@0 {
};
};
};
/include/ "mpc8641si-post.dtsi"
arch/powerpc/boot/dts/fsl/t1023rdb.dts
View file @ a1b53446
......@@ -79,7 +79,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl512s";
compatible = "spansion,s25fl512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>; /* input clk */
};
......@@ -111,6 +111,47 @@ current-sensor@41 {
shunt-resistor = <1000>;
};
};
fman@400000 {
fm1mac1: ethernet@e0000 {
phy-handle = <&sgmii_rtk_phy2>;
phy-connection-type = "sgmii";
sleep = <&rcpm 0x80000000>;
};
fm1mac2: ethernet@e2000 {
sleep = <&rcpm 0x40000000>;
};
fm1mac3: ethernet@e4000 {
phy-handle = <&sgmii_aqr_phy3>;
phy-connection-type = "sgmii-2500";
sleep = <&rcpm 0x20000000>;
};
fm1mac4: ethernet@e6000 {
phy-handle = <&rgmii_rtk_phy1>;
phy-connection-type = "rgmii";
sleep = <&rcpm 0x10000000>;
};
mdio0: mdio@fc000 {
rgmii_rtk_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sgmii_rtk_phy2: ethernet-phy@3 {
reg = <0x3>;
};
};
xmdio0: mdio@fd000 {
sgmii_aqr_phy3: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
};
};
};
pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t1024qds.dts
View file @ a1b53446
......@@ -87,7 +87,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11"; /* 16MB */
compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
reg = <0>;
spi-max-frequency = <10000000>;
};
......@@ -95,7 +95,7 @@ flash@0 {
flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25wf040"; /* 512KB */
compatible = "sst,sst25wf040", "jedec,spi-nor"; /* 512KB */
reg = <1>;
spi-max-frequency = <10000000>;
};
......@@ -103,7 +103,7 @@ flash@1 {
flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "eon,en25s64"; /* 8MB */
compatible = "eon,en25s64", "jedec,spi-nor"; /* 8MB */
reg = <2>;
spi-max-frequency = <10000000>;
};
......
arch/powerpc/boot/dts/fsl/t1024rdb.dts
View file @ a1b53446
......@@ -89,7 +89,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q512ax3";
compatible = "micron,n25q512ax3", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>; /* input clk */
};
......@@ -140,6 +140,51 @@ pca9546@77 {
#size-cells = <0>;
};
};
fman@400000 {
fm1mac1: ethernet@e0000 {
phy-handle = <&xg_aqr105_phy3>;
phy-connection-type = "xgmii";
sleep = <&rcpm 0x80000000>;
};
fm1mac2: ethernet@e2000 {
sleep = <&rcpm 0x40000000>;
};
fm1mac3: ethernet@e4000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
sleep = <&rcpm 0x20000000>;
};
fm1mac4: ethernet@e6000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
sleep = <&rcpm 0x10000000>;
};
mdio0: mdio@fc000 {
rgmii_phy1: ethernet-phy@2 {
reg = <0x2>;
};
rgmii_phy2: ethernet-phy@6 {
reg = <0x6>;
};
};
xmdio0: mdio@fd000 {
xg_aqr105_phy3: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
sg_2500_aqr105_phy4: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
};
};
};
pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t1040rdb.dts
View file @ a1b53446
/*
* T1040RDB Device Tree Source
*
* Copyright 2014 Freescale Semiconductor Inc.
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -38,6 +38,36 @@
/ {
model = "fsl,T1040RDB";
compatible = "fsl,T1040RDB";
aliases {
phy_sgmii_2 = &phy_sgmii_2;
};
soc@ffe000000 {
fman@400000 {
ethernet@e0000 {
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@fc000 {
phy_sgmii_2: ethernet-phy@03 {
reg = <0x03>;
};
};
};
};
ifc: localbus@ffe124000 {
cpld@3,0 {
compatible = "fsl,t1040rdb-cpld";
......
arch/powerpc/boot/dts/fsl/t1042rdb.dts
View file @ a1b53446
/*
* T1042RDB Device Tree Source
*
* Copyright 2014 Freescale Semiconductor Inc.
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -38,6 +38,34 @@
/ {
model = "fsl,T1042RDB";
compatible = "fsl,T1042RDB";
aliases {
phy_sgmii_2 = &phy_sgmii_2;
};
soc@ffe000000 {
fman@400000 {
ethernet@e0000 {
status = "disabled";
};
ethernet@e2000 {
status = "disabled";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@fc000 {
phy_sgmii_2: ethernet-phy@03 {
reg = <0x03>;
};
};
};
};
ifc: localbus@ffe124000 {
cpld@3,0 {
compatible = "fsl,t1042rdb-cpld";
......
arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts
View file @ a1b53446
/*
* T1042RDB_PI Device Tree Source
*
* Copyright 2014 Freescale Semiconductor Inc.
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -38,11 +38,13 @@
/ {
model = "fsl,T1042RDB_PI";
compatible = "fsl,T1042RDB_PI";
ifc: localbus@ffe124000 {
cpld@3,0 {
compatible = "fsl,t1042rdb_pi-cpld";
};
};
soc: soc@ffe000000 {
i2c@118000 {
rtc@68 {
......@@ -51,6 +53,20 @@ rtc@68 {
interrupts = <0x2 0x1 0 0>;
};
};
fman@400000 {
ethernet@e0000 {
status = "disabled";
};
ethernet@e2000 {
status = "disabled";
};
ethernet@e4000 {
status = "disabled";
};
};
};
};
......
arch/powerpc/boot/dts/fsl/t104xd4rdb.dtsi
View file @ a1b53446
......@@ -104,7 +104,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q512ax3";
compatible = "micron,n25q512ax3", "jedec,spi-nor";
reg = <0>;
/* input clock */
spi-max-frequency = <10000000>;
......
arch/powerpc/boot/dts/fsl/t104xqds.dtsi
View file @ a1b53446
/*
* T104xQDS Device Tree Source
*
* Copyright 2013 - 2014 Freescale Semiconductor Inc.
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -38,6 +38,33 @@ / {
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
emi1_rgmii0 = &t1040mdio0;
emi1_rgmii1 = &t1040mdio1;
emi1_slot3 = &t1040mdio3;
emi1_slot5 = &t1040mdio5;
emi1_slot6 = &t1040mdio6;
emi1_slot7 = &t1040mdio7;
rgmii_phy1 = &rgmii_phy1;
rgmii_phy2 = &rgmii_phy2;
phy_s3_01 = &phy_s3_01;
phy_s3_02 = &phy_s3_02;
phy_s3_03 = &phy_s3_03;
phy_s3_04 = &phy_s3_04;
phy_s5_01 = &phy_s5_01;
phy_s5_02 = &phy_s5_02;
phy_s5_03 = &phy_s5_03;
phy_s5_04 = &phy_s5_04;
phy_s6_01 = &phy_s6_01;
phy_s6_02 = &phy_s6_02;
phy_s6_03 = &phy_s6_03;
phy_s6_04 = &phy_s6_04;
phy_s7_01 = &phy_s7_01;
phy_s7_02 = &phy_s7_02;
phy_s7_03 = &phy_s7_03;
phy_s7_04 = &phy_s7_04;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
......@@ -85,6 +112,128 @@ board-control@3,0 {
#size-cells = <1>;
compatible = "fsl,fpga-qixis";
reg = <3 0 0x300>;
ranges = <0 3 0 0x300>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <0x54 1>;
mux-mask = <0xe0>;
t1040mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
status = "disabled";
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
};
t1040mdio1: mdio@20 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
status = "disabled";
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
t1040mdio3: mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
status = "disabled";
phy_s3_01: ethernet-phy@1c {
reg = <0x1c>;
};
phy_s3_02: ethernet-phy@1d {
reg = <0x1d>;
};
phy_s3_03: ethernet-phy@1e {
reg = <0x1e>;
};
phy_s3_04: ethernet-phy@1f {
reg = <0x1f>;
};
};
t1040mdio5: mdio@a0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa0>;
phy_s5_01: ethernet-phy@1c {
reg = <0x14>;
};
phy_s5_02: ethernet-phy@1d {
reg = <0x15>;
};
phy_s5_03: ethernet-phy@1e {
reg = <0x16>;
};
phy_s5_04: ethernet-phy@1f {
reg = <0x17>;
};
};
t1040mdio6: mdio@c0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc0>;
phy_s6_01: ethernet-phy@1c {
reg = <0x18>;
};
phy_s6_02: ethernet-phy@1d {
reg = <0x19>;
};
phy_s6_03: ethernet-phy@1e {
reg = <0x1a>;
};
phy_s6_04: ethernet-phy@1f {
reg = <0x1b>;
};
};
t1040mdio7: mdio@e0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe0>;
status = "disabled";
phy_s7_01: ethernet-phy@1c {
reg = <0x1c>;
};
phy_s7_02: ethernet-phy@1d {
reg = <0x1d>;
};
phy_s7_03: ethernet-phy@1e {
reg = <0x1e>;
};
phy_s7_04: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
};
};
......@@ -112,7 +261,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11";
compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
......@@ -129,6 +278,33 @@ rtc@68 {
interrupts = <0x1 0x1 0 0>;
};
};
fman@400000 {
ethernet@e0000 {
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_s7_03>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
};
};
pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
View file @ a1b53446
/*
* T1040RDB/T1042RDB Device Tree Source
*
* Copyright 2014 Freescale Semiconductor Inc.
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -33,6 +33,12 @@
*/
/ {
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_2 = &phy_sgmii_2;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
......@@ -103,10 +109,15 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q512a";
compatible = "micron,n25q512a", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
slic@3 {
compatible = "maxim,ds26522";
reg = <3>;
spi-max-frequency = <2000000>; /* input clock */
};
};
i2c@118000 {
......@@ -125,6 +136,31 @@ pca9546@77 {
};
};
fman@400000 {
ethernet@e6000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
mdio0: mdio@fc000 {
phy_sgmii_2: ethernet-phy@03 {
reg = <0x03>;
};
phy_rgmii_0: ethernet-phy@01 {
reg = <0x01>;
};
phy_rgmii_1: ethernet-phy@02 {
reg = <0x02>;
};
};
};
};
pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t2080qds.dts
View file @ a1b53446
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arch/powerpc/boot/dts/fsl/t2080rdb.dts
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/*
* T2080PCIe-RDB Board Device Tree Source
*
* Copyright 2014 Freescale Semiconductor Inc.
* Copyright 2014 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -54,4 +54,69 @@ port2 {
};
};
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&xg_aq1202_phy3>;
phy-connection-type = "xgmii";
};
ethernet@e2000 {
phy-handle = <&xg_aq1202_phy4>;
phy-connection-type = "xgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&xg_cs4315_phy1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xg_cs4315_phy2>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
mdio@fd000 {
xg_cs4315_phy1: ethernet-phy@c {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0xc>;
};
xg_cs4315_phy2: ethernet-phy@d {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0xd>;
};
xg_aq1202_phy3: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
xg_aq1202_phy4: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
};
};
};
/include/ "t2080si-post.dtsi"
arch/powerpc/boot/dts/fsl/t2081qds.dts
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arch/powerpc/boot/dts/fsl/t208xqds.dtsi
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......@@ -112,7 +112,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11"; /* 16MB */
compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
reg = <0>;
spi-max-frequency = <40000000>; /* input clock */
};
......@@ -120,7 +120,7 @@ flash@0 {
flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25wf040";
compatible = "sst,sst25wf040", "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <35000000>;
};
......@@ -128,7 +128,7 @@ flash@1 {
flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "eon,en25s64";
compatible = "eon,en25s64", "jedec,spi-nor";
reg = <2>;
spi-max-frequency = <35000000>;
};
......
arch/powerpc/boot/dts/fsl/t208xrdb.dtsi
View file @ a1b53446
......@@ -113,7 +113,7 @@ spi@110000 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q512a";
compatible = "micron,n25q512a", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
......
arch/powerpc/boot/dts/fsl/t4240qds.dts
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arch/powerpc/configs/83xx/mpc834x_itx_defconfig
View file @ a1b53446
......@@ -35,7 +35,6 @@ CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_IDE=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_SCSI_SPI_ATTRS=y
......
arch/powerpc/configs/85xx/ksi8560_defconfig
View file @ a1b53446
......@@ -34,7 +34,6 @@ CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_IDE=y
CONFIG_NETDEVICES=y
CONFIG_FS_ENET=y
# CONFIG_FS_ENET_HAS_SCC is not set
......
arch/powerpc/configs/85xx/stx_gp3_defconfig
View file @ a1b53446
......@@ -31,8 +31,6 @@ CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_IDE=y
CONFIG_BLK_DEV_IDECD=m
CONFIG_SCSI=m
CONFIG_BLK_DEV_SD=m
CONFIG_CHR_DEV_ST=m
......
arch/powerpc/configs/86xx-smp.config 0 → 100644
View file @ a1b53446
CONFIG_NR_CPUS=2
CONFIG_SMP=y
arch/powerpc/configs/86xx/gef_ppc9a_defconfig deleted 100644 → 0
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