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Commit a200ad22 authored by Mike Frysinger's avatar Mike Frysinger
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Blackfin: update anomaly lists 

Update anomaly headers to match latest released anomaly sheets.
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 4d5e6fd4
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Showing with 178 additions and 125 deletions
arch/blackfin/mach-bf518/include/mach/anomaly.h
View file @ a200ad22
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
*/ */
/* This file should be up to date with: /* This file should be up to date with:
* - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List * - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
*/ */
/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ /* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
...@@ -45,29 +45,31 @@ ...@@ -45,29 +45,31 @@
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1) #define ANOMALY_05000426 (1)
/* Software System Reset Corrupts PLL_LOCKCNT Register */ /* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (1) #define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (1) #define ANOMALY_05000431 (1)
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
#define ANOMALY_05000435 (1) #define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
#define ANOMALY_05000438 (1) #define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
/* Preboot Cannot be Used to Alter the PLL_DIV Register */ /* Preboot Cannot be Used to Alter the PLL_DIV Register */
#define ANOMALY_05000439 (1) #define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
#define ANOMALY_05000440 (1) #define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1) #define ANOMALY_05000443 (1)
/* Incorrect L1 Instruction Bank B Memory Map Location */ /* Incorrect L1 Instruction Bank B Memory Map Location */
#define ANOMALY_05000444 (1) #define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
#define ANOMALY_05000452 (1) #define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
/* PWM_TRIPB Signal Not Available on PG10 */ /* PWM_TRIPB Signal Not Available on PG10 */
#define ANOMALY_05000453 (1) #define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
#define ANOMALY_05000455 (1) #define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
/* False Hardware Error when RETI points to invalid memory */ /* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0) #define ANOMALY_05000099 (0)
...@@ -78,24 +80,30 @@ ...@@ -78,24 +80,30 @@
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0) #define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0) #define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0) #define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0) #define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0) #define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0) #define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0) #define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0) #define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0) #define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0) #define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0) #define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0) #define ANOMALY_05000250 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0) #define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0) #define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0) #define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0) #define ANOMALY_05000278 (0)
#define ANOMALY_05000281 (0)
#define ANOMALY_05000283 (0)
#define ANOMALY_05000285 (0) #define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0) #define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0) #define ANOMALY_05000301 (0)
...@@ -103,10 +111,13 @@ ...@@ -103,10 +111,13 @@
#define ANOMALY_05000307 (0) #define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0) #define ANOMALY_05000312 (0)
#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (0) #define ANOMALY_05000353 (0)
#define ANOMALY_05000357 (0)
#define ANOMALY_05000362 (1) #define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0) #define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (0) #define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0) #define ANOMALY_05000389 (0)
...@@ -117,5 +128,7 @@ ...@@ -117,5 +128,7 @@
#define ANOMALY_05000448 (0) #define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0) #define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0) #define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#endif #endif
arch/blackfin/mach-bf527/include/mach/anomaly.h
View file @ a200ad22
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) #define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) #define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ #define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
...@@ -184,8 +184,12 @@ ...@@ -184,8 +184,12 @@
#define ANOMALY_05000456 (1) #define ANOMALY_05000456 (1)
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
#define ANOMALY_05000457 (1) #define ANOMALY_05000457 (1)
/* False Hardware Error when RETI points to invalid memory */ /* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* USB Rx DMA hang */
#define ANOMALY_05000465 (1)
/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
#define ANOMALY_05000467 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0) #define ANOMALY_05000099 (0)
...@@ -195,24 +199,30 @@ ...@@ -195,24 +199,30 @@
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0) #define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0) #define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0) #define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0) #define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0) #define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0) #define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0) #define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0) #define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0) #define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0) #define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0) #define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0) #define ANOMALY_05000250 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0) #define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0) #define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0) #define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0) #define ANOMALY_05000278 (0)
#define ANOMALY_05000281 (0)
#define ANOMALY_05000283 (0)
#define ANOMALY_05000285 (0) #define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0) #define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0) #define ANOMALY_05000301 (0)
...@@ -220,6 +230,7 @@ ...@@ -220,6 +230,7 @@
#define ANOMALY_05000307 (0) #define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0) #define ANOMALY_05000312 (0)
#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1) #define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
......
arch/blackfin/mach-bf537/include/mach/anomaly.h
View file @ a200ad22
...@@ -34,13 +34,13 @@ ...@@ -34,13 +34,13 @@
# define ANOMALY_BF537 0 # define ANOMALY_BF537 0
#endif #endif
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) #define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ /* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) #define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000180 (1) #define ANOMALY_05000180 (1)
...@@ -50,11 +50,11 @@ ...@@ -50,11 +50,11 @@
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) #define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1) #define ANOMALY_05000245 (1)
/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ /* Buffered CLKIN Output Is Disabled by Default */
#define ANOMALY_05000247 (1) #define ANOMALY_05000247 (1)
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) #define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
/* EMAC Tx DMA error after an early frame abort */ /* EMAC TX DMA Error After an Early Frame Abort */
#define ANOMALY_05000252 (__SILICON_REVISION__ < 3) #define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
/* Maximum External Clock Speed for Timers */ /* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (__SILICON_REVISION__ < 3) #define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
...@@ -62,7 +62,7 @@ ...@@ -62,7 +62,7 @@
#define ANOMALY_05000254 (__SILICON_REVISION__ > 2) #define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
#define ANOMALY_05000255 (__SILICON_REVISION__ < 3) #define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
/* EMAC MDIO input latched on wrong MDC edge */ /* EMAC MDIO Input Latched on Wrong MDC Edge */
#define ANOMALY_05000256 (__SILICON_REVISION__ < 3) #define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
#define ANOMALY_05000257 (__SILICON_REVISION__ < 3) #define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
...@@ -80,7 +80,7 @@ ...@@ -80,7 +80,7 @@
#define ANOMALY_05000264 (__SILICON_REVISION__ < 3) #define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1) #define ANOMALY_05000265 (1)
/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ /* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
#define ANOMALY_05000268 (__SILICON_REVISION__ < 3) #define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 3) #define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
...@@ -92,15 +92,15 @@ ...@@ -92,15 +92,15 @@
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) #define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
/* SPI Master boot mode does not work well with Atmel Data flash devices */ /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
#define ANOMALY_05000280 (1) #define ANOMALY_05000280 (1)
/* False Hardware Error Exception When ISR Context Is Not Restored */ /* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) #define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) #define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 3) #define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ /* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
#define ANOMALY_05000285 (__SILICON_REVISION__ < 3) #define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */ /* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 3) #define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
...@@ -112,25 +112,25 @@ ...@@ -112,25 +112,25 @@
#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) #define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */ /* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) #define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ /* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
#define ANOMALY_05000309 (__SILICON_REVISION__ < 3) #define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1) #define ANOMALY_05000310 (1)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1) #define ANOMALY_05000312 (1)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (1) #define ANOMALY_05000313 (1)
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 3) #define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
/* EMAC RMII mode: collisions occur in Full Duplex mode */ /* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
#define ANOMALY_05000316 (__SILICON_REVISION__ < 3) #define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ /* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) #define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ /* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
#define ANOMALY_05000322 (1) #define ANOMALY_05000322 (1)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
/* New Feature: UART Remains Enabled after UART Boot */ /* UART Gets Disabled after UART Boot */
#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (1) #define ANOMALY_05000355 (1)
...@@ -154,7 +154,7 @@ ...@@ -154,7 +154,7 @@
#define ANOMALY_05000426 (1) #define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1) #define ANOMALY_05000443 (1)
/* False Hardware Error when RETI points to invalid memory */ /* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
...@@ -165,14 +165,17 @@ ...@@ -165,14 +165,17 @@
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0) #define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0) #define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0) #define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0) #define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0) #define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0) #define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0) #define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0) #define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0) #define ANOMALY_05000242 (0)
#define ANOMALY_05000248 (0) #define ANOMALY_05000248 (0)
#define ANOMALY_05000266 (0) #define ANOMALY_05000266 (0)
...@@ -195,5 +198,7 @@ ...@@ -195,5 +198,7 @@
#define ANOMALY_05000448 (0) #define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0) #define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0) #define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#endif #endif
arch/blackfin/mach-bf538/include/mach/anomaly.h
View file @ a200ad22
...@@ -30,13 +30,13 @@ ...@@ -30,13 +30,13 @@
# define ANOMALY_BF539 0 # define ANOMALY_BF539 0
#endif #endif
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) #define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1) #define ANOMALY_05000166 (1)
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
#define ANOMALY_05000179 (1) #define ANOMALY_05000179 (1)
...@@ -70,11 +70,11 @@ ...@@ -70,11 +70,11 @@
#define ANOMALY_05000277 (__SILICON_REVISION__ < 4) #define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 4) #define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
/* False Hardware Error Exception When ISR Context Is Not Restored */ /* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 4) #define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 4) #define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 4) #define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */ /* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 4) #define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
...@@ -92,11 +92,11 @@ ...@@ -92,11 +92,11 @@
#define ANOMALY_05000307 (__SILICON_REVISION__ < 4) #define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1) #define ANOMALY_05000310 (1)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (__SILICON_REVISION__ < 5) #define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (__SILICON_REVISION__ < 4) #define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 4) #define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) #define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
...@@ -110,7 +110,7 @@ ...@@ -110,7 +110,7 @@
#define ANOMALY_05000371 (__SILICON_REVISION__ < 5) #define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */ /* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
#define ANOMALY_05000374 (__SILICON_REVISION__ == 4) #define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
/* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */ /* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
#define ANOMALY_05000375 (__SILICON_REVISION__ < 4) #define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ < 4) #define ANOMALY_05000402 (__SILICON_REVISION__ < 4)
...@@ -126,26 +126,32 @@ ...@@ -126,26 +126,32 @@
#define ANOMALY_05000436 (__SILICON_REVISION__ > 3) #define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1) #define ANOMALY_05000443 (1)
/* False Hardware Error when RETI points to invalid memory */ /* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0) #define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0) #define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0) #define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0) #define ANOMALY_05000171 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0) #define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0) #define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0) #define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0) #define ANOMALY_05000231 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0) #define ANOMALY_05000242 (0)
#define ANOMALY_05000248 (0) #define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0) #define ANOMALY_05000250 (0)
#define ANOMALY_05000254 (0) #define ANOMALY_05000254 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000274 (0) #define ANOMALY_05000274 (0)
#define ANOMALY_05000287 (0) #define ANOMALY_05000287 (0)
#define ANOMALY_05000305 (0) #define ANOMALY_05000305 (0)
...@@ -166,5 +172,7 @@ ...@@ -166,5 +172,7 @@
#define ANOMALY_05000448 (0) #define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0) #define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0) #define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#endif #endif
arch/blackfin/mach-bf548/include/mach/anomaly.h
View file @ a200ad22
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
# error will not work on BF548 silicon version 0.0, or 0.1 # error will not work on BF548 silicon version 0.0, or 0.1
#endif #endif
/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1) #define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) #define ANOMALY_05000119 (1)
...@@ -30,17 +30,17 @@ ...@@ -30,17 +30,17 @@
#define ANOMALY_05000265 (1) #define ANOMALY_05000265 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1) #define ANOMALY_05000272 (1)
/* False Hardware Error Exception When ISR Context Is Not Restored */ /* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) #define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) #define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1) #define ANOMALY_05000310 (1)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) #define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
/* TWI Slave Boot Mode Is Not Functional */ /* TWI Slave Boot Mode Is Not Functional */
#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) #define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
/* External FIFO Boot Mode Is Not Functional */ /* FIFO Boot Mode Not Functional */
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2) #define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) #define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
...@@ -178,8 +178,12 @@ ...@@ -178,8 +178,12 @@
#define ANOMALY_05000450 (1) #define ANOMALY_05000450 (1)
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
#define ANOMALY_05000456 (__SILICON_REVISION__ < 3) #define ANOMALY_05000456 (__SILICON_REVISION__ < 3)
/* False Hardware Error when RETI points to invalid memory */ /* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* USB Rx DMA hang */
#define ANOMALY_05000465 (1)
/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
#define ANOMALY_05000467 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0) #define ANOMALY_05000099 (0)
...@@ -189,30 +193,36 @@ ...@@ -189,30 +193,36 @@
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0) #define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0) #define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0) #define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0) #define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0) #define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0) #define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0) #define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0) #define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0) #define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0) #define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0) #define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0) #define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0) #define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0) #define ANOMALY_05000250 (0)
#define ANOMALY_05000254 (0) #define ANOMALY_05000254 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0) #define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0) #define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0) #define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0) #define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0) #define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0) #define ANOMALY_05000278 (0)
#define ANOMALY_05000283 (0)
#define ANOMALY_05000287 (0) #define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0) #define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0) #define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0) #define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0) #define ANOMALY_05000311 (0)
#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0) #define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1) #define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
......
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