Commit a22f0788 authored by Yaniv Rosner's avatar Yaniv Rosner Committed by David S. Miller

bnx2x: Add dual-media changes

Add required changes in order to support dual-media boards.
Signed-off-by: default avatarYaniv Rosner <yanivr@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent de6eae1f
...@@ -566,13 +566,13 @@ struct bnx2x_common { ...@@ -566,13 +566,13 @@ struct bnx2x_common {
struct bnx2x_port { struct bnx2x_port {
u32 pmf; u32 pmf;
u32 link_config; u32 link_config[LINK_CONFIG_SIZE];
u32 supported; u32 supported[LINK_CONFIG_SIZE];
/* link settings - missing defines */ /* link settings - missing defines */
#define SUPPORTED_2500baseX_Full (1 << 15) #define SUPPORTED_2500baseX_Full (1 << 15)
u32 advertising; u32 advertising[LINK_CONFIG_SIZE];
/* link settings - missing defines */ /* link settings - missing defines */
#define ADVERTISED_2500baseX_Full (1 << 15) #define ADVERTISED_2500baseX_Full (1 << 15)
...@@ -931,7 +931,7 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, ...@@ -931,7 +931,7 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
u32 bnx2x_fw_command(struct bnx2x *bp, u32 command); u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
u32 addr, u32 len); u32 addr, u32 len);
...@@ -939,7 +939,7 @@ void bnx2x_calc_fc_adv(struct bnx2x *bp); ...@@ -939,7 +939,7 @@ void bnx2x_calc_fc_adv(struct bnx2x *bp);
int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
u32 data_hi, u32 data_lo, int common); u32 data_hi, u32 data_lo, int common);
void bnx2x_update_coalesce(struct bnx2x *bp); void bnx2x_update_coalesce(struct bnx2x *bp);
int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
int wait) int wait)
{ {
......
...@@ -1283,7 +1283,7 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode) ...@@ -1283,7 +1283,7 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
common blocks should be initialized, otherwise - not common blocks should be initialized, otherwise - not
*/ */
if (!BP_NOMCP(bp)) { if (!BP_NOMCP(bp)) {
load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ); load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0);
if (!load_code) { if (!load_code) {
BNX2X_ERR("MCP response failure, aborting\n"); BNX2X_ERR("MCP response failure, aborting\n");
rc = -EBUSY; rc = -EBUSY;
...@@ -1322,9 +1322,9 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode) ...@@ -1322,9 +1322,9 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
rc = bnx2x_init_hw(bp, load_code); rc = bnx2x_init_hw(bp, load_code);
if (rc) { if (rc) {
BNX2X_ERR("HW init failed, aborting\n"); BNX2X_ERR("HW init failed, aborting\n");
bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE); bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP); bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
goto load_error2; goto load_error2;
} }
...@@ -1339,7 +1339,7 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode) ...@@ -1339,7 +1339,7 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
/* Send LOAD_DONE command to MCP */ /* Send LOAD_DONE command to MCP */
if (!BP_NOMCP(bp)) { if (!BP_NOMCP(bp)) {
load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE); load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
if (!load_code) { if (!load_code) {
BNX2X_ERR("MCP response failure, aborting\n"); BNX2X_ERR("MCP response failure, aborting\n");
rc = -EBUSY; rc = -EBUSY;
...@@ -1455,8 +1455,8 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode) ...@@ -1455,8 +1455,8 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
load_error3: load_error3:
bnx2x_int_disable_sync(bp, 1); bnx2x_int_disable_sync(bp, 1);
if (!BP_NOMCP(bp)) { if (!BP_NOMCP(bp)) {
bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP); bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE); bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
} }
bp->port.pmf = 0; bp->port.pmf = 0;
/* Free SKBs, SGEs, TPA pool and driver internals */ /* Free SKBs, SGEs, TPA pool and driver internals */
......
...@@ -49,10 +49,11 @@ void bnx2x_link_set(struct bnx2x *bp); ...@@ -49,10 +49,11 @@ void bnx2x_link_set(struct bnx2x *bp);
* Query link status * Query link status
* *
* @param bp * @param bp
* @param is_serdes
* *
* @return 0 - link is UP * @return 0 - link is UP
*/ */
u8 bnx2x_link_test(struct bnx2x *bp); u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
/** /**
* Handles link status change * Handles link status change
......
This diff is collapsed.
...@@ -238,7 +238,88 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ ...@@ -238,7 +238,88 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
u16 xgxs_config_tx[4]; /* 0x1A0 */ u16 xgxs_config_tx[4]; /* 0x1A0 */
u32 Reserved1[64]; /* 0x1A8 */ u32 Reserved1[57]; /* 0x1A8 */
u32 speed_capability_mask2; /* 0x28C */
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12G 0x00000080
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12_DOT_5G 0x00000100
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_13G 0x00000200
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_15G 0x00000400
#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_16G 0x00000800
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12G 0x00800000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12_DOT_5G 0x01000000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_13G 0x02000000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_15G 0x04000000
#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_16G 0x08000000
/* In the case where two media types (e.g. copper and fiber) are
present and electrically active at the same time, PHY Selection
will determine which of the two PHYs will be designated as the
Active PHY and used for a connection to the network. */
u32 multi_phy_config; /* 0x290 */
#define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
#define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
#define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
/* When enabled, all second phy nvram parameters will be swapped
with the first phy parameters */
#define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
#define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
#define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
#define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
/* Address of the second external phy */
u32 external_phy_config2; /* 0x294 */
#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
/* The second XGXS external PHY type */
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
/* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
8706, 8726 and 8727) not all 4 values are needed. */
u16 xgxs_config2_rx[4]; /* 0x296 */
u16 xgxs_config2_tx[4]; /* 0x2A0 */
u32 lane_config; u32 lane_config;
#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
...@@ -534,8 +615,15 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ ...@@ -534,8 +615,15 @@ struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
/* The default for MCP link configuration, /* The default for MCP link configuration,
uses the same defines as link_config */ uses the same defines as link_config */
u32 mfw_wol_link_cfg; u32 mfw_wol_link_cfg;
/* The default for the driver of the second external phy,
uses the same defines as link_config */
u32 link_config2; /* 0x47C */
/* The default for MCP of the second external phy,
uses the same defines as link_config */
u32 mfw_wol_link_cfg2; /* 0x480 */
u32 reserved[19]; u32 Reserved2[17]; /* 0x484 */
}; };
...@@ -703,8 +791,14 @@ struct drv_func_mb { ...@@ -703,8 +791,14 @@ struct drv_func_mb {
* The optic module verification commands require bootcode * The optic module verification commands require bootcode
* v5.0.6 or later * v5.0.6 or later
*/ */
#define DRV_MSG_CODE_VRFY_OPT_MDL 0xa0000000 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
#define REQ_BC_VER_4_VRFY_OPT_MDL 0x00050006 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
/*
* The specific optic module verification command requires bootcode
* v5.2.12 or later
*/
#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
...@@ -939,7 +1033,12 @@ struct shmem2_region { ...@@ -939,7 +1033,12 @@ struct shmem2_region {
#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
#define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE #define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE
u32 ext_phy_fw_version2[PORT_MAX];
/*
* For backwards compatibility, if the mf_cfg_addr does not exist
* (the size filed is smaller than 0xc) the mf_cfg resides at the
* end of struct shmem_region
*/
}; };
......
This diff is collapsed.
...@@ -59,13 +59,18 @@ ...@@ -59,13 +59,18 @@
#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) #define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
/* Single Media board contains single external phy */ /* Single Media board contains single external phy */
#define SINGLE_MEDIA(params) (params->num_phys == 2) #define SINGLE_MEDIA(params) (params->num_phys == 2)
/* Dual Media board contains two external phy with different media */
#define DUAL_MEDIA(params) (params->num_phys == 3)
#define FW_PARAM_MDIO_CTRL_OFFSET 16
#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
(phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
/***********************************************************/ /***********************************************************/
/* Structs */ /* Structs */
/***********************************************************/ /***********************************************************/
#define INT_PHY 0 #define INT_PHY 0
#define EXT_PHY1 1 #define EXT_PHY1 1
#define EXT_PHY2 2
#define MAX_PHYS 2 #define MAX_PHYS 3
/* Same configuration is shared between the XGXS and the first external phy */ /* Same configuration is shared between the XGXS and the first external phy */
#define LINK_CONFIG_SIZE (MAX_PHYS - 1) #define LINK_CONFIG_SIZE (MAX_PHYS - 1)
...@@ -91,6 +96,8 @@ typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len); ...@@ -91,6 +96,8 @@ typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params); typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
typedef void (*set_link_led_t)(struct bnx2x_phy *phy, typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
struct link_params *params, u8 mode); struct link_params *params, u8 mode);
typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
struct link_params *params, u32 action);
struct bnx2x_phy { struct bnx2x_phy {
u32 type; u32 type;
...@@ -107,6 +114,8 @@ struct bnx2x_phy { ...@@ -107,6 +114,8 @@ struct bnx2x_phy {
#define FLAGS_FAN_FAILURE_DET_REQ (1<<2) #define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
/* Initialize first the XGXS and only then the phy itself */ /* Initialize first the XGXS and only then the phy itself */
#define FLAGS_INIT_XGXS_FIRST (1<<3) #define FLAGS_INIT_XGXS_FIRST (1<<3)
#define FLAGS_REARM_LATCH_SIGNAL (1<<6)
#define FLAGS_SFP_NOT_APPROVED (1<<7)
u8 def_md_devad; u8 def_md_devad;
u8 reserved; u8 reserved;
...@@ -161,6 +170,11 @@ struct bnx2x_phy { ...@@ -161,6 +170,11 @@ struct bnx2x_phy {
/* Set link led mode (on/off/oper)*/ /* Set link led mode (on/off/oper)*/
set_link_led_t set_link_led; set_link_led_t set_link_led;
/* PHY Specific tasks */
phy_specific_func_t phy_specific_func;
#define DISABLE_TX 1
#define ENABLE_TX 2
}; };
/* Inputs parameters to the CLC */ /* Inputs parameters to the CLC */
...@@ -177,18 +191,18 @@ struct link_params { ...@@ -177,18 +191,18 @@ struct link_params {
#define LOOPBACK_EXT_PHY 4 #define LOOPBACK_EXT_PHY 4
#define LOOPBACK_EXT 5 #define LOOPBACK_EXT 5
u16 req_duplex;
u16 req_flow_ctrl;
u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
req_flow_ctrl is set to AUTO */
u16 req_line_speed; /* Also determine AutoNeg */
/* Device parameters */ /* Device parameters */
u8 mac_addr[6]; u8 mac_addr[6];
u16 req_duplex[LINK_CONFIG_SIZE];
u16 req_flow_ctrl[LINK_CONFIG_SIZE];
u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
/* shmem parameters */ /* shmem parameters */
u32 shmem_base; u32 shmem_base;
u32 speed_cap_mask; u32 shmem2_base;
u32 speed_cap_mask[LINK_CONFIG_SIZE];
u32 switch_cfg; u32 switch_cfg;
#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
...@@ -202,6 +216,7 @@ struct link_params { ...@@ -202,6 +216,7 @@ struct link_params {
u32 feature_config_flags; u32 feature_config_flags;
#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
/* Will be populated during common init */ /* Will be populated during common init */
struct bnx2x_phy phy[MAX_PHYS]; struct bnx2x_phy phy[MAX_PHYS];
...@@ -210,9 +225,12 @@ struct link_params { ...@@ -210,9 +225,12 @@ struct link_params {
u8 rsrv; u8 rsrv;
u16 hw_led_mode; /* part of the hw_config read from the shmem */ u16 hw_led_mode; /* part of the hw_config read from the shmem */
u32 multi_phy_config;
/* Device pointer passed to all callback functions */ /* Device pointer passed to all callback functions */
struct bnx2x *bp; struct bnx2x *bp;
u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
req_flow_ctrl is set to AUTO */
}; };
/* Output parameters */ /* Output parameters */
...@@ -233,12 +251,6 @@ struct link_vars { ...@@ -233,12 +251,6 @@ struct link_vars {
u16 flow_ctrl; u16 flow_ctrl;
u16 ieee_fc; u16 ieee_fc;
u32 autoneg;
#define AUTO_NEG_DISABLED 0x0
#define AUTO_NEG_ENABLED 0x1
#define AUTO_NEG_COMPLETE 0x2
#define AUTO_NEG_PARALLEL_DETECTION_USED 0x3
/* The same definitions as the shmem parameter */ /* The same definitions as the shmem parameter */
u32 link_status; u32 link_status;
}; };
...@@ -246,8 +258,6 @@ struct link_vars { ...@@ -246,8 +258,6 @@ struct link_vars {
/***********************************************************/ /***********************************************************/
/* Functions */ /* Functions */
/***********************************************************/ /***********************************************************/
/* Initialize the phy */
u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output); u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
/* Reset the link. Should be called when driver or interface goes down /* Reset the link. Should be called when driver or interface goes down
...@@ -298,10 +308,11 @@ void bnx2x_handle_module_detect_int(struct link_params *params); ...@@ -298,10 +308,11 @@ void bnx2x_handle_module_detect_int(struct link_params *params);
/* Get the actual link status. In case it returns 0, link is up, /* Get the actual link status. In case it returns 0, link is up,
otherwise link is down*/ otherwise link is down*/
u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars); u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars,
u8 is_serdes);
/* One-time initialization for external phy after power up */ /* One-time initialization for external phy after power up */
u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base); u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base);
/* Reset the external PHY using GPIO */ /* Reset the external PHY using GPIO */
void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port); void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
...@@ -316,12 +327,19 @@ u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, ...@@ -316,12 +327,19 @@ u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
void bnx2x_hw_reset_phy(struct link_params *params); void bnx2x_hw_reset_phy(struct link_params *params);
/* Checks if HW lock is required for this phy/board type */ /* Checks if HW lock is required for this phy/board type */
u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base); u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base,
u32 shmem2_base);
/* Returns the aggregative supported attributes of the phys on board */ /* Returns the aggregative supported attributes of the phys on board */
u32 bnx2x_supported_attr(struct link_params *params, u8 phy_idx); u32 bnx2x_supported_attr(struct link_params *params, u8 phy_idx);
/* Check swap bit and adjust PHY order */
u32 bnx2x_phy_selection(struct link_params *params);
/* Probe the phys on board, and populate them in "params" */ /* Probe the phys on board, and populate them in "params" */
u8 bnx2x_phy_probe(struct link_params *params); u8 bnx2x_phy_probe(struct link_params *params);
/* Checks if fan failure detection is required on one of the phys on board */ /* Checks if fan failure detection is required on one of the phys on board */
u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base, u8 port); u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
u32 shmem2_base, u8 port);
#endif /* BNX2X_LINK_H */ #endif /* BNX2X_LINK_H */
This diff is collapsed.
...@@ -4964,6 +4964,8 @@ ...@@ -4964,6 +4964,8 @@
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
...@@ -5192,6 +5194,8 @@ Theotherbitsarereservedandshouldbezero*/ ...@@ -5192,6 +5194,8 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_XS_8706_REG_BANK_RX3 0x80ec #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
#define MDIO_XS_8706_REG_BANK_RXA 0x80fc #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
#define MDIO_AN_DEVAD 0x7 #define MDIO_AN_DEVAD 0x7
/*ieee*/ /*ieee*/
#define MDIO_AN_REG_CTRL 0x0000 #define MDIO_AN_REG_CTRL 0x0000
...@@ -5227,6 +5231,27 @@ Theotherbitsarereservedandshouldbezero*/ ...@@ -5227,6 +5231,27 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
/* BCM84823 only */
#define MDIO_CTL_DEVAD 0x1e
#define MDIO_CTL_REG_84823_MEDIA 0x401a
#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
/* These pins configure the BCM84823 interface to MAC after reset. */
#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
/* These pins configure the BCM84823 interface to Line after reset. */
#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
/* When this pin is active high during reset, 10GBASE-T core is power
* down, When it is active low the 10GBASE-T is power up
*/
#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
#define IGU_FUNC_BASE 0x0400 #define IGU_FUNC_BASE 0x0400
#define IGU_ADDR_MSIX 0x0000 #define IGU_ADDR_MSIX 0x0000
......
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