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Commit a23fde09 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Felix Fietkau
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mt76: use mt76x02_dev instead of mt76_dev in mt76x02_mmio.c 

Use mt76x02_dev data structure as reference in mt76x02_mmio.c
instead of mt76_dev
Signed-off-by: default avatarLorenzo Bianconi <lorenzo.bianconi@redhat.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 466495b1
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Inline Side-by-side
Showing with 64 additions and 62 deletions
drivers/net/wireless/mediatek/mt76/mt76.h
View file @ a23fde09
......@@ -517,8 +517,8 @@ static inline u16 mt76_rev(struct mt76_dev *dev)
#define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
#define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
#define __mt76_init_queues(dev) (dev)->queue_ops->init((dev))
#define __mt76_queue_alloc(dev, ...) (dev)->queue_ops->alloc((dev), __VA_ARGS__)
#define mt76_init_queues(dev) (dev)->mt76.queue_ops->init(&((dev)->mt76))
#define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_add_buf(dev, ...) (dev)->mt76.queue_ops->add_buf(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)
#define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)
......
drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
View file @ a23fde09
......@@ -27,7 +27,7 @@ static int mt76x0e_start(struct ieee80211_hw *hw)
mutex_lock(&dev->mt76.mutex);
mt76x02_mac_start(&dev->mt76);
mt76x02_mac_start(dev);
ieee80211_queue_delayed_work(dev->mt76.hw, &dev->mac_work,
MT_CALIBRATE_INTERVAL);
ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
......@@ -85,12 +85,12 @@ static int mt76x0e_register_device(struct mt76x02_dev *dev)
if (!mt76x02_wait_for_mac(&dev->mt76))
return -ETIMEDOUT;
mt76x02_dma_disable(&dev->mt76);
mt76x02_dma_disable(dev);
err = mt76x0e_mcu_init(dev);
if (err < 0)
return err;
err = mt76x02_dma_init(&dev->mt76);
err = mt76x02_dma_init(dev);
if (err < 0)
return err;
......
drivers/net/wireless/mediatek/mt76/mt76x02.h
View file @ a23fde09
......@@ -155,15 +155,15 @@ int mt76x02_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
extern const u16 mt76x02_beacon_offsets[16];
void mt76x02_set_beacon_offsets(struct mt76_dev *dev);
void mt76x02_set_irq_mask(struct mt76_dev *dev, u32 clear, u32 set);
void mt76x02_mac_start(struct mt76_dev *dev);
void mt76x02_set_irq_mask(struct mt76x02_dev *dev, u32 clear, u32 set);
void mt76x02_mac_start(struct mt76x02_dev *dev);
static inline void mt76x02_irq_enable(struct mt76_dev *dev, u32 mask)
static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask)
{
mt76x02_set_irq_mask(dev, 0, mask);
}
static inline void mt76x02_irq_disable(struct mt76_dev *dev, u32 mask)
static inline void mt76x02_irq_disable(struct mt76x02_dev *dev, u32 mask)
{
mt76x02_set_irq_mask(dev, mask, 0);
}
......
drivers/net/wireless/mediatek/mt76/mt76x02_dma.h
View file @ a23fde09
......@@ -17,8 +17,8 @@
#ifndef __MT76x02_DMA_H
#define __MT76x02_DMA_H
#include "mt76x02.h"
#include "dma.h"
#include "mt76x02_regs.h"
#define MT_TXD_INFO_LEN GENMASK(15, 0)
#define MT_TXD_INFO_NEXT_VLD BIT(16)
......@@ -70,8 +70,7 @@ mt76x02_wait_for_wpdma(struct mt76_dev *dev, int timeout)
0, timeout);
}
int mt76x02_dma_init(struct mt76_dev *dev);
void mt76x02_dma_enable(struct mt76_dev *dev);
void mt76x02_dma_disable(struct mt76_dev *dev);
int mt76x02_dma_init(struct mt76x02_dev *dev);
void mt76x02_dma_disable(struct mt76x02_dev *dev);
#endif /* __MT76x02_DMA_H */
drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c
View file @ a23fde09
......@@ -20,16 +20,16 @@
#include "mt76x02.h"
static int
mt76x02_init_tx_queue(struct mt76_dev *dev, struct mt76_queue *q,
mt76x02_init_tx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
int idx, int n_desc)
{
int ret;
q->regs = dev->mmio.regs + MT_TX_RING_BASE + idx * MT_RING_SIZE;
q->regs = dev->mt76.mmio.regs + MT_TX_RING_BASE + idx * MT_RING_SIZE;
q->ndesc = n_desc;
q->hw_idx = idx;
ret = __mt76_queue_alloc(dev, q);
ret = mt76_queue_alloc(dev, q);
if (ret)
return ret;
......@@ -39,16 +39,16 @@ mt76x02_init_tx_queue(struct mt76_dev *dev, struct mt76_queue *q,
}
static int
mt76x02_init_rx_queue(struct mt76_dev *dev, struct mt76_queue *q,
mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
int idx, int n_desc, int bufsize)
{
int ret;
q->regs = dev->mmio.regs + MT_RX_RING_BASE + idx * MT_RING_SIZE;
q->regs = dev->mt76.mmio.regs + MT_RX_RING_BASE + idx * MT_RING_SIZE;
q->ndesc = n_desc;
q->buf_size = bufsize;
ret = __mt76_queue_alloc(dev, q);
ret = mt76_queue_alloc(dev, q);
if (ret)
return ret;
......@@ -57,7 +57,7 @@ mt76x02_init_rx_queue(struct mt76_dev *dev, struct mt76_queue *q,
return 0;
}
int mt76x02_dma_init(struct mt76_dev *dev)
int mt76x02_dma_init(struct mt76x02_dev *dev)
{
struct mt76_txwi_cache __maybe_unused *t;
struct mt76_queue *q;
......@@ -66,89 +66,89 @@ int mt76x02_dma_init(struct mt76_dev *dev)
BUILD_BUG_ON(sizeof(t->txwi) < sizeof(struct mt76x02_txwi));
BUILD_BUG_ON(sizeof(struct mt76x02_rxwi) > MT_RX_HEADROOM);
mt76_dma_attach(dev);
__mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
mt76_dma_attach(&dev->mt76);
mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
for (i = 0; i < IEEE80211_NUM_ACS; i++) {
ret = mt76x02_init_tx_queue(dev, &dev->q_tx[i],
ret = mt76x02_init_tx_queue(dev, &dev->mt76.q_tx[i],
mt76_ac_to_hwq(i),
MT_TX_RING_SIZE);
if (ret)
return ret;
}
ret = mt76x02_init_tx_queue(dev, &dev->q_tx[MT_TXQ_PSD],
ret = mt76x02_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_PSD],
MT_TX_HW_QUEUE_MGMT, MT_TX_RING_SIZE);
if (ret)
return ret;
ret = mt76x02_init_tx_queue(dev, &dev->q_tx[MT_TXQ_MCU],
ret = mt76x02_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
MT_TX_HW_QUEUE_MCU, MT_MCU_RING_SIZE);
if (ret)
return ret;
ret = mt76x02_init_rx_queue(dev, &dev->q_rx[MT_RXQ_MCU], 1,
ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
MT_MCU_RING_SIZE, MT_RX_BUF_SIZE);
if (ret)
return ret;
q = &dev->q_rx[MT_RXQ_MAIN];
q = &dev->mt76.q_rx[MT_RXQ_MAIN];
q->buf_offset = MT_RX_HEADROOM - sizeof(struct mt76x02_rxwi);
ret = mt76x02_init_rx_queue(dev, q, 0, MT76X02_RX_RING_SIZE,
MT_RX_BUF_SIZE);
if (ret)
return ret;
return __mt76_init_queues(dev);
return mt76_init_queues(dev);
}
EXPORT_SYMBOL_GPL(mt76x02_dma_init);
void mt76x02_set_irq_mask(struct mt76_dev *dev, u32 clear, u32 set)
void mt76x02_set_irq_mask(struct mt76x02_dev *dev, u32 clear, u32 set)
{
unsigned long flags;
spin_lock_irqsave(&dev->mmio.irq_lock, flags);
dev->mmio.irqmask &= ~clear;
dev->mmio.irqmask |= set;
__mt76_wr(dev, MT_INT_MASK_CSR, dev->mmio.irqmask);
spin_unlock_irqrestore(&dev->mmio.irq_lock, flags);
spin_lock_irqsave(&dev->mt76.mmio.irq_lock, flags);
dev->mt76.mmio.irqmask &= ~clear;
dev->mt76.mmio.irqmask |= set;
mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask);
spin_unlock_irqrestore(&dev->mt76.mmio.irq_lock, flags);
}
EXPORT_SYMBOL_GPL(mt76x02_set_irq_mask);
void mt76x02_dma_enable(struct mt76_dev *dev)
static void mt76x02_dma_enable(struct mt76x02_dev *dev)
{
u32 val;
__mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
mt76x02_wait_for_wpdma(dev, 1000);
mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
mt76x02_wait_for_wpdma(&dev->mt76, 1000);
usleep_range(50, 100);
val = FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
MT_WPDMA_GLO_CFG_TX_DMA_EN |
MT_WPDMA_GLO_CFG_RX_DMA_EN;
__mt76_set(dev, MT_WPDMA_GLO_CFG, val);
__mt76_clear(dev, MT_WPDMA_GLO_CFG,
mt76_set(dev, MT_WPDMA_GLO_CFG, val);
mt76_clear(dev, MT_WPDMA_GLO_CFG,
MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
}
EXPORT_SYMBOL_GPL(mt76x02_dma_enable);
void mt76x02_dma_disable(struct mt76_dev *dev)
void mt76x02_dma_disable(struct mt76x02_dev *dev)
{
u32 val = __mt76_rr(dev, MT_WPDMA_GLO_CFG);
u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
MT_WPDMA_GLO_CFG_BIG_ENDIAN |
MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
__mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
}
EXPORT_SYMBOL_GPL(mt76x02_dma_disable);
void mt76x02_mac_start(struct mt76_dev *dev)
void mt76x02_mac_start(struct mt76x02_dev *dev)
{
mt76x02_dma_enable(dev);
__mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
__mt76_wr(dev, MT_MAC_SYS_CTRL,
mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
mt76_wr(dev, MT_MAC_SYS_CTRL,
MT_MAC_SYS_CTRL_ENABLE_TX |
MT_MAC_SYS_CTRL_ENABLE_RX);
mt76x02_irq_enable(dev,
......
drivers/net/wireless/mediatek/mt76/mt76x2/pci_core.c
View file @ a23fde09
......@@ -20,7 +20,10 @@
void mt76x2_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
{
mt76x02_irq_enable(mdev, MT_INT_RX_DONE(q));
struct mt76x02_dev *dev;
dev = container_of(mdev, struct mt76x02_dev, mt76);
mt76x02_irq_enable(dev, MT_INT_RX_DONE(q));
}
irqreturn_t mt76x2_irq_handler(int irq, void *dev_instance)
......@@ -39,17 +42,17 @@ irqreturn_t mt76x2_irq_handler(int irq, void *dev_instance)
intr &= dev->mt76.mmio.irqmask;
if (intr & MT_INT_TX_DONE_ALL) {
mt76x02_irq_disable(&dev->mt76, MT_INT_TX_DONE_ALL);
mt76x02_irq_disable(dev, MT_INT_TX_DONE_ALL);
tasklet_schedule(&dev->tx_tasklet);
}
if (intr & MT_INT_RX_DONE(0)) {
mt76x02_irq_disable(&dev->mt76, MT_INT_RX_DONE(0));
mt76x02_irq_disable(dev, MT_INT_RX_DONE(0));
napi_schedule(&dev->mt76.napi[0]);
}
if (intr & MT_INT_RX_DONE(1)) {
mt76x02_irq_disable(&dev->mt76, MT_INT_RX_DONE(1));
mt76x02_irq_disable(dev, MT_INT_RX_DONE(1));
napi_schedule(&dev->mt76.napi[1]);
}
......@@ -66,7 +69,7 @@ irqreturn_t mt76x2_irq_handler(int irq, void *dev_instance)
}
if (intr & MT_INT_GPTIMER) {
mt76x02_irq_disable(&dev->mt76, MT_INT_GPTIMER);
mt76x02_irq_disable(dev, MT_INT_GPTIMER);
tasklet_schedule(&dev->dfs_pd.dfs_tasklet);
}
......
drivers/net/wireless/mediatek/mt76/mt76x2/pci_dfs.c
View file @ a23fde09
......@@ -679,7 +679,7 @@ static void mt76x2_dfs_tasklet(unsigned long arg)
mt76_wr(dev, MT_BBP(DFS, 1), 0xf);
out:
mt76x02_irq_enable(&dev->mt76, MT_INT_GPTIMER);
mt76x02_irq_enable(dev, MT_INT_GPTIMER);
}
static void mt76x2_dfs_init_sw_detector(struct mt76x02_dev *dev)
......@@ -835,7 +835,7 @@ void mt76x2_dfs_init_params(struct mt76x02_dev *dev)
/* enable debug mode */
mt76x2_dfs_set_capture_mode_ctrl(dev, true);
mt76x02_irq_enable(&dev->mt76, MT_INT_GPTIMER);
mt76x02_irq_enable(dev, MT_INT_GPTIMER);
mt76_rmw_field(dev, MT_INT_TIMER_EN,
MT_INT_TIMER_EN_GP_TIMER_EN, 1);
} else {
......@@ -845,7 +845,7 @@ void mt76x2_dfs_init_params(struct mt76x02_dev *dev)
mt76_wr(dev, MT_BBP(DFS, 1), 0xf);
mt76_wr(dev, 0x212c, 0);
mt76x02_irq_disable(&dev->mt76, MT_INT_GPTIMER);
mt76x02_irq_disable(dev, MT_INT_GPTIMER);
mt76_rmw_field(dev, MT_INT_TIMER_EN,
MT_INT_TIMER_EN_GP_TIMER_EN, 0);
}
......
drivers/net/wireless/mediatek/mt76/mt76x2/pci_dma.c
View file @ a23fde09
......@@ -27,7 +27,7 @@ void mt76x2_tx_tasklet(unsigned long data)
mt76_queue_tx_cleanup(dev, i, false);
mt76x02_mac_poll_tx_status(dev, false);
mt76x02_irq_enable(&dev->mt76, MT_INT_TX_DONE_ALL);
mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
}
void mt76x2_dma_cleanup(struct mt76x02_dev *dev)
......
drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c
View file @ a23fde09
......@@ -186,7 +186,7 @@ int mt76x2_mac_start(struct mt76x02_dev *dev)
mt76_rr(dev, MT_TX_STAT_FIFO);
memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats));
mt76x02_mac_start(&dev->mt76);
mt76x02_mac_start(dev);
return 0;
}
......@@ -301,7 +301,7 @@ int mt76x2_init_hardware(struct mt76x02_dev *dev)
tasklet_init(&dev->pre_tbtt_tasklet, mt76x2_pre_tbtt_tasklet,
(unsigned long) dev);
mt76x02_dma_disable(&dev->mt76);
mt76x02_dma_disable(dev);
mt76x2_reset_wlan(dev, true);
mt76x2_power_on(dev);
......@@ -315,7 +315,7 @@ int mt76x2_init_hardware(struct mt76x02_dev *dev)
dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
ret = mt76x02_dma_init(&dev->mt76);
ret = mt76x02_dma_init(dev);
if (ret)
return ret;
......
drivers/net/wireless/mediatek/mt76/mt76x2/pci_mac.c
View file @ a23fde09
......@@ -142,9 +142,9 @@ void mt76x2_mac_set_beacon_enable(struct mt76x02_dev *dev,
mt76_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en);
if (en)
mt76x02_irq_enable(&dev->mt76, MT_INT_PRE_TBTT | MT_INT_TBTT);
mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
else
mt76x02_irq_disable(&dev->mt76, MT_INT_PRE_TBTT | MT_INT_TBTT);
mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
}
void mt76x2_update_channel(struct mt76_dev *mdev)
......
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