Commit a2b91efd authored by Lucas Stach's avatar Lucas Stach Committed by Shawn Guo

arm64: dts: imx8mq: move watchdog nodes to correct location

The were added at the end of the AIPS1 address space, while they
are in fact in the middle.
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent bfeffd15
...@@ -199,6 +199,30 @@ gpio5: gpio@30240000 { ...@@ -199,6 +199,30 @@ gpio5: gpio@30240000 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
}; };
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
status = "disabled";
};
wdog2: watchdog@30290000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30290000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
status = "disabled";
};
wdog3: watchdog@302a0000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x302a0000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
status = "disabled";
};
iomuxc: iomuxc@30330000 { iomuxc: iomuxc@30330000 {
compatible = "fsl,imx8mq-iomuxc"; compatible = "fsl,imx8mq-iomuxc";
reg = <0x30330000 0x10000>; reg = <0x30330000 0x10000>;
...@@ -228,30 +252,6 @@ clk: clock-controller@30380000 { ...@@ -228,30 +252,6 @@ clk: clock-controller@30380000 {
"clk_ext1", "clk_ext2", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4"; "clk_ext3", "clk_ext4";
}; };
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
status = "disabled";
};
wdog2: watchdog@30290000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x30290000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
status = "disabled";
};
wdog3: watchdog@302a0000 {
compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
reg = <0x302a0000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
status = "disabled";
};
}; };
bus@30400000 { /* AIPS2 */ bus@30400000 { /* AIPS2 */
......
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