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Kirill Smelkov
linux
Commits
a31bb032
Commit
a31bb032
authored
Jun 30, 2016
by
Stephen Boyd
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Merge branch 'clk-hi6220-rtc' into clk-next
* clk-hi6220-rtc: clk: hi6220: Add RTC clock for pl031
parents
5ff5ec59
6fb924dc
Changes
2
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2 changed files
with
5 additions
and
2 deletions
+5
-2
drivers/clk/hisilicon/clk-hi6220.c
drivers/clk/hisilicon/clk-hi6220.c
+2
-0
include/dt-bindings/clock/hi6220-clock.h
include/dt-bindings/clock/hi6220-clock.h
+3
-2
No files found.
drivers/clk/hisilicon/clk-hi6220.c
View file @
a31bb032
...
@@ -68,6 +68,8 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
...
@@ -68,6 +68,8 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
{
HI6220_TIMER7_PCLK
,
"timer7_pclk"
,
"clk_tcxo"
,
CLK_SET_RATE_PARENT
|
CLK_IGNORE_UNUSED
,
0x630
,
22
,
0
,
},
{
HI6220_TIMER7_PCLK
,
"timer7_pclk"
,
"clk_tcxo"
,
CLK_SET_RATE_PARENT
|
CLK_IGNORE_UNUSED
,
0x630
,
22
,
0
,
},
{
HI6220_TIMER8_PCLK
,
"timer8_pclk"
,
"clk_tcxo"
,
CLK_SET_RATE_PARENT
|
CLK_IGNORE_UNUSED
,
0x630
,
23
,
0
,
},
{
HI6220_TIMER8_PCLK
,
"timer8_pclk"
,
"clk_tcxo"
,
CLK_SET_RATE_PARENT
|
CLK_IGNORE_UNUSED
,
0x630
,
23
,
0
,
},
{
HI6220_UART0_PCLK
,
"uart0_pclk"
,
"clk_tcxo"
,
CLK_SET_RATE_PARENT
|
CLK_IGNORE_UNUSED
,
0x630
,
24
,
0
,
},
{
HI6220_UART0_PCLK
,
"uart0_pclk"
,
"clk_tcxo"
,
CLK_SET_RATE_PARENT
|
CLK_IGNORE_UNUSED
,
0x630
,
24
,
0
,
},
{
HI6220_RTC0_PCLK
,
"rtc0_pclk"
,
"clk_tcxo"
,
CLK_SET_RATE_PARENT
|
CLK_IGNORE_UNUSED
,
0x630
,
25
,
0
,
},
{
HI6220_RTC1_PCLK
,
"rtc1_pclk"
,
"clk_tcxo"
,
CLK_SET_RATE_PARENT
|
CLK_IGNORE_UNUSED
,
0x630
,
26
,
0
,
},
};
};
static
void
__init
hi6220_clk_ao_init
(
struct
device_node
*
np
)
static
void
__init
hi6220_clk_ao_init
(
struct
device_node
*
np
)
...
...
include/dt-bindings/clock/hi6220-clock.h
View file @
a31bb032
...
@@ -55,8 +55,9 @@
...
@@ -55,8 +55,9 @@
#define HI6220_TIMER7_PCLK 34
#define HI6220_TIMER7_PCLK 34
#define HI6220_TIMER8_PCLK 35
#define HI6220_TIMER8_PCLK 35
#define HI6220_UART0_PCLK 36
#define HI6220_UART0_PCLK 36
#define HI6220_RTC0_PCLK 37
#define HI6220_AO_NR_CLKS 37
#define HI6220_RTC1_PCLK 38
#define HI6220_AO_NR_CLKS 39
/* clk in Hi6220 systrl */
/* clk in Hi6220 systrl */
/* gate clock */
/* gate clock */
...
...
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