Merge tag 'mips_5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:

 - added printing of CPU options for /proc/cpuinfo

 - removed support for Netlogic SOCs

 - fixes and cleanup

* tag 'mips_5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: Cobalt: Explain GT64111 early PCI fixup
  mips: fix HUGETLB function without THP enabled
  mips: cm: Convert to bitfield API to fix out-of-bounds access
  MIPS: Remove NETLOGIC support
  MIPS: kernel: proc: add CPU option reporting
  MIPS: kernel: proc: use seq_puts instead of seq_printf
  MIPS: kernel: proc: fix trivial style errors
  MIPS: Fix assembly error from MIPSr2 code used within MIPS_ISA_ARCH_LEVEL
  MIPS: octeon: Remove unused functions
  MIPS: Loongson64: Add of_node_put() before break
  bcm47xx: Replace printk(KERN_ALERT ... pci_devname(dev)) with pci_alert()
  bcm47xx: Get rid of redundant 'else'
  MIPS: sni: Fix the build
  MIPS: Avoid macro redefinitions
  MIPS: loongson64: Fix no screen display during boot-up
  MIPS: loongson64: make CPU_LOONGSON64 depends on MIPS_FP_SUPPORT

arch/mips/Kbuild.platforms

@@ -19,7 +19,6 @@ platform-$(CONFIG_MACH_LOONGSON32)	+= loongson32/
 platform-$(CONFIG_MACH_LOONGSON64)	+= loongson64/
 platform-$(CONFIG_MIPS_MALTA)		+= mti-malta/
 platform-$(CONFIG_MACH_NINTENDO64)	+= n64/
-platform-$(CONFIG_NLM_COMMON)		+= netlogic/
 platform-$(CONFIG_PIC32MZDA)		+= pic32/
 platform-$(CONFIG_RALINK)		+= ralink/
 platform-$(CONFIG_MIKROTIK_RB532)	+= rb532/

arch/mips/Kconfig

@@ -995,60 +995,6 @@ config CAVIUM_OCTEON_SOC
 		Hikari
 	  Say Y here for most Octeon reference boards.
 
-config NLM_XLR_BOARD
-	bool "Netlogic XLR/XLS based systems"
-	select BOOT_ELF32
-	select NLM_COMMON
-	select SYS_HAS_CPU_XLR
-	select SYS_SUPPORTS_SMP
-	select HAVE_PCI
-	select SWAP_IO_SPACE
-	select SYS_SUPPORTS_32BIT_KERNEL
-	select SYS_SUPPORTS_64BIT_KERNEL
-	select PHYS_ADDR_T_64BIT
-	select SYS_SUPPORTS_BIG_ENDIAN
-	select SYS_SUPPORTS_HIGHMEM
-	select NR_CPUS_DEFAULT_32
-	select CEVT_R4K
-	select CSRC_R4K
-	select IRQ_MIPS_CPU
-	select ZONE_DMA32 if 64BIT
-	select SYNC_R4K
-	select SYS_HAS_EARLY_PRINTK
-	select SYS_SUPPORTS_ZBOOT
-	select SYS_SUPPORTS_ZBOOT_UART16550
-	help
-	  Support for systems based on Netlogic XLR and XLS processors.
-	  Say Y here if you have a XLR or XLS based board.
-
-config NLM_XLP_BOARD
-	bool "Netlogic XLP based systems"
-	select BOOT_ELF32
-	select NLM_COMMON
-	select SYS_HAS_CPU_XLP
-	select SYS_SUPPORTS_SMP
-	select HAVE_PCI
-	select SYS_SUPPORTS_32BIT_KERNEL
-	select SYS_SUPPORTS_64BIT_KERNEL
-	select PHYS_ADDR_T_64BIT
-	select GPIOLIB
-	select SYS_SUPPORTS_BIG_ENDIAN
-	select SYS_SUPPORTS_LITTLE_ENDIAN
-	select SYS_SUPPORTS_HIGHMEM
-	select NR_CPUS_DEFAULT_32
-	select CEVT_R4K
-	select CSRC_R4K
-	select IRQ_MIPS_CPU
-	select ZONE_DMA32 if 64BIT
-	select SYNC_R4K
-	select SYS_HAS_EARLY_PRINTK
-	select USE_OF
-	select SYS_SUPPORTS_ZBOOT
-	select SYS_SUPPORTS_ZBOOT_UART16550
-	help
-	  This board is based on Netlogic XLP Processor.
-	  Say Y here if you have a XLP based board.
-
 endchoice
 
 source "arch/mips/alchemy/Kconfig"
@@ -1071,7 +1017,6 @@ source "arch/mips/cavium-octeon/Kconfig"
 source "arch/mips/loongson2ef/Kconfig"
 source "arch/mips/loongson32/Kconfig"
 source "arch/mips/loongson64/Kconfig"
-source "arch/mips/netlogic/Kconfig"
 
 endmenu
 
@@ -1371,6 +1316,7 @@ config CPU_LOONGSON64
 	select MIPS_ASID_BITS_VARIABLE
 	select MIPS_PGD_C0_CONTEXT
 	select MIPS_L1_CACHE_SHIFT_6
+	select MIPS_FP_SUPPORT
 	select GPIOLIB
 	select SWIOTLB
 	select HAVE_KVM
@@ -1778,32 +1724,6 @@ config CPU_BMIPS
 	help
 	  Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
 
-config CPU_XLR
-	bool "Netlogic XLR SoC"
-	depends on SYS_HAS_CPU_XLR
-	select CPU_SUPPORTS_32BIT_KERNEL
-	select CPU_SUPPORTS_64BIT_KERNEL
-	select CPU_SUPPORTS_HIGHMEM
-	select CPU_SUPPORTS_HUGEPAGES
-	select WEAK_ORDERING
-	select WEAK_REORDERING_BEYOND_LLSC
-	help
-	  Netlogic Microsystems XLR/XLS processors.
-
-config CPU_XLP
-	bool "Netlogic XLP SoC"
-	depends on SYS_HAS_CPU_XLP
-	select CPU_SUPPORTS_32BIT_KERNEL
-	select CPU_SUPPORTS_64BIT_KERNEL
-	select CPU_SUPPORTS_HIGHMEM
-	select WEAK_ORDERING
-	select WEAK_REORDERING_BEYOND_LLSC
-	select CPU_HAS_PREFETCH
-	select CPU_MIPSR2
-	select CPU_SUPPORTS_HUGEPAGES
-	select MIPS_ASID_BITS_VARIABLE
-	help
-	  Netlogic Microsystems XLP processors.
 endchoice
 
 config CPU_MIPS32_3_5_FEATURES
@@ -2050,12 +1970,6 @@ config SYS_HAS_CPU_BMIPS5000
 	select SYS_HAS_CPU_BMIPS
 	select ARCH_HAS_SYNC_DMA_FOR_CPU
 
-config SYS_HAS_CPU_XLR
-	bool
-
-config SYS_HAS_CPU_XLP
-	bool
-
 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -2150,7 +2064,7 @@ config CPU_SUPPORTS_HUGEPAGES
 config MIPS_PGD_C0_CONTEXT
 	bool
 	depends on 64BIT
-	default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP
+	default y if (CPU_MIPSR2 || CPU_MIPSR6)
 
 #
 # Set to y for ptrace access to watch registers.
@@ -2833,7 +2747,7 @@ config NODES_SHIFT
 
 config HW_PERF_EVENTS
 	bool "Enable hardware performance counter support for perf events"
-	depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64)
+	depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64)
 	default y
 	help
 	  Enable hardware performance counter support for perf events. If

arch/mips/boot/compressed/uart-16550.c

@@ -23,18 +23,6 @@
 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))
 #endif
 
-#ifdef CONFIG_CPU_XLR
-#define UART0_BASE  0x1EF14000
-#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
-#define IOTYPE unsigned int
-#endif
-
-#ifdef CONFIG_CPU_XLP
-#define UART0_BASE  0x18030100
-#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset))
-#define IOTYPE unsigned int
-#endif
-
 #ifndef IOTYPE
 #define IOTYPE char
 #endif

arch/mips/boot/dts/Makefile

@@ -9,7 +9,6 @@ subdir-$(CONFIG_MACH_LOONGSON64)	+= loongson
 subdir-$(CONFIG_SOC_VCOREIII)		+= mscc
 subdir-$(CONFIG_MIPS_MALTA)		+= mti
 subdir-$(CONFIG_LEGACY_BOARD_SEAD3)	+= mti
-subdir-$(CONFIG_NLM_XLP_BOARD)		+= netlogic
 subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445)	+= ni
 subdir-$(CONFIG_MACH_PIC32)		+= pic32
 subdir-$(CONFIG_ATH79)			+= qca

arch/mips/boot/dts/netlogic/Makefile

-# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_DT_XLP_EVP)	+= xlp_evp.dtb
-dtb-$(CONFIG_DT_XLP_SVP)	+= xlp_svp.dtb
-dtb-$(CONFIG_DT_XLP_FVP)	+= xlp_fvp.dtb
-dtb-$(CONFIG_DT_XLP_GVP)	+= xlp_gvp.dtb
-dtb-$(CONFIG_DT_XLP_RVP)	+= xlp_rvp.dtb
-
-obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .o, $(dtb-y))

arch/mips/boot/dts/netlogic/xlp_evp.dts

-// SPDX-License-Identifier: GPL-2.0
-/*
- * XLP8XX Device Tree Source for EVP boards
- */
-
-/dts-v1/;
-/ {
-	model = "netlogic,XLP-EVP";
-	compatible = "netlogic,xlp";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <1>;
-		compatible = "simple-bus";
-		ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
-			  1 0  0 0x16000000  0x02000000>; // GBU chipselects
-
-		serial0: serial@30000 {
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0 0x30100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <133333333>;
-			interrupt-parent = <&pic>;
-			interrupts = <17>;
-		};
-		serial1: serial@31000 {
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0 0x31100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <133333333>;
-			interrupt-parent = <&pic>;
-			interrupts = <18>;
-		};
-		i2c0: ocores@32000 {
-			compatible = "opencores,i2c-ocores";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x32100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <32000000>;
-			interrupt-parent = <&pic>;
-			interrupts = <30>;
-		};
-		i2c1: ocores@33000 {
-			compatible = "opencores,i2c-ocores";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x33100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <32000000>;
-			interrupt-parent = <&pic>;
-			interrupts = <31>;
-
-			rtc@68 {
-				compatible = "dallas,ds1374";
-				reg = <0x68>;
-			};
-
-			dtt@4c {
-				compatible = "national,lm90";
-				reg = <0x4c>;
-			};
-		};
-		pic: pic@4000 {
-			compatible = "netlogic,xlp-pic";
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			reg = <0 0x4000 0x200>;
-			interrupt-controller;
-		};
-
-		nor_flash@1,0 {
-			compatible = "cfi-flash";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			bank-width = <2>;
-			reg = <1 0 0x1000000>;
-
-			partition@0 {
-				label = "x-loader";
-				reg = <0x0 0x100000>; /* 1M */
-				read-only;
-			};
-
-			partition@100000 {
-				label = "u-boot";
-				reg = <0x100000 0x100000>; /* 1M */
-			};
-
-			partition@200000 {
-				label = "kernel";
-				reg = <0x200000 0x500000>; /* 5M */
-			};
-
-			partition@700000 {
-				label = "rootfs";
-				reg = <0x700000 0x800000>; /* 8M */
-			};
-
-			partition@f00000 {
-				label = "env";
-				reg = <0xf00000 0x100000>; /* 1M */
-				read-only;
-			};
-		};
-
-		gpio: xlp_gpio@34100 {
-			compatible = "netlogic,xlp832-gpio";
-			reg = <0 0x34100 0x1000>;
-			#gpio-cells = <2>;
-			gpio-controller;
-
-			#interrupt-cells = <2>;
-			interrupt-parent = <&pic>;
-			interrupts = <39>;
-			interrupt-controller;
-		};
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
-	};
-};

arch/mips/boot/dts/netlogic/xlp_fvp.dts

-// SPDX-License-Identifier: GPL-2.0
-/*
- * XLP2XX Device Tree Source for FVP boards
- */
-
-/dts-v1/;
-/ {
-	model = "netlogic,XLP-FVP";
-	compatible = "netlogic,xlp";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <1>;
-		compatible = "simple-bus";
-		ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
-			  1 0  0 0x16000000  0x02000000>; // GBU chipselects
-
-		serial0: serial@30000 {
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0 0x30100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <133333333>;
-			interrupt-parent = <&pic>;
-			interrupts = <17>;
-		};
-		serial1: serial@31000 {
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0 0x31100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <133333333>;
-			interrupt-parent = <&pic>;
-			interrupts = <18>;
-		};
-		i2c0: ocores@37100 {
-			compatible = "opencores,i2c-ocores";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x37100 0x20>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <32000000>;
-			interrupt-parent = <&pic>;
-			interrupts = <30>;
-		};
-		i2c1: ocores@37120 {
-			compatible = "opencores,i2c-ocores";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x37120 0x20>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <32000000>;
-			interrupt-parent = <&pic>;
-			interrupts = <31>;
-
-			rtc@68 {
-				compatible = "dallas,ds1374";
-				reg = <0x68>;
-			};
-
-			dtt@4c {
-				compatible = "national,lm90";
-				reg = <0x4c>;
-			};
-		};
-		pic: pic@4000 {
-			compatible = "netlogic,xlp-pic";
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			reg = <0 0x4000 0x200>;
-			interrupt-controller;
-		};
-
-		nor_flash@1,0 {
-			compatible = "cfi-flash";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			bank-width = <2>;
-			reg = <1 0 0x1000000>;
-
-			partition@0 {
-				label = "x-loader";
-				reg = <0x0 0x100000>; /* 1M */
-				read-only;
-			};
-
-			partition@100000 {
-				label = "u-boot";
-				reg = <0x100000 0x100000>; /* 1M */
-			};
-
-			partition@200000 {
-				label = "kernel";
-				reg = <0x200000 0x500000>; /* 5M */
-			};
-
-			partition@700000 {
-				label = "rootfs";
-				reg = <0x700000 0x800000>; /* 8M */
-			};
-
-			partition@f00000 {
-				label = "env";
-				reg = <0xf00000 0x100000>; /* 1M */
-				read-only;
-			};
-		};
-
-		gpio: xlp_gpio@34100 {
-			compatible = "netlogic,xlp208-gpio";
-			reg = <0 0x34100 0x1000>;
-			#gpio-cells = <2>;
-			gpio-controller;
-
-			#interrupt-cells = <2>;
-			interrupt-parent = <&pic>;
-			interrupts = <39>;
-			interrupt-controller;
-		};
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
-	};
-};

arch/mips/boot/dts/netlogic/xlp_gvp.dts

-// SPDX-License-Identifier: GPL-2.0
-/*
- * XLP9XX Device Tree Source for GVP boards
- */
-
-/dts-v1/;
-/ {
-	model = "netlogic,XLP-GVP";
-	compatible = "netlogic,xlp";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <1>;
-		compatible = "simple-bus";
-		ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
-			  1 0  0 0x16000000  0x02000000>; // GBU chipselects
-
-		serial0: serial@30000 {
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0 0x112100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <125000000>;
-			interrupt-parent = <&pic>;
-			interrupts = <17>;
-		};
-		pic: pic@110000 {
-			compatible = "netlogic,xlp-pic";
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			reg = <0 0x110000 0x200>;
-			interrupt-controller;
-		};
-
-		nor_flash@1,0 {
-			compatible = "cfi-flash";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			bank-width = <2>;
-			reg = <1 0 0x1000000>;
-
-			partition@0 {
-				label = "x-loader";
-				reg = <0x0 0x100000>; /* 1M */
-				read-only;
-			};
-
-			partition@100000 {
-				label = "u-boot";
-				reg = <0x100000 0x100000>; /* 1M */
-			};
-
-			partition@200000 {
-				label = "kernel";
-				reg = <0x200000 0x500000>; /* 5M */
-			};
-
-			partition@700000 {
-				label = "rootfs";
-				reg = <0x700000 0x800000>; /* 8M */
-			};
-
-			partition@f00000 {
-				label = "env";
-				reg = <0xf00000 0x100000>; /* 1M */
-				read-only;
-			};
-		};
-
-		gpio: xlp_gpio@114100 {
-			compatible = "netlogic,xlp980-gpio";
-			reg = <0 0x114100 0x1000>;
-			#gpio-cells = <2>;
-			gpio-controller;
-
-			#interrupt-cells = <2>;
-			interrupt-parent = <&pic>;
-			interrupts = <39>;
-			interrupt-controller;
-		};
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
-	};
-};

arch/mips/boot/dts/netlogic/xlp_rvp.dts

-// SPDX-License-Identifier: GPL-2.0
-/*
- * XLP5XX Device Tree Source for RVP boards
- */
-
-/dts-v1/;
-/ {
-	model = "netlogic,XLP-RVP";
-	compatible = "netlogic,xlp";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <1>;
-		compatible = "simple-bus";
-		ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
-			  1 0  0 0x16000000  0x02000000>; // GBU chipselects
-
-		serial0: serial@30000 {
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0 0x112100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <125000000>;
-			interrupt-parent = <&pic>;
-			interrupts = <17>;
-		};
-		pic: pic@110000 {
-			compatible = "netlogic,xlp-pic";
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			reg = <0 0x110000 0x200>;
-			interrupt-controller;
-		};
-
-		nor_flash@1,0 {
-			compatible = "cfi-flash";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			bank-width = <2>;
-			reg = <1 0 0x1000000>;
-
-			partition@0 {
-				label = "x-loader";
-				reg = <0x0 0x100000>; /* 1M */
-				read-only;
-			};
-
-			partition@100000 {
-				label = "u-boot";
-				reg = <0x100000 0x100000>; /* 1M */
-			};
-
-			partition@200000 {
-				label = "kernel";
-				reg = <0x200000 0x500000>; /* 5M */
-			};
-
-			partition@700000 {
-				label = "rootfs";
-				reg = <0x700000 0x800000>; /* 8M */
-			};
-
-			partition@f00000 {
-				label = "env";
-				reg = <0xf00000 0x100000>; /* 1M */
-				read-only;
-			};
-		};
-
-		gpio: xlp_gpio@114100 {
-			compatible = "netlogic,xlp532-gpio";
-			reg = <0 0x114100 0x1000>;
-			#gpio-cells = <2>;
-			gpio-controller;
-
-			#interrupt-cells = <2>;
-			interrupt-parent = <&pic>;
-			interrupts = <39>;
-			interrupt-controller;
-		};
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
-	};
-};

arch/mips/boot/dts/netlogic/xlp_svp.dts

-// SPDX-License-Identifier: GPL-2.0
-/*
- * XLP3XX Device Tree Source for SVP boards
- */
-
-/dts-v1/;
-/ {
-	model = "netlogic,XLP-SVP";
-	compatible = "netlogic,xlp";
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <1>;
-		compatible = "simple-bus";
-		ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
-			  1 0  0 0x16000000  0x02000000>; // GBU chipselects
-
-		serial0: serial@30000 {
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0 0x30100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <133333333>;
-			interrupt-parent = <&pic>;
-			interrupts = <17>;
-		};
-		serial1: serial@31000 {
-			device_type = "serial";
-			compatible = "ns16550";
-			reg = <0 0x31100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <133333333>;
-			interrupt-parent = <&pic>;
-			interrupts = <18>;
-		};
-		i2c0: ocores@32000 {
-			compatible = "opencores,i2c-ocores";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x32100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <32000000>;
-			interrupt-parent = <&pic>;
-			interrupts = <30>;
-		};
-		i2c1: ocores@33000 {
-			compatible = "opencores,i2c-ocores";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0 0x33100 0xa00>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <32000000>;
-			interrupt-parent = <&pic>;
-			interrupts = <31>;
-
-			rtc@68 {
-				compatible = "dallas,ds1374";
-				reg = <0x68>;
-			};
-
-			dtt@4c {
-				compatible = "national,lm90";
-				reg = <0x4c>;
-			};
-		};
-		pic: pic@4000 {
-			compatible = "netlogic,xlp-pic";
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			reg = <0 0x4000 0x200>;
-			interrupt-controller;
-		};
-
-		nor_flash@1,0 {
-			compatible = "cfi-flash";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			bank-width = <2>;
-			reg = <1 0 0x1000000>;
-
-			partition@0 {
-				label = "x-loader";
-				reg = <0x0 0x100000>; /* 1M */
-				read-only;
-			};
-
-			partition@100000 {
-				label = "u-boot";
-				reg = <0x100000 0x100000>; /* 1M */
-			};
-
-			partition@200000 {
-				label = "kernel";
-				reg = <0x200000 0x500000>; /* 5M */
-			};
-
-			partition@700000 {
-				label = "rootfs";
-				reg = <0x700000 0x800000>; /* 8M */
-			};
-
-			partition@f00000 {
-				label = "env";
-				reg = <0xf00000 0x100000>; /* 1M */
-				read-only;
-			};
-		};
-
-		gpio: xlp_gpio@34100 {
-			compatible = "netlogic,xlp316-gpio";
-			reg = <0 0x34100 0x1000>;
-			#gpio-cells = <2>;
-			gpio-controller;
-
-			#interrupt-cells = <2>;
-			interrupt-parent = <&pic>;
-			interrupts = <39>;
-			interrupt-controller;
-		};
-	};
-
-	chosen {
-		bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
-	};
-};

arch/mips/cavium-octeon/executive/cvmx-helper.c

@@ -1055,16 +1055,6 @@ int cvmx_helper_initialize_packet_io_global(void)
 }
 EXPORT_SYMBOL_GPL(cvmx_helper_initialize_packet_io_global);
 
-/**
- * Does core local initialization for packet io
- *
- * Returns Zero on success, non-zero on failure
- */
-int cvmx_helper_initialize_packet_io_local(void)
-{
-	return cvmx_pko_initialize_local();
-}
-
 /**
  * Return the link state of an IPD/PKO port as returned by
  * auto negotiation. The result of this function may not match

arch/mips/cavium-octeon/executive/cvmx-pko.c

@@ -229,20 +229,6 @@ void cvmx_pko_initialize_global(void)
 	}
 }
 
-/*
- * This function does per-core initialization required by the PKO routines.
- * This must be called on all cores that will do packet output, and must
- * be called after the FPA has been initialized and filled with pages.
- *
- * Returns 0 on success
- *	   !0 on failure
- */
-int cvmx_pko_initialize_local(void)
-{
-	/* Nothing to do */
-	return 0;
-}
-
 /*
  * Enables the packet output hardware. It must already be
  * configured.

arch/mips/configs/loongson3_defconfig

@@ -282,6 +282,7 @@ CONFIG_DRM=y
 CONFIG_DRM_RADEON=m
 CONFIG_DRM_QXL=y
 CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_FB=y
 CONFIG_FB_RADEON=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_PLATFORM=m

arch/mips/include/asm/cmpxchg.h

@@ -249,6 +249,7 @@ static inline unsigned long __cmpxchg64(volatile void *ptr,
 	/* Load 64 bits from ptr */
 	"	" __SYNC(full, loongson3_war) "		\n"
 	"1:	lld	%L0, %3		# __cmpxchg64	\n"
+	"	.set	pop				\n"
 	/*
 	 * Split the 64 bit value we loaded into the 2 registers that hold the
 	 * ret variable.
@@ -276,12 +277,14 @@ static inline unsigned long __cmpxchg64(volatile void *ptr,
 	"	or	%L1, %L1, $at			\n"
 	"	.set	at				\n"
 #  endif
+	"	.set	push				\n"
+	"	.set	" MIPS_ISA_ARCH_LEVEL "		\n"
 	/* Attempt to store new at ptr */
 	"	scd	%L1, %2				\n"
 	/* If we failed, loop! */
 	"\t" __SC_BEQZ "%L1, 1b				\n"
-	"	.set	pop				\n"
 	"2:	" __SYNC(full, loongson3_war) "		\n"
+	"	.set	pop				\n"
 	: "=&r"(ret),
 	  "=&r"(tmp),
 	  "=" GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr)

arch/mips/include/asm/cop2.h

@@ -22,17 +22,6 @@ extern void octeon_cop2_restore(struct octeon_cop2_state *);
 #define cop2_present		1
 #define cop2_lazy_restore	1
 
-#elif defined(CONFIG_CPU_XLP)
-
-extern void nlm_cop2_save(struct nlm_cop2_state *);
-extern void nlm_cop2_restore(struct nlm_cop2_state *);
-
-#define cop2_save(r)		nlm_cop2_save(&(r)->thread.cp2)
-#define cop2_restore(r)		nlm_cop2_restore(&(r)->thread.cp2)
-
-#define cop2_present		1
-#define cop2_lazy_restore	0
-
 #elif defined(CONFIG_CPU_LOONGSON64)
 
 #define cop2_present		1

arch/mips/include/asm/cpu-type.h

@@ -195,14 +195,6 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 #ifdef CONFIG_SYS_HAS_CPU_BMIPS5000
 	case CPU_BMIPS5000:
 #endif
-
-#ifdef CONFIG_SYS_HAS_CPU_XLP
-	case CPU_XLP:
-#endif
-
-#ifdef CONFIG_SYS_HAS_CPU_XLR
-	case CPU_XLR:
-#endif
 		break;
 	default:
 		unreachable();

arch/mips/include/asm/cpu.h

@@ -328,7 +328,7 @@ enum cpu_type_enum {
 	 */
 	CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF,
 	CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
-	CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
+	CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_I6500,
 
 	CPU_QEMU_GENERIC,
 

arch/mips/include/asm/ginvt.h

@@ -12,11 +12,13 @@ enum ginvt_type {
 
 #ifdef TOOLCHAIN_SUPPORTS_GINV
 # define _ASM_SET_GINV	".set	ginv\n"
+# define _ASM_UNSET_GINV
 #else
-_ASM_MACRO_1R1I(ginvt, rs, type,
-		_ASM_INSN_IF_MIPS(0x7c0000bd | (__rs << 21) | (\\type << 8))
-		_ASM_INSN32_IF_MM(0x0000717c | (__rs << 16) | (\\type << 9)));
-# define _ASM_SET_GINV
+# define _ASM_SET_GINV							\
+	_ASM_MACRO_1R1I(ginvt, rs, type,				\
+			_ASM_INSN_IF_MIPS(0x7c0000bd | (__rs << 21) | (\\type << 8))	\
+			_ASM_INSN32_IF_MM(0x0000717c | (__rs << 16) | (\\type << 9)))
+# define _ASM_UNSET_GINV ".purgem ginvt\n"
 #endif
 
 static __always_inline void ginvt(unsigned long addr, enum ginvt_type type)
@@ -25,6 +27,7 @@ static __always_inline void ginvt(unsigned long addr, enum ginvt_type type)
 		".set	push\n"
 		_ASM_SET_GINV
 		"	ginvt	%0, %1\n"
+		_ASM_UNSET_GINV
 		".set	pop"
 		: /* no outputs */
 		: "r"(addr), "i"(type)

arch/mips/include/asm/hazards.h

@@ -160,7 +160,7 @@ do {									\
 
 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
 	defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \
-	defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
+	defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.

arch/mips/include/asm/mach-loongson64/loongson_regs.h

@@ -21,8 +21,10 @@ static inline u32 read_cpucfg(u32 reg)
 	u32 __res;
 
 	__asm__ __volatile__(
+		_ASM_SET_PARSE_R
 		"parse_r __res,%0\n\t"
 		"parse_r reg,%1\n\t"
+		_ASM_UNSET_PARSE_R
 		".insn \n\t"
 		".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t"
 		:"=r"(__res)
@@ -143,8 +145,10 @@ static inline u32 csr_readl(u32 reg)
 
 	/* RDCSR reg, val */
 	__asm__ __volatile__(
+		_ASM_SET_PARSE_R
 		"parse_r __res,%0\n\t"
 		"parse_r reg,%1\n\t"
+		_ASM_UNSET_PARSE_R
 		".insn \n\t"
 		".word (0xc8000118 | (reg << 21) | (__res << 11))\n\t"
 		:"=r"(__res)
@@ -160,8 +164,10 @@ static inline u64 csr_readq(u32 reg)
 
 	/* DRDCSR reg, val */
 	__asm__ __volatile__(
+		_ASM_SET_PARSE_R
 		"parse_r __res,%0\n\t"
 		"parse_r reg,%1\n\t"
+		_ASM_UNSET_PARSE_R
 		".insn \n\t"
 		".word (0xc8020118 | (reg << 21) | (__res << 11))\n\t"
 		:"=r"(__res)
@@ -175,8 +181,10 @@ static inline void csr_writel(u32 val, u32 reg)
 {
 	/* WRCSR reg, val */
 	__asm__ __volatile__(
+		_ASM_SET_PARSE_R
 		"parse_r reg,%0\n\t"
 		"parse_r val,%1\n\t"
+		_ASM_UNSET_PARSE_R
 		".insn \n\t"
 		".word (0xc8010118 | (reg << 21) | (val << 11))\n\t"
 		:
@@ -189,8 +197,10 @@ static inline void csr_writeq(u64 val, u32 reg)
 {
 	/* DWRCSR reg, val */
 	__asm__ __volatile__(
+		_ASM_SET_PARSE_R
 		"parse_r reg,%0\n\t"
 		"parse_r val,%1\n\t"
+		_ASM_UNSET_PARSE_R
 		".insn \n\t"
 		".word (0xc8030118 | (reg << 21) | (val << 11))\n\t"
 		:
@@ -243,8 +253,10 @@ static inline u64 drdtime(void)
 	u64 val = 0;
 
 	__asm__ __volatile__(
+		_ASM_SET_PARSE_R
 		"parse_r rID,%0\n\t"
 		"parse_r val,%1\n\t"
+		_ASM_UNSET_PARSE_R
 		".insn \n\t"
 		".word (0xc8090118 | (rID << 21) | (val << 11))\n\t"
 		:"=r"(rID),"=r"(val)

arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h

-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2011 Netlogic Microsystems
- * Copyright (C) 2003 Ralf Baechle
- */
-#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H
-
-#define cpu_has_4kex		1
-#define cpu_has_4k_cache	1
-#define cpu_has_watch		1
-#define cpu_has_mips16		0
-#define cpu_has_mips16e2	0
-#define cpu_has_counter		1
-#define cpu_has_divec		1
-#define cpu_has_vce		0
-#define cpu_has_cache_cdex_p	0
-#define cpu_has_cache_cdex_s	0
-#define cpu_has_prefetch	1
-#define cpu_has_mcheck		1
-#define cpu_has_ejtag		1
-
-#define cpu_has_llsc		1
-#define cpu_has_vtag_icache	0
-#define cpu_has_ic_fills_f_dc	1
-#define cpu_has_dsp		0
-#define cpu_has_dsp2		0
-#define cpu_has_mipsmt		0
-#define cpu_icache_snoops_remote_store	1
-
-#define cpu_has_64bits		1
-
-#define cpu_has_mips32r1	1
-#define cpu_has_mips64r1	1
-
-#define cpu_has_inclusive_pcaches	0
-
-#define cpu_dcache_line_size()	32
-#define cpu_icache_line_size()	32
-
-#if defined(CONFIG_CPU_XLR)
-#define cpu_has_userlocal	0
-#define cpu_has_dc_aliases	0
-#define cpu_has_mips32r2	0
-#define cpu_has_mips64r2	0
-#elif defined(CONFIG_CPU_XLP)
-#define cpu_has_userlocal	1
-#define cpu_has_mips32r2	1
-#define cpu_has_mips64r2	1
-#else
-#error "Unknown Netlogic CPU"
-#endif
-
-#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */

arch/mips/include/asm/mach-netlogic/irq.h

-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2011 Netlogic Microsystems.
- */
-#ifndef __ASM_NETLOGIC_IRQ_H
-#define __ASM_NETLOGIC_IRQ_H
-
-#include <asm/mach-netlogic/multi-node.h>
-#define NLM_IRQS_PER_NODE	1024
-#define NR_IRQS			(NLM_IRQS_PER_NODE * NLM_NR_NODES)
-
-#define MIPS_CPU_IRQ_BASE	0
-
-#endif /* __ASM_NETLOGIC_IRQ_H */

arch/mips/include/asm/mach-netlogic/multi-node.h

-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NETLOGIC_MULTI_NODE_H_
-#define _NETLOGIC_MULTI_NODE_H_
-
-#ifndef CONFIG_NLM_MULTINODE
-#define NLM_NR_NODES		1
-#else
-#if defined(CONFIG_NLM_MULTINODE_2)
-#define NLM_NR_NODES		2
-#elif defined(CONFIG_NLM_MULTINODE_4)
-#define NLM_NR_NODES		4
-#else
-#define NLM_NR_NODES		1
-#endif
-#endif
-
-#define NLM_THREADS_PER_CORE	4
-
-struct nlm_soc_info {
-	unsigned long	coremask;	/* cores enabled on the soc */
-	unsigned long	ebase;		/* not used now */
-	uint64_t	irqmask;	/* EIMR for the node */
-	uint64_t	sysbase;	/* only for XLP - sys block base */
-	uint64_t	picbase;	/* PIC block base */
-	spinlock_t	piclock;	/* lock for PIC access */
-	cpumask_t	cpumask;	/* logical cpu mask for node */
-	unsigned int	socbus;
-};
-
-extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
-#define nlm_get_node(i)		(&nlm_nodes[i])
-#define nlm_node_present(n)	((n) >= 0 && (n) < NLM_NR_NODES && \
-					nlm_get_node(n)->coremask != 0)
-#ifdef CONFIG_CPU_XLR
-#define nlm_current_node()	(&nlm_nodes[0])
-#else
-#define nlm_current_node()	(&nlm_nodes[nlm_nodeid()])
-#endif
-void nlm_node_init(int node);
-
-#endif

arch/mips/include/asm/mips-cm.h

@@ -11,6 +11,7 @@
 #ifndef __MIPS_ASM_MIPS_CM_H__
 #define __MIPS_ASM_MIPS_CM_H__
 
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/errno.h>
 
@@ -153,8 +154,8 @@ GCR_ACCESSOR_RO(32, 0x030, rev)
 #define CM_GCR_REV_MINOR			GENMASK(7, 0)
 
 #define CM_ENCODE_REV(major, minor) \
-		(((major) << __ffs(CM_GCR_REV_MAJOR)) | \
-		 ((minor) << __ffs(CM_GCR_REV_MINOR)))
+		(FIELD_PREP(CM_GCR_REV_MAJOR, major) | \
+		 FIELD_PREP(CM_GCR_REV_MINOR, minor))
 
 #define CM_REV_CM2				CM_ENCODE_REV(6, 0)
 #define CM_REV_CM2_5				CM_ENCODE_REV(7, 0)
@@ -362,10 +363,10 @@ static inline int mips_cm_revision(void)
 static inline unsigned int mips_cm_max_vp_width(void)
 {
 	extern int smp_num_siblings;
-	uint32_t cfg;
 
 	if (mips_cm_revision() >= CM_REV_CM3)
-		return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW;
+		return FIELD_GET(CM_GCR_SYS_CONFIG2_MAXVPW,
+				 read_gcr_sys_config2());
 
 	if (mips_cm_present()) {
 		/*
@@ -373,8 +374,7 @@ static inline unsigned int mips_cm_max_vp_width(void)
 		 * number of VP(E)s, and if that ever changes then this will
 		 * need revisiting.
 		 */
-		cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE;
-		return (cfg >> __ffs(CM_GCR_Cx_CONFIG_PVPE)) + 1;
+		return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, read_gcr_cl_config()) + 1;
 	}
 
 	if (IS_ENABLED(CONFIG_SMP))

arch/mips/include/asm/msa.h

@@ -162,16 +162,26 @@ static inline void init_msa_upper(void)
  * to allow compilation with toolchains that do not support MSA. Once all
  * toolchains in use support MSA these can be removed.
  */
-_ASM_MACRO_2R(cfcmsa, rd, cs,
-	_ASM_INSN_IF_MIPS(0x787e0019 | __cs << 11 | __rd << 6)
-	_ASM_INSN32_IF_MM(0x587e0016 | __cs << 11 | __rd << 6));
-_ASM_MACRO_2R(ctcmsa, cd, rs,
-	_ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6)
-	_ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6));
-#define _ASM_SET_MSA ""
+
+#define _ASM_SET_CFCMSA							\
+	_ASM_MACRO_2R(cfcmsa, rd, cs,					\
+		      _ASM_INSN_IF_MIPS(0x787e0019 | __cs << 11 | __rd << 6)	\
+		      _ASM_INSN32_IF_MM(0x587e0016 | __cs << 11 | __rd << 6))
+#define _ASM_UNSET_CFCMSA ".purgem cfcmsa\n\t"
+#define _ASM_SET_CTCMSA							\
+	_ASM_MACRO_2R(ctcmsa, cd, rs,					\
+		      _ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6)	\
+		      _ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6))
+#define _ASM_UNSET_CTCMSA ".purgem ctcmsa\n\t"
 #else /* TOOLCHAIN_SUPPORTS_MSA */
-#define _ASM_SET_MSA ".set\tfp=64\n\t"				\
-		     ".set\tmsa\n\t"
+#define _ASM_SET_CFCMSA						\
+		".set\tfp=64\n\t"				\
+		".set\tmsa\n\t"
+#define _ASM_UNSET_CFCMSA
+#define _ASM_SET_CTCMSA						\
+		".set\tfp=64\n\t"				\
+		".set\tmsa\n\t"
+#define _ASM_UNSET_CTCMSA
 #endif
 
 #define __BUILD_MSA_CTL_REG(name, cs)				\
@@ -180,8 +190,9 @@ static inline unsigned int read_msa_##name(void)		\
 	unsigned int reg;					\
 	__asm__ __volatile__(					\
 	"	.set	push\n"					\
-	_ASM_SET_MSA						\
+	_ASM_SET_CFCMSA						\
 	"	cfcmsa	%0, $" #cs "\n"				\
+	_ASM_UNSET_CFCMSA					\
 	"	.set	pop\n"					\
 	: "=r"(reg));						\
 	return reg;						\
@@ -191,8 +202,9 @@ static inline void write_msa_##name(unsigned int val)		\
 {								\
 	__asm__ __volatile__(					\
 	"	.set	push\n"					\
-	_ASM_SET_MSA						\
+	_ASM_SET_CTCMSA						\
 	"	ctcmsa	$" #cs ", %0\n"				\
+	_ASM_UNSET_CTCMSA					\
 	"	.set	pop\n"					\
 	: : "r"(val));						\
 }

arch/mips/include/asm/netlogic/common.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NETLOGIC_COMMON_H_
-#define _NETLOGIC_COMMON_H_
-
-/*
- * Common SMP definitions
- */
-#define RESET_VEC_PHYS		0x1fc00000
-#define RESET_VEC_SIZE		8192		/* 8KB reset code and data */
-#define RESET_DATA_PHYS		(RESET_VEC_PHYS + (1<<10))
-
-/* Offsets of parameters in the RESET_DATA_PHYS area */
-#define BOOT_THREAD_MODE	0
-#define BOOT_NMI_LOCK		4
-#define BOOT_NMI_HANDLER	8
-
-/* CPU ready flags for each CPU */
-#define BOOT_CPU_READY		2048
-
-#ifndef __ASSEMBLY__
-#include <linux/cpumask.h>
-#include <linux/spinlock.h>
-#include <asm/irq.h>
-#include <asm/mach-netlogic/multi-node.h>
-
-struct irq_desc;
-void nlm_smp_function_ipi_handler(struct irq_desc *desc);
-void nlm_smp_resched_ipi_handler(struct irq_desc *desc);
-void nlm_smp_irq_init(int hwcpuid);
-void nlm_boot_secondary_cpus(void);
-int nlm_wakeup_secondary_cpus(void);
-void nlm_rmiboot_preboot(void);
-void nlm_percpu_init(int hwcpuid);
-
-static inline void *
-nlm_get_boot_data(int offset)
-{
-	return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset);
-}
-
-static inline void
-nlm_set_nmi_handler(void *handler)
-{
-	void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER);
-
-	*(int64_t *)nmih = (long)handler;
-}
-
-/*
- * Misc.
- */
-void nlm_init_boot_cpu(void);
-unsigned int nlm_get_cpu_frequency(void);
-extern const struct plat_smp_ops nlm_smp_ops;
-extern char nlm_reset_entry[], nlm_reset_entry_end[];
-
-extern unsigned int nlm_threads_per_core;
-extern cpumask_t nlm_cpumask;
-
-struct irq_data;
-uint64_t nlm_pci_irqmask(int node);
-void nlm_setup_pic_irq(int node, int picirq, int irq, int irt);
-void nlm_set_pic_extra_ack(int node, int irq,  void (*xack)(struct irq_data *));
-
-#ifdef CONFIG_PCI_MSI
-void nlm_dispatch_msi(int node, int lirq);
-void nlm_dispatch_msix(int node, int msixirq);
-#endif
-
-/*
- * The NR_IRQs is divided between nodes, each of them has a separate irq space
- */
-static inline int nlm_irq_to_xirq(int node, int irq)
-{
-	return node * NR_IRQS / NLM_NR_NODES + irq;
-}
-
-#ifdef CONFIG_CPU_XLR
-#define nlm_cores_per_node()	8
-#else
-static inline int nlm_cores_per_node(void)
-{
-	return ((read_c0_prid() & PRID_IMP_MASK)
-				== PRID_IMP_NETLOGIC_XLP9XX) ? 32 : 8;
-}
-#endif
-static inline int nlm_threads_per_node(void)
-{
-	return nlm_cores_per_node() * NLM_THREADS_PER_CORE;
-}
-
-static inline int nlm_hwtid_to_node(int hwtid)
-{
-	return hwtid / nlm_threads_per_node();
-}
-
-extern int nlm_cpu_ready[];
-#endif /* __ASSEMBLY__ */
-#endif /* _NETLOGIC_COMMON_H_ */

arch/mips/include/asm/netlogic/haldefs.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_HALDEFS_H__
-#define __NLM_HAL_HALDEFS_H__
-
-#include <linux/irqflags.h>	/* for local_irq_disable */
-
-/*
- * This file contains platform specific memory mapped IO implementation
- * and will provide a way to read 32/64 bit memory mapped registers in
- * all ABIs
- */
-static inline uint32_t
-nlm_read_reg(uint64_t base, uint32_t reg)
-{
-	volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
-
-	return *addr;
-}
-
-static inline void
-nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
-{
-	volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
-
-	*addr = val;
-}
-
-/*
- * For o32 compilation, we have to disable interrupts to access 64 bit
- * registers
- *
- * We need to disable interrupts because we save just the lower 32 bits of
- * registers in  interrupt handling. So if we get hit by an interrupt while
- * using the upper 32 bits of a register, we lose.
- */
-
-static inline uint64_t
-nlm_read_reg64(uint64_t base, uint32_t reg)
-{
-	uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
-	volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
-	uint64_t val;
-
-	if (sizeof(unsigned long) == 4) {
-		unsigned long flags;
-
-		local_irq_save(flags);
-		__asm__ __volatile__(
-			".set	push"			"\n\t"
-			".set	mips64"			"\n\t"
-			"ld	%L0, %1"		"\n\t"
-			"dsra32	%M0, %L0, 0"		"\n\t"
-			"sll	%L0, %L0, 0"		"\n\t"
-			".set	pop"			"\n"
-			: "=r" (val)
-			: "m" (*ptr));
-		local_irq_restore(flags);
-	} else
-		val = *ptr;
-
-	return val;
-}
-
-static inline void
-nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
-{
-	uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
-	volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
-
-	if (sizeof(unsigned long) == 4) {
-		unsigned long flags;
-		uint64_t tmp;
-
-		local_irq_save(flags);
-		__asm__ __volatile__(
-			".set	push"			"\n\t"
-			".set	mips64"			"\n\t"
-			"dsll32	%L0, %L0, 0"		"\n\t"
-			"dsrl32	%L0, %L0, 0"		"\n\t"
-			"dsll32	%M0, %M0, 0"		"\n\t"
-			"or	%L0, %L0, %M0"		"\n\t"
-			"sd	%L0, %2"		"\n\t"
-			".set	pop"			"\n"
-			: "=r" (tmp)
-			: "0" (val), "m" (*ptr));
-		local_irq_restore(flags);
-	} else
-		*ptr = val;
-}
-
-/*
- * Routines to store 32/64 bit values to 64 bit addresses,
- * used when going thru XKPHYS to access registers
- */
-static inline uint32_t
-nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
-{
-	return nlm_read_reg(base, reg);
-}
-
-static inline void
-nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
-{
-	nlm_write_reg(base, reg, val);
-}
-
-static inline uint64_t
-nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
-{
-	return nlm_read_reg64(base, reg);
-}
-
-static inline void
-nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
-{
-	nlm_write_reg64(base, reg, val);
-}
-
-/* Location where IO base is mapped */
-extern uint64_t nlm_io_base;
-
-#if defined(CONFIG_CPU_XLP)
-static inline uint64_t
-nlm_pcicfg_base(uint32_t devoffset)
-{
-	return nlm_io_base + devoffset;
-}
-
-#elif defined(CONFIG_CPU_XLR)
-
-static inline uint64_t
-nlm_mmio_base(uint32_t devoffset)
-{
-	return nlm_io_base + devoffset;
-}
-#endif
-
-#endif

arch/mips/include/asm/netlogic/interrupt.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_NLM_INTERRUPT_H
-#define _ASM_NLM_INTERRUPT_H
-
-/* Defines for the IRQ numbers */
-
-#define IRQ_IPI_SMP_FUNCTION	3
-#define IRQ_IPI_SMP_RESCHEDULE	4
-#define IRQ_FMN			5
-#define IRQ_TIMER		7
-
-#endif

arch/mips/include/asm/netlogic/mips-extns.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_NLM_MIPS_EXTS_H
-#define _ASM_NLM_MIPS_EXTS_H
-
-/*
- * XLR and XLP interrupt request and interrupt mask registers
- */
-/*
- * NOTE: Do not save/restore flags around write_c0_eimr().
- * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS
- * register. Restoring flags will overwrite the lower 8 bits of EIMR.
- *
- * Call with interrupts disabled.
- */
-#define write_c0_eimr(val)						\
-do {									\
-	if (sizeof(unsigned long) == 4) {				\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
-			"or\t%L0, %L0, %M0\n\t"				\
-			"dmtc0\t%L0, $9, 7\n\t"				\
-			".set\tmips0"					\
-			: : "r" (val));					\
-	} else								\
-		__write_64bit_c0_register($9, 7, (val));		\
-} while (0)
-
-/*
- * Handling the 64 bit EIMR and EIRR registers in 32-bit mode with
- * standard functions will be very inefficient. This provides
- * optimized functions for the normal operations on the registers.
- *
- * Call with interrupts disabled.
- */
-static inline void ack_c0_eirr(int irq)
-{
-	__asm__ __volatile__(
-		".set	push\n\t"
-		".set	mips64\n\t"
-		".set	noat\n\t"
-		"li	$1, 1\n\t"
-		"dsllv	$1, $1, %0\n\t"
-		"dmtc0	$1, $9, 6\n\t"
-		".set	pop"
-		: : "r" (irq));
-}
-
-static inline void set_c0_eimr(int irq)
-{
-	__asm__ __volatile__(
-		".set	push\n\t"
-		".set	mips64\n\t"
-		".set	noat\n\t"
-		"li	$1, 1\n\t"
-		"dsllv	%0, $1, %0\n\t"
-		"dmfc0	$1, $9, 7\n\t"
-		"or	$1, %0\n\t"
-		"dmtc0	$1, $9, 7\n\t"
-		".set	pop"
-		: "+r" (irq));
-}
-
-static inline void clear_c0_eimr(int irq)
-{
-	__asm__ __volatile__(
-		".set	push\n\t"
-		".set	mips64\n\t"
-		".set	noat\n\t"
-		"li	$1, 1\n\t"
-		"dsllv	%0, $1, %0\n\t"
-		"dmfc0	$1, $9, 7\n\t"
-		"or	$1, %0\n\t"
-		"xor	$1, %0\n\t"
-		"dmtc0	$1, $9, 7\n\t"
-		".set	pop"
-		: "+r" (irq));
-}
-
-/*
- * Read c0 eimr and c0 eirr, do AND of the two values, the result is
- * the interrupts which are raised and are not masked.
- */
-static inline uint64_t read_c0_eirr_and_eimr(void)
-{
-	uint64_t val;
-
-#ifdef CONFIG_64BIT
-	val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7);
-#else
-	__asm__ __volatile__(
-		".set	push\n\t"
-		".set	mips64\n\t"
-		".set	noat\n\t"
-		"dmfc0	%M0, $9, 6\n\t"
-		"dmfc0	%L0, $9, 7\n\t"
-		"and	%M0, %L0\n\t"
-		"dsll	%L0, %M0, 32\n\t"
-		"dsra	%M0, %M0, 32\n\t"
-		"dsra	%L0, %L0, 32\n\t"
-		".set	pop"
-		: "=r" (val));
-#endif
-	return val;
-}
-
-static inline int hard_smp_processor_id(void)
-{
-	return __read_32bit_c0_register($15, 1) & 0x3ff;
-}
-
-static inline int nlm_nodeid(void)
-{
-	uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
-
-	if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
-			(prid == PRID_IMP_NETLOGIC_XLP5XX))
-		return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
-	else
-		return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
-}
-
-static inline unsigned int nlm_core_id(void)
-{
-	uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
-
-	if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
-			(prid == PRID_IMP_NETLOGIC_XLP5XX))
-		return (read_c0_ebase() & 0x7c) >> 2;
-	else
-		return (read_c0_ebase() & 0x1c) >> 2;
-}
-
-static inline unsigned int nlm_thread_id(void)
-{
-	return read_c0_ebase() & 0x3;
-}
-
-#define __read_64bit_c2_split(source, sel)				\
-({									\
-	unsigned long long __val;					\
-	unsigned long __flags;						\
-									\
-	local_irq_save(__flags);					\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc2\t%M0, " #source "\n\t"			\
-			"dsll\t%L0, %M0, 32\n\t"			\
-			"dsra\t%M0, %M0, 32\n\t"			\
-			"dsra\t%L0, %L0, 32\n\t"			\
-			".set\tmips0\n\t"				\
-			: "=r" (__val));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc2\t%M0, " #source ", " #sel "\n\t"		\
-			"dsll\t%L0, %M0, 32\n\t"			\
-			"dsra\t%M0, %M0, 32\n\t"			\
-			"dsra\t%L0, %L0, 32\n\t"			\
-			".set\tmips0\n\t"				\
-			: "=r" (__val));				\
-	local_irq_restore(__flags);					\
-									\
-	__val;								\
-})
-
-#define __write_64bit_c2_split(source, sel, val)			\
-do {									\
-	unsigned long __flags;						\
-									\
-	local_irq_save(__flags);					\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
-			"or\t%L0, %L0, %M0\n\t"				\
-			"dmtc2\t%L0, " #source "\n\t"			\
-			".set\tmips0\n\t"				\
-			: : "r" (val));					\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
-			"or\t%L0, %L0, %M0\n\t"				\
-			"dmtc2\t%L0, " #source ", " #sel "\n\t"		\
-			".set\tmips0\n\t"				\
-			: : "r" (val));					\
-	local_irq_restore(__flags);					\
-} while (0)
-
-#define __read_32bit_c2_register(source, sel)				\
-({ uint32_t __res;							\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mfc2\t%0, " #source "\n\t"			\
-			".set\tmips0\n\t"				\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mfc2\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0\n\t"				\
-			: "=r" (__res));				\
-	__res;								\
-})
-
-#define __read_64bit_c2_register(source, sel)				\
-({ unsigned long long __res;						\
-	if (sizeof(unsigned long) == 4)					\
-		__res = __read_64bit_c2_split(source, sel);		\
-	else if (sel == 0)						\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc2\t%0, " #source "\n\t"			\
-			".set\tmips0\n\t"				\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc2\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0\n\t"				\
-			: "=r" (__res));				\
-	__res;								\
-})
-
-#define __write_64bit_c2_register(register, sel, value)			\
-do {									\
-	if (sizeof(unsigned long) == 4)					\
-		__write_64bit_c2_split(register, sel, value);		\
-	else if (sel == 0)						\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmtc2\t%z0, " #register "\n\t"			\
-			".set\tmips0\n\t"				\
-			: : "Jr" (value));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmtc2\t%z0, " #register ", " #sel "\n\t"	\
-			".set\tmips0\n\t"				\
-			: : "Jr" (value));				\
-} while (0)
-
-#define __write_32bit_c2_register(reg, sel, value)			\
-({									\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mtc2\t%z0, " #reg "\n\t"			\
-			".set\tmips0\n\t"				\
-			: : "Jr" (value));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mtc2\t%z0, " #reg ", " #sel "\n\t"		\
-			".set\tmips0\n\t"				\
-			: : "Jr" (value));				\
-})
-
-#endif /*_ASM_NLM_MIPS_EXTS_H */

arch/mips/include/asm/netlogic/psb-bootinfo.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ASM_NETLOGIC_BOOTINFO_H
-#define _ASM_NETLOGIC_BOOTINFO_H
-
-struct psb_info {
-	uint64_t boot_level;
-	uint64_t io_base;
-	uint64_t output_device;
-	uint64_t uart_print;
-	uint64_t led_output;
-	uint64_t init;
-	uint64_t exit;
-	uint64_t warm_reset;
-	uint64_t wakeup;
-	uint64_t online_cpu_map;
-	uint64_t master_reentry_sp;
-	uint64_t master_reentry_gp;
-	uint64_t master_reentry_fn;
-	uint64_t slave_reentry_fn;
-	uint64_t magic_dword;
-	uint64_t uart_putchar;
-	uint64_t size;
-	uint64_t uart_getchar;
-	uint64_t nmi_handler;
-	uint64_t psb_version;
-	uint64_t mac_addr;
-	uint64_t cpu_frequency;
-	uint64_t board_version;
-	uint64_t malloc;
-	uint64_t free;
-	uint64_t global_shmem_addr;
-	uint64_t global_shmem_size;
-	uint64_t psb_os_cpu_map;
-	uint64_t userapp_cpu_map;
-	uint64_t wakeup_os;
-	uint64_t psb_mem_map;
-	uint64_t board_major_version;
-	uint64_t board_minor_version;
-	uint64_t board_manf_revision;
-	uint64_t board_serial_number;
-	uint64_t psb_physaddr_map;
-	uint64_t xlr_loaderip_config;
-	uint64_t bldr_envp;
-	uint64_t avail_mem_map;
-};
-
-/* This is what netlboot passes and linux boot_mem_map is subtly different */
-#define NLM_BOOT_MEM_MAP_MAX	32
-struct nlm_boot_mem_map {
-	int nr_map;
-	struct nlm_boot_mem_map_entry {
-		uint64_t addr;		/* start of memory segment */
-		uint64_t size;		/* size of memory segment */
-		uint32_t type;		/* type of memory segment */
-	} map[NLM_BOOT_MEM_MAP_MAX];
-};
-#define NLM_BOOT_MEM_RAM	1
-
-/* Pointer to saved boot loader info */
-extern struct psb_info nlm_prom_info;
-
-#endif

arch/mips/include/asm/netlogic/xlp-hal/bridge.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_BRIDGE_H__
-#define __NLM_HAL_BRIDGE_H__
-
-/**
-* @file_name mio.h
-* @author Netlogic Microsystems
-* @brief Basic definitions of XLP memory and io subsystem
-*/
-
-/*
- * BRIDGE specific registers
- *
- * These registers start after the PCIe header, which has 0x40
- * standard entries
- */
-#define BRIDGE_MODE			0x00
-#define BRIDGE_PCI_CFG_BASE		0x01
-#define BRIDGE_PCI_CFG_LIMIT		0x02
-#define BRIDGE_PCIE_CFG_BASE		0x03
-#define BRIDGE_PCIE_CFG_LIMIT		0x04
-#define BRIDGE_BUSNUM_BAR0		0x05
-#define BRIDGE_BUSNUM_BAR1		0x06
-#define BRIDGE_BUSNUM_BAR2		0x07
-#define BRIDGE_BUSNUM_BAR3		0x08
-#define BRIDGE_BUSNUM_BAR4		0x09
-#define BRIDGE_BUSNUM_BAR5		0x0a
-#define BRIDGE_BUSNUM_BAR6		0x0b
-#define BRIDGE_FLASH_BAR0		0x0c
-#define BRIDGE_FLASH_BAR1		0x0d
-#define BRIDGE_FLASH_BAR2		0x0e
-#define BRIDGE_FLASH_BAR3		0x0f
-#define BRIDGE_FLASH_LIMIT0		0x10
-#define BRIDGE_FLASH_LIMIT1		0x11
-#define BRIDGE_FLASH_LIMIT2		0x12
-#define BRIDGE_FLASH_LIMIT3		0x13
-
-#define BRIDGE_DRAM_BAR(i)		(0x14 + (i))
-#define BRIDGE_DRAM_LIMIT(i)		(0x1c + (i))
-#define BRIDGE_DRAM_NODE_TRANSLN(i)	(0x24 + (i))
-#define BRIDGE_DRAM_CHNL_TRANSLN(i)	(0x2c + (i))
-
-#define BRIDGE_PCIEMEM_BASE0		0x34
-#define BRIDGE_PCIEMEM_BASE1		0x35
-#define BRIDGE_PCIEMEM_BASE2		0x36
-#define BRIDGE_PCIEMEM_BASE3		0x37
-#define BRIDGE_PCIEMEM_LIMIT0		0x38
-#define BRIDGE_PCIEMEM_LIMIT1		0x39
-#define BRIDGE_PCIEMEM_LIMIT2		0x3a
-#define BRIDGE_PCIEMEM_LIMIT3		0x3b
-#define BRIDGE_PCIEIO_BASE0		0x3c
-#define BRIDGE_PCIEIO_BASE1		0x3d
-#define BRIDGE_PCIEIO_BASE2		0x3e
-#define BRIDGE_PCIEIO_BASE3		0x3f
-#define BRIDGE_PCIEIO_LIMIT0		0x40
-#define BRIDGE_PCIEIO_LIMIT1		0x41
-#define BRIDGE_PCIEIO_LIMIT2		0x42
-#define BRIDGE_PCIEIO_LIMIT3		0x43
-#define BRIDGE_PCIEMEM_BASE4		0x44
-#define BRIDGE_PCIEMEM_BASE5		0x45
-#define BRIDGE_PCIEMEM_BASE6		0x46
-#define BRIDGE_PCIEMEM_LIMIT4		0x47
-#define BRIDGE_PCIEMEM_LIMIT5		0x48
-#define BRIDGE_PCIEMEM_LIMIT6		0x49
-#define BRIDGE_PCIEIO_BASE4		0x4a
-#define BRIDGE_PCIEIO_BASE5		0x4b
-#define BRIDGE_PCIEIO_BASE6		0x4c
-#define BRIDGE_PCIEIO_LIMIT4		0x4d
-#define BRIDGE_PCIEIO_LIMIT5		0x4e
-#define BRIDGE_PCIEIO_LIMIT6		0x4f
-#define BRIDGE_NBU_EVENT_CNT_CTL	0x50
-#define BRIDGE_EVNTCTR1_LOW		0x51
-#define BRIDGE_EVNTCTR1_HI		0x52
-#define BRIDGE_EVNT_CNT_CTL2		0x53
-#define BRIDGE_EVNTCTR2_LOW		0x54
-#define BRIDGE_EVNTCTR2_HI		0x55
-#define BRIDGE_TRACEBUF_MATCH0		0x56
-#define BRIDGE_TRACEBUF_MATCH1		0x57
-#define BRIDGE_TRACEBUF_MATCH_LOW	0x58
-#define BRIDGE_TRACEBUF_MATCH_HI	0x59
-#define BRIDGE_TRACEBUF_CTRL		0x5a
-#define BRIDGE_TRACEBUF_INIT		0x5b
-#define BRIDGE_TRACEBUF_ACCESS		0x5c
-#define BRIDGE_TRACEBUF_READ_DATA0	0x5d
-#define BRIDGE_TRACEBUF_READ_DATA1	0x5d
-#define BRIDGE_TRACEBUF_READ_DATA2	0x5f
-#define BRIDGE_TRACEBUF_READ_DATA3	0x60
-#define BRIDGE_TRACEBUF_STATUS		0x61
-#define BRIDGE_ADDRESS_ERROR0		0x62
-#define BRIDGE_ADDRESS_ERROR1		0x63
-#define BRIDGE_ADDRESS_ERROR2		0x64
-#define BRIDGE_TAG_ECC_ADDR_ERROR0	0x65
-#define BRIDGE_TAG_ECC_ADDR_ERROR1	0x66
-#define BRIDGE_TAG_ECC_ADDR_ERROR2	0x67
-#define BRIDGE_LINE_FLUSH0		0x68
-#define BRIDGE_LINE_FLUSH1		0x69
-#define BRIDGE_NODE_ID			0x6a
-#define BRIDGE_ERROR_INTERRUPT_EN	0x6b
-#define BRIDGE_PCIE0_WEIGHT		0x2c0
-#define BRIDGE_PCIE1_WEIGHT		0x2c1
-#define BRIDGE_PCIE2_WEIGHT		0x2c2
-#define BRIDGE_PCIE3_WEIGHT		0x2c3
-#define BRIDGE_USB_WEIGHT		0x2c4
-#define BRIDGE_NET_WEIGHT		0x2c5
-#define BRIDGE_POE_WEIGHT		0x2c6
-#define BRIDGE_CMS_WEIGHT		0x2c7
-#define BRIDGE_DMAENG_WEIGHT		0x2c8
-#define BRIDGE_SEC_WEIGHT		0x2c9
-#define BRIDGE_COMP_WEIGHT		0x2ca
-#define BRIDGE_GIO_WEIGHT		0x2cb
-#define BRIDGE_FLASH_WEIGHT		0x2cc
-
-/* FIXME verify */
-#define BRIDGE_9XX_FLASH_BAR(i)		(0x11 + (i))
-#define BRIDGE_9XX_FLASH_BAR_LIMIT(i)	(0x15 + (i))
-
-#define BRIDGE_9XX_DRAM_BAR(i)		(0x19 + (i))
-#define BRIDGE_9XX_DRAM_LIMIT(i)	(0x29 + (i))
-#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i)	(0x39 + (i))
-#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i)	(0x49 + (i))
-
-#define BRIDGE_9XX_ADDRESS_ERROR0	0x9d
-#define BRIDGE_9XX_ADDRESS_ERROR1	0x9e
-#define BRIDGE_9XX_ADDRESS_ERROR2	0x9f
-
-#define BRIDGE_9XX_PCIEMEM_BASE0	0x59
-#define BRIDGE_9XX_PCIEMEM_BASE1	0x5a
-#define BRIDGE_9XX_PCIEMEM_BASE2	0x5b
-#define BRIDGE_9XX_PCIEMEM_BASE3	0x5c
-#define BRIDGE_9XX_PCIEMEM_LIMIT0	0x5d
-#define BRIDGE_9XX_PCIEMEM_LIMIT1	0x5e
-#define BRIDGE_9XX_PCIEMEM_LIMIT2	0x5f
-#define BRIDGE_9XX_PCIEMEM_LIMIT3	0x60
-#define BRIDGE_9XX_PCIEIO_BASE0		0x61
-#define BRIDGE_9XX_PCIEIO_BASE1		0x62
-#define BRIDGE_9XX_PCIEIO_BASE2		0x63
-#define BRIDGE_9XX_PCIEIO_BASE3		0x64
-#define BRIDGE_9XX_PCIEIO_LIMIT0	0x65
-#define BRIDGE_9XX_PCIEIO_LIMIT1	0x66
-#define BRIDGE_9XX_PCIEIO_LIMIT2	0x67
-#define BRIDGE_9XX_PCIEIO_LIMIT3	0x68
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_bridge_reg(b, r)	nlm_read_reg(b, r)
-#define nlm_write_bridge_reg(b, r, v)	nlm_write_reg(b, r, v)
-#define nlm_get_bridge_pcibase(node)	nlm_pcicfg_base(cpu_is_xlp9xx() ? \
-		XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node))
-#define nlm_get_bridge_regbase(node)	\
-			(nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-#endif /* __ASSEMBLY__ */
-#endif /* __NLM_HAL_BRIDGE_H__ */

arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_CPUCONTROL_H__
-#define __NLM_HAL_CPUCONTROL_H__
-
-#define CPU_BLOCKID_IFU		0
-#define CPU_BLOCKID_ICU		1
-#define CPU_BLOCKID_IEU		2
-#define CPU_BLOCKID_LSU		3
-#define CPU_BLOCKID_MMU		4
-#define CPU_BLOCKID_PRF		5
-#define CPU_BLOCKID_SCH		7
-#define CPU_BLOCKID_SCU		8
-#define CPU_BLOCKID_FPU		9
-#define CPU_BLOCKID_MAP		10
-
-#define IFU_BRUB_RESERVE	0x007
-
-#define ICU_DEFEATURE		0x100
-
-#define LSU_DEFEATURE		0x304
-#define LSU_DEBUG_ADDR		0x305
-#define LSU_DEBUG_DATA0		0x306
-#define LSU_CERRLOG_REGID	0x309
-#define SCHED_DEFEATURE		0x700
-
-/* Offsets of interest from the 'MAP' Block */
-#define MAP_THREADMODE			0x00
-#define MAP_EXT_EBASE_ENABLE		0x04
-#define MAP_CCDI_CONFIG			0x08
-#define MAP_THRD0_CCDI_STATUS		0x0c
-#define MAP_THRD1_CCDI_STATUS		0x10
-#define MAP_THRD2_CCDI_STATUS		0x14
-#define MAP_THRD3_CCDI_STATUS		0x18
-#define MAP_THRD0_DEBUG_MODE		0x1c
-#define MAP_THRD1_DEBUG_MODE		0x20
-#define MAP_THRD2_DEBUG_MODE		0x24
-#define MAP_THRD3_DEBUG_MODE		0x28
-#define MAP_MISC_STATE			0x60
-#define MAP_DEBUG_READ_CTL		0x64
-#define MAP_DEBUG_READ_REG0		0x68
-#define MAP_DEBUG_READ_REG1		0x6c
-
-#define MMU_SETUP		0x400
-#define MMU_LFSRSEED		0x401
-#define MMU_HPW_NUM_PAGE_LVL	0x410
-#define MMU_PGWKR_PGDBASE	0x411
-#define MMU_PGWKR_PGDSHFT	0x412
-#define MMU_PGWKR_PGDMASK	0x413
-#define MMU_PGWKR_PUDSHFT	0x414
-#define MMU_PGWKR_PUDMASK	0x415
-#define MMU_PGWKR_PMDSHFT	0x416
-#define MMU_PGWKR_PMDMASK	0x417
-#define MMU_PGWKR_PTESHFT	0x418
-#define MMU_PGWKR_PTEMASK	0x419
-
-#endif /* __NLM_CPUCONTROL_H__ */

arch/mips/include/asm/netlogic/xlp-hal/iomap.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_IOMAP_H__
-#define __NLM_HAL_IOMAP_H__
-
-#define XLP_DEFAULT_IO_BASE		0x18000000
-#define XLP_DEFAULT_PCI_ECFG_BASE	XLP_DEFAULT_IO_BASE
-#define XLP_DEFAULT_PCI_CFG_BASE	0x1c000000
-
-#define NMI_BASE			0xbfc00000
-#define XLP_IO_CLK			133333333
-
-#define XLP_PCIE_CFG_SIZE		0x1000		/* 4K */
-#define XLP_PCIE_DEV_BLK_SIZE		(8 * XLP_PCIE_CFG_SIZE)
-#define XLP_PCIE_BUS_BLK_SIZE		(256 * XLP_PCIE_DEV_BLK_SIZE)
-#define XLP_IO_SIZE			(64 << 20)	/* ECFG space size */
-#define XLP_IO_PCI_HDRSZ		0x100
-#define XLP_IO_DEV(node, dev)		((dev) + (node) * 8)
-#define XLP_IO_PCI_OFFSET(b, d, f)	(((b) << 20) | ((d) << 15) | ((f) << 12))
-
-#define XLP_HDR_OFFSET(node, bus, dev, fn) \
-		XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn)
-
-#define XLP_IO_BRIDGE_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 0, 0)
-/* coherent inter chip */
-#define XLP_IO_CIC0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 0, 1)
-#define XLP_IO_CIC1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 0, 2)
-#define XLP_IO_CIC2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 0, 3)
-#define XLP_IO_PIC_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 0, 4)
-
-#define XLP_IO_PCIE_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 1, i)
-#define XLP_IO_PCIE0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 1, 0)
-#define XLP_IO_PCIE1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 1, 1)
-#define XLP_IO_PCIE2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 1, 2)
-#define XLP_IO_PCIE3_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 1, 3)
-
-#define XLP_IO_USB_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 2, i)
-#define XLP_IO_USB_EHCI0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 0)
-#define XLP_IO_USB_OHCI0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 1)
-#define XLP_IO_USB_OHCI1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 2)
-#define XLP_IO_USB_EHCI1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 3)
-#define XLP_IO_USB_OHCI2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 4)
-#define XLP_IO_USB_OHCI3_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 5)
-
-#define XLP_IO_SATA_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 3, 2)
-
-/* XLP2xx has an updated USB block */
-#define XLP2XX_IO_USB_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 4, i)
-#define XLP2XX_IO_USB_XHCI0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 1)
-#define XLP2XX_IO_USB_XHCI1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 2)
-#define XLP2XX_IO_USB_XHCI2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 3)
-
-#define XLP_IO_NAE_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 3, 0)
-#define XLP_IO_POE_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 3, 1)
-
-#define XLP_IO_CMS_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 4, 0)
-
-#define XLP_IO_DMA_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 5, 1)
-#define XLP_IO_SEC_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 5, 2)
-#define XLP_IO_CMP_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 5, 3)
-
-#define XLP_IO_UART_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 6, i)
-#define XLP_IO_UART0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 0)
-#define XLP_IO_UART1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 1)
-#define XLP_IO_I2C_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 6, 2 + i)
-#define XLP_IO_I2C0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 2)
-#define XLP_IO_I2C1_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 3)
-#define XLP_IO_GPIO_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 4)
-/* on 2XX, all I2C busses are on the same block */
-#define XLP2XX_IO_I2C_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 7)
-
-/* system management */
-#define XLP_IO_SYS_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 6, 5)
-#define XLP_IO_JTAG_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 6)
-
-/* Flash */
-#define XLP_IO_NOR_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 0)
-#define XLP_IO_NAND_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 7, 1)
-#define XLP_IO_SPI_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 2)
-#define XLP_IO_MMC_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 3)
-
-/* Things have changed drastically in XLP 9XX */
-#define XLP9XX_HDR_OFFSET(n, d, f)	\
-			XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f)
-
-#define XLP9XX_IO_BRIDGE_OFFSET(node)	XLP_IO_PCI_OFFSET(0, 0, node)
-#define XLP9XX_IO_PIC_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 2, 0)
-#define XLP9XX_IO_UART_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 2, 2)
-#define XLP9XX_IO_SYS_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 6, 0)
-#define XLP9XX_IO_FUSE_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 6, 1)
-#define XLP9XX_IO_CLOCK_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 6, 2)
-#define XLP9XX_IO_POWER_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 6, 3)
-#define XLP9XX_IO_JTAG_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 6, 4)
-
-#define XLP9XX_IO_PCIE_OFFSET(node, i)	XLP9XX_HDR_OFFSET(node, 1, i)
-#define XLP9XX_IO_PCIE0_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 1, 0)
-#define XLP9XX_IO_PCIE2_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 1, 2)
-#define XLP9XX_IO_PCIE3_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 1, 3)
-
-/* XLP9xx USB block */
-#define XLP9XX_IO_USB_OFFSET(node, i)		XLP9XX_HDR_OFFSET(node, 4, i)
-#define XLP9XX_IO_USB_XHCI0_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 4, 1)
-#define XLP9XX_IO_USB_XHCI1_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 4, 2)
-
-/* XLP9XX on-chip SATA controller */
-#define XLP9XX_IO_SATA_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 3, 2)
-
-/* Flash */
-#define XLP9XX_IO_NOR_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 0)
-#define XLP9XX_IO_NAND_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 1)
-#define XLP9XX_IO_SPI_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 2)
-#define XLP9XX_IO_MMC_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 3)
-
-/* PCI config header register id's */
-#define XLP_PCI_CFGREG0			0x00
-#define XLP_PCI_CFGREG1			0x01
-#define XLP_PCI_CFGREG2			0x02
-#define XLP_PCI_CFGREG3			0x03
-#define XLP_PCI_CFGREG4			0x04
-#define XLP_PCI_CFGREG5			0x05
-#define XLP_PCI_DEVINFO_REG0		0x30
-#define XLP_PCI_DEVINFO_REG1		0x31
-#define XLP_PCI_DEVINFO_REG2		0x32
-#define XLP_PCI_DEVINFO_REG3		0x33
-#define XLP_PCI_DEVINFO_REG4		0x34
-#define XLP_PCI_DEVINFO_REG5		0x35
-#define XLP_PCI_DEVINFO_REG6		0x36
-#define XLP_PCI_DEVINFO_REG7		0x37
-#define XLP_PCI_DEVSCRATCH_REG0		0x38
-#define XLP_PCI_DEVSCRATCH_REG1		0x39
-#define XLP_PCI_DEVSCRATCH_REG2		0x3a
-#define XLP_PCI_DEVSCRATCH_REG3		0x3b
-#define XLP_PCI_MSGSTN_REG		0x3c
-#define XLP_PCI_IRTINFO_REG		0x3d
-#define XLP_PCI_UCODEINFO_REG		0x3e
-#define XLP_PCI_SBB_WT_REG		0x3f
-
-/* PCI IDs for SoC device */
-#define PCI_VENDOR_NETLOGIC		0x184e
-
-#define PCI_DEVICE_ID_NLM_ROOT		0x1001
-#define PCI_DEVICE_ID_NLM_ICI		0x1002
-#define PCI_DEVICE_ID_NLM_PIC		0x1003
-#define PCI_DEVICE_ID_NLM_PCIE		0x1004
-#define PCI_DEVICE_ID_NLM_EHCI		0x1007
-#define PCI_DEVICE_ID_NLM_OHCI		0x1008
-#define PCI_DEVICE_ID_NLM_NAE		0x1009
-#define PCI_DEVICE_ID_NLM_POE		0x100A
-#define PCI_DEVICE_ID_NLM_FMN		0x100B
-#define PCI_DEVICE_ID_NLM_RAID		0x100D
-#define PCI_DEVICE_ID_NLM_SAE		0x100D
-#define PCI_DEVICE_ID_NLM_RSA		0x100E
-#define PCI_DEVICE_ID_NLM_CMP		0x100F
-#define PCI_DEVICE_ID_NLM_UART		0x1010
-#define PCI_DEVICE_ID_NLM_I2C		0x1011
-#define PCI_DEVICE_ID_NLM_NOR		0x1015
-#define PCI_DEVICE_ID_NLM_NAND		0x1016
-#define PCI_DEVICE_ID_NLM_MMC		0x1018
-#define PCI_DEVICE_ID_NLM_SATA		0x101A
-#define PCI_DEVICE_ID_NLM_XHCI		0x101D
-
-#define PCI_DEVICE_ID_XLP9XX_MMC	0x9018
-#define PCI_DEVICE_ID_XLP9XX_SATA	0x901A
-#define PCI_DEVICE_ID_XLP9XX_XHCI	0x901D
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_pci_reg(b, r)		nlm_read_reg(b, r)
-#define nlm_write_pci_reg(b, r, v)	nlm_write_reg(b, r, v)
-
-static inline int xlp9xx_get_socbus(int node)
-{
-	uint64_t socbridge;
-
-	if (node == 0)
-		return 1;
-	socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node));
-	return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff;
-}
-#endif /* !__ASSEMBLY */
-
-#endif /* __NLM_HAL_IOMAP_H__ */

arch/mips/include/asm/netlogic/xlp-hal/pcibus.h

-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_PCIBUS_H__
-#define __NLM_HAL_PCIBUS_H__
-
-/* PCIE Memory and IO regions */
-#define PCIE_MEM_BASE			0xd0000000ULL
-#define PCIE_MEM_LIMIT			0xdfffffffULL
-#define PCIE_IO_BASE			0x14000000ULL
-#define PCIE_IO_LIMIT			0x15ffffffULL
-
-#define PCIE_BRIDGE_CMD			0x1
-#define PCIE_BRIDGE_MSI_CAP		0x14
-#define PCIE_BRIDGE_MSI_ADDRL		0x15
-#define PCIE_BRIDGE_MSI_ADDRH		0x16
-#define PCIE_BRIDGE_MSI_DATA		0x17
-
-/* XLP Global PCIE configuration space registers */
-#define PCIE_BYTE_SWAP_MEM_BASE		0x247
-#define PCIE_BYTE_SWAP_MEM_LIM		0x248
-#define PCIE_BYTE_SWAP_IO_BASE		0x249
-#define PCIE_BYTE_SWAP_IO_LIM		0x24A
-
-#define PCIE_BRIDGE_MSIX_ADDR_BASE	0x24F
-#define PCIE_BRIDGE_MSIX_ADDR_LIMIT	0x250
-#define PCIE_MSI_STATUS			0x25A
-#define PCIE_MSI_EN			0x25B
-#define PCIE_MSIX_STATUS		0x25D
-#define PCIE_INT_STATUS0		0x25F
-#define PCIE_INT_STATUS1		0x260
-#define PCIE_INT_EN0			0x261
-#define PCIE_INT_EN1			0x262
-
-/* XLP9XX has basic changes */
-#define PCIE_9XX_BYTE_SWAP_MEM_BASE	0x25c
-#define PCIE_9XX_BYTE_SWAP_MEM_LIM	0x25d
-#define PCIE_9XX_BYTE_SWAP_IO_BASE	0x25e
-#define PCIE_9XX_BYTE_SWAP_IO_LIM	0x25f
-
-#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE	0x264
-#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT	0x265
-#define PCIE_9XX_MSI_STATUS		0x283
-#define PCIE_9XX_MSI_EN			0x284
-/* 128 MSIX vectors available in 9xx */
-#define PCIE_9XX_MSIX_STATUS0		0x286
-#define PCIE_9XX_MSIX_STATUSX(n)	(n + 0x286)
-#define PCIE_9XX_MSIX_VEC		0x296
-#define PCIE_9XX_MSIX_VECX(n)		(n + 0x296)
-#define PCIE_9XX_INT_STATUS0		0x397
-#define PCIE_9XX_INT_STATUS1		0x398
-#define PCIE_9XX_INT_EN0		0x399
-#define PCIE_9XX_INT_EN1		0x39a
-
-/* other */
-#define PCIE_NLINKS			4
-
-/* MSI addresses */
-#define MSI_ADDR_BASE			0xfffee00000ULL
-#define MSI_ADDR_SZ			0x10000
-#define MSI_LINK_ADDR(n, l)		(MSI_ADDR_BASE + \
-				(PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
-#define MSIX_ADDR_BASE			0xfffef00000ULL
-#define MSIX_LINK_ADDR(n, l)		(MSIX_ADDR_BASE + \
-				(PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ)
-#ifndef __ASSEMBLY__
-
-#define nlm_read_pcie_reg(b, r)		nlm_read_reg(b, r)
-#define nlm_write_pcie_reg(b, r, v)	nlm_write_reg(b, r, v)
-#define nlm_get_pcie_base(node, inst)	nlm_pcicfg_base(cpu_is_xlp9xx() ? \
-	XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst))
-
-#ifdef CONFIG_PCI_MSI
-void xlp_init_node_msi_irqs(int node, int link);
-#else
-static inline void xlp_init_node_msi_irqs(int node, int link) {}
-#endif
-
-struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev);
-
-#endif
-#endif /* __NLM_HAL_PCIBUS_H__ */

arch/mips/include/asm/netlogic/xlp-hal/sys.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NLM_HAL_SYS_H__
-#define __NLM_HAL_SYS_H__
-
-/**
-* @file_name sys.h
-* @author Netlogic Microsystems
-* @brief HAL for System configuration registers
-*/
-#define SYS_CHIP_RESET				0x00
-#define SYS_POWER_ON_RESET_CFG			0x01
-#define SYS_EFUSE_DEVICE_CFG_STATUS0		0x02
-#define SYS_EFUSE_DEVICE_CFG_STATUS1		0x03
-#define SYS_EFUSE_DEVICE_CFG_STATUS2		0x04
-#define SYS_EFUSE_DEVICE_CFG3			0x05
-#define SYS_EFUSE_DEVICE_CFG4			0x06
-#define SYS_EFUSE_DEVICE_CFG5			0x07
-#define SYS_EFUSE_DEVICE_CFG6			0x08
-#define SYS_EFUSE_DEVICE_CFG7			0x09
-#define SYS_PLL_CTRL				0x0a
-#define SYS_CPU_RESET				0x0b
-#define SYS_CPU_NONCOHERENT_MODE		0x0d
-#define SYS_CORE_DFS_DIS_CTRL			0x0e
-#define SYS_CORE_DFS_RST_CTRL			0x0f
-#define SYS_CORE_DFS_BYP_CTRL			0x10
-#define SYS_CORE_DFS_PHA_CTRL			0x11
-#define SYS_CORE_DFS_DIV_INC_CTRL		0x12
-#define SYS_CORE_DFS_DIV_DEC_CTRL		0x13
-#define SYS_CORE_DFS_DIV_VALUE			0x14
-#define SYS_RESET				0x15
-#define SYS_DFS_DIS_CTRL			0x16
-#define SYS_DFS_RST_CTRL			0x17
-#define SYS_DFS_BYP_CTRL			0x18
-#define SYS_DFS_DIV_INC_CTRL			0x19
-#define SYS_DFS_DIV_DEC_CTRL			0x1a
-#define SYS_DFS_DIV_VALUE0			0x1b
-#define SYS_DFS_DIV_VALUE1			0x1c
-#define SYS_SENSE_AMP_DLY			0x1d
-#define SYS_SOC_SENSE_AMP_DLY			0x1e
-#define SYS_CTRL0				0x1f
-#define SYS_CTRL1				0x20
-#define SYS_TIMEOUT_BS1				0x21
-#define SYS_BYTE_SWAP				0x22
-#define SYS_VRM_VID				0x23
-#define SYS_PWR_RAM_CMD				0x24
-#define SYS_PWR_RAM_ADDR			0x25
-#define SYS_PWR_RAM_DATA0			0x26
-#define SYS_PWR_RAM_DATA1			0x27
-#define SYS_PWR_RAM_DATA2			0x28
-#define SYS_PWR_UCODE				0x29
-#define SYS_CPU0_PWR_STATUS			0x2a
-#define SYS_CPU1_PWR_STATUS			0x2b
-#define SYS_CPU2_PWR_STATUS			0x2c
-#define SYS_CPU3_PWR_STATUS			0x2d
-#define SYS_CPU4_PWR_STATUS			0x2e
-#define SYS_CPU5_PWR_STATUS			0x2f
-#define SYS_CPU6_PWR_STATUS			0x30
-#define SYS_CPU7_PWR_STATUS			0x31
-#define SYS_STATUS				0x32
-#define SYS_INT_POL				0x33
-#define SYS_INT_TYPE				0x34
-#define SYS_INT_STATUS				0x35
-#define SYS_INT_MASK0				0x36
-#define SYS_INT_MASK1				0x37
-#define SYS_UCO_S_ECC				0x38
-#define SYS_UCO_M_ECC				0x39
-#define SYS_UCO_ADDR				0x3a
-#define SYS_UCO_INSTR				0x3b
-#define SYS_MEM_BIST0				0x3c
-#define SYS_MEM_BIST1				0x3d
-#define SYS_MEM_BIST2				0x3e
-#define SYS_MEM_BIST3				0x3f
-#define SYS_MEM_BIST4				0x40
-#define SYS_MEM_BIST5				0x41
-#define SYS_MEM_BIST6				0x42
-#define SYS_MEM_BIST7				0x43
-#define SYS_MEM_BIST8				0x44
-#define SYS_MEM_BIST9				0x45
-#define SYS_MEM_BIST10				0x46
-#define SYS_MEM_BIST11				0x47
-#define SYS_MEM_BIST12				0x48
-#define SYS_SCRTCH0				0x49
-#define SYS_SCRTCH1				0x4a
-#define SYS_SCRTCH2				0x4b
-#define SYS_SCRTCH3				0x4c
-
-/* PLL registers XLP2XX */
-#define SYS_CPU_PLL_CTRL0(core)			(0x1c0 + (core * 4))
-#define SYS_CPU_PLL_CTRL1(core)			(0x1c1 + (core * 4))
-#define SYS_CPU_PLL_CTRL2(core)			(0x1c2 + (core * 4))
-#define SYS_CPU_PLL_CTRL3(core)			(0x1c3 + (core * 4))
-#define SYS_PLL_CTRL0				0x240
-#define SYS_PLL_CTRL1				0x241
-#define SYS_PLL_CTRL2				0x242
-#define SYS_PLL_CTRL3				0x243
-#define SYS_DMC_PLL_CTRL0			0x244
-#define SYS_DMC_PLL_CTRL1			0x245
-#define SYS_DMC_PLL_CTRL2			0x246
-#define SYS_DMC_PLL_CTRL3			0x247
-
-#define SYS_PLL_CTRL0_DEVX(x)			(0x248 + (x) * 4)
-#define SYS_PLL_CTRL1_DEVX(x)			(0x249 + (x) * 4)
-#define SYS_PLL_CTRL2_DEVX(x)			(0x24a + (x) * 4)
-#define SYS_PLL_CTRL3_DEVX(x)			(0x24b + (x) * 4)
-
-#define SYS_CPU_PLL_CHG_CTRL			0x288
-#define SYS_PLL_CHG_CTRL			0x289
-#define SYS_CLK_DEV_DIS				0x28a
-#define SYS_CLK_DEV_SEL				0x28b
-#define SYS_CLK_DEV_DIV				0x28c
-#define SYS_CLK_DEV_CHG				0x28d
-#define SYS_CLK_DEV_SEL_REG			0x28e
-#define SYS_CLK_DEV_DIV_REG			0x28f
-#define SYS_CPU_PLL_LOCK			0x29f
-#define SYS_SYS_PLL_LOCK			0x2a0
-#define SYS_PLL_MEM_CMD				0x2a1
-#define SYS_CPU_PLL_MEM_REQ			0x2a2
-#define SYS_SYS_PLL_MEM_REQ			0x2a3
-#define SYS_PLL_MEM_STAT			0x2a4
-
-/* PLL registers XLP9XX */
-#define SYS_9XX_CPU_PLL_CTRL0(core)		(0xc0 + (core * 4))
-#define SYS_9XX_CPU_PLL_CTRL1(core)		(0xc1 + (core * 4))
-#define SYS_9XX_CPU_PLL_CTRL2(core)		(0xc2 + (core * 4))
-#define SYS_9XX_CPU_PLL_CTRL3(core)		(0xc3 + (core * 4))
-#define SYS_9XX_DMC_PLL_CTRL0			0x140
-#define SYS_9XX_DMC_PLL_CTRL1			0x141
-#define SYS_9XX_DMC_PLL_CTRL2			0x142
-#define SYS_9XX_DMC_PLL_CTRL3			0x143
-#define SYS_9XX_PLL_CTRL0			0x144
-#define SYS_9XX_PLL_CTRL1			0x145
-#define SYS_9XX_PLL_CTRL2			0x146
-#define SYS_9XX_PLL_CTRL3			0x147
-
-#define SYS_9XX_PLL_CTRL0_DEVX(x)		(0x148 + (x) * 4)
-#define SYS_9XX_PLL_CTRL1_DEVX(x)		(0x149 + (x) * 4)
-#define SYS_9XX_PLL_CTRL2_DEVX(x)		(0x14a + (x) * 4)
-#define SYS_9XX_PLL_CTRL3_DEVX(x)		(0x14b + (x) * 4)
-
-#define SYS_9XX_CPU_PLL_CHG_CTRL		0x188
-#define SYS_9XX_PLL_CHG_CTRL			0x189
-#define SYS_9XX_CLK_DEV_DIS			0x18a
-#define SYS_9XX_CLK_DEV_SEL			0x18b
-#define SYS_9XX_CLK_DEV_DIV			0x18d
-#define SYS_9XX_CLK_DEV_CHG			0x18f
-
-#define SYS_9XX_CLK_DEV_SEL_REG			0x1a4
-#define SYS_9XX_CLK_DEV_DIV_REG			0x1a6
-
-/* Registers changed on 9XX */
-#define SYS_9XX_POWER_ON_RESET_CFG		0x00
-#define SYS_9XX_CHIP_RESET			0x01
-#define SYS_9XX_CPU_RESET			0x02
-#define SYS_9XX_CPU_NONCOHERENT_MODE		0x03
-
-/* XLP 9XX fuse block registers */
-#define FUSE_9XX_DEVCFG6			0xc6
-
-#ifndef __ASSEMBLY__
-
-#define nlm_read_sys_reg(b, r)		nlm_read_reg(b, r)
-#define nlm_write_sys_reg(b, r, v)	nlm_write_reg(b, r, v)
-#define nlm_get_sys_pcibase(node)	nlm_pcicfg_base(cpu_is_xlp9xx() ? \
-		XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node))
-#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-/* XLP9XX fuse block */
-#define nlm_get_fuse_pcibase(node)	\
-			nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node))
-#define nlm_get_fuse_regbase(node)	\
-			(nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-#define nlm_get_clock_pcibase(node)	\
-			nlm_pcicfg_base(XLP9XX_IO_CLOCK_OFFSET(node))
-#define nlm_get_clock_regbase(node)	\
-			(nlm_get_clock_pcibase(node) + XLP_IO_PCI_HDRSZ)
-
-unsigned int nlm_get_pic_frequency(int node);
-#endif
-#endif

arch/mips/include/asm/netlogic/xlp-hal/uart.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __XLP_HAL_UART_H__
-#define __XLP_HAL_UART_H__
-
-/* UART Specific registers */
-#define UART_RX_DATA		0x00
-#define UART_TX_DATA		0x00
-
-#define UART_INT_EN		0x01
-#define UART_INT_ID		0x02
-#define UART_FIFO_CTL		0x02
-#define UART_LINE_CTL		0x03
-#define UART_MODEM_CTL		0x04
-#define UART_LINE_STS		0x05
-#define UART_MODEM_STS		0x06
-
-#define UART_DIVISOR0		0x00
-#define UART_DIVISOR1		0x01
-
-#define BASE_BAUD		(XLP_IO_CLK/16)
-#define BAUD_DIVISOR(baud)	(BASE_BAUD / baud)
-
-/* LCR mask values */
-#define LCR_5BITS		0x00
-#define LCR_6BITS		0x01
-#define LCR_7BITS		0x02
-#define LCR_8BITS		0x03
-#define LCR_STOPB		0x04
-#define LCR_PENAB		0x08
-#define LCR_PODD		0x00
-#define LCR_PEVEN		0x10
-#define LCR_PONE		0x20
-#define LCR_PZERO		0x30
-#define LCR_SBREAK		0x40
-#define LCR_EFR_ENABLE		0xbf
-#define LCR_DLAB		0x80
-
-/* MCR mask values */
-#define MCR_DTR			0x01
-#define MCR_RTS			0x02
-#define MCR_DRS			0x04
-#define MCR_IE			0x08
-#define MCR_LOOPBACK		0x10
-
-/* FCR mask values */
-#define FCR_RCV_RST		0x02
-#define FCR_XMT_RST		0x04
-#define FCR_RX_LOW		0x00
-#define FCR_RX_MEDL		0x40
-#define FCR_RX_MEDH		0x80
-#define FCR_RX_HIGH		0xc0
-
-/* IER mask values */
-#define IER_ERXRDY		0x1
-#define IER_ETXRDY		0x2
-#define IER_ERLS		0x4
-#define IER_EMSC		0x8
-
-#if !defined(LOCORE) && !defined(__ASSEMBLY__)
-
-#define nlm_read_uart_reg(b, r)		nlm_read_reg(b, r)
-#define nlm_write_uart_reg(b, r, v)	nlm_write_reg(b, r, v)
-#define nlm_get_uart_pcibase(node, inst)	\
-	nlm_pcicfg_base(cpu_is_xlp9xx() ?  XLP9XX_IO_UART_OFFSET(node) : \
-						XLP_IO_UART_OFFSET(node, inst))
-#define nlm_get_uart_regbase(node, inst)	\
-			(nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
-
-static inline void
-nlm_uart_set_baudrate(uint64_t base, int baud)
-{
-	uint32_t lcr;
-
-	lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
-
-	/* enable divisor register, and write baud values */
-	nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
-	nlm_write_uart_reg(base, UART_DIVISOR0,
-			(BAUD_DIVISOR(baud) & 0xff));
-	nlm_write_uart_reg(base, UART_DIVISOR1,
-			((BAUD_DIVISOR(baud) >> 8) & 0xff));
-
-	/* restore default lcr */
-	nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
-}
-
-static inline void
-nlm_uart_outbyte(uint64_t base, char c)
-{
-	uint32_t lsr;
-
-	for (;;) {
-		lsr = nlm_read_uart_reg(base, UART_LINE_STS);
-		if (lsr & 0x20)
-			break;
-	}
-
-	nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
-}
-
-static inline char
-nlm_uart_inbyte(uint64_t base)
-{
-	int data, lsr;
-
-	for (;;) {
-		lsr = nlm_read_uart_reg(base, UART_LINE_STS);
-		if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
-			data = 0;
-			break;
-		}
-		if (lsr & 0x01) {	/* Rx data */
-			data = nlm_read_uart_reg(base, UART_RX_DATA);
-			break;
-		}
-	}
-
-	return (char)data;
-}
-
-static inline int
-nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
-	int parity, int int_en, int loopback)
-{
-	uint32_t lcr;
-
-	lcr = 0;
-	if (databits >= 8)
-		lcr |= LCR_8BITS;
-	else if (databits == 7)
-		lcr |= LCR_7BITS;
-	else if (databits == 6)
-		lcr |= LCR_6BITS;
-	else
-		lcr |= LCR_5BITS;
-
-	if (stopbits > 1)
-		lcr |= LCR_STOPB;
-
-	lcr |= parity << 3;
-
-	/* setup default lcr */
-	nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
-
-	/* Reset the FIFOs */
-	nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
-
-	nlm_uart_set_baudrate(base, baud);
-
-	if (loopback)
-		nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
-
-	if (int_en)
-		nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
-
-	return 0;
-}
-#endif /* !LOCORE && !__ASSEMBLY__ */
-#endif /* __XLP_HAL_UART_H__ */

arch/mips/include/asm/netlogic/xlp-hal/xlp.h

-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _NLM_HAL_XLP_H
-#define _NLM_HAL_XLP_H
-
-#define PIC_UART_0_IRQ			17
-#define PIC_UART_1_IRQ			18
-
-#define PIC_PCIE_LINK_LEGACY_IRQ_BASE	19
-#define PIC_PCIE_LINK_LEGACY_IRQ(i)	(19 + (i))
-
-#define PIC_EHCI_0_IRQ			23
-#define PIC_EHCI_1_IRQ			24
-#define PIC_OHCI_0_IRQ			25
-#define PIC_OHCI_1_IRQ			26
-#define PIC_OHCI_2_IRQ			27
-#define PIC_OHCI_3_IRQ			28
-#define PIC_2XX_XHCI_0_IRQ		23
-#define PIC_2XX_XHCI_1_IRQ		24
-#define PIC_2XX_XHCI_2_IRQ		25
-#define PIC_9XX_XHCI_0_IRQ		23
-#define PIC_9XX_XHCI_1_IRQ		24
-#define PIC_9XX_XHCI_2_IRQ		25
-
-#define PIC_MMC_IRQ			29
-#define PIC_I2C_0_IRQ			30
-#define PIC_I2C_1_IRQ			31
-#define PIC_I2C_2_IRQ			32
-#define PIC_I2C_3_IRQ			33
-#define PIC_SPI_IRQ			34
-#define PIC_NAND_IRQ			37
-#define PIC_SATA_IRQ			38
-#define PIC_GPIO_IRQ			39
-
-#define PIC_PCIE_LINK_MSI_IRQ_BASE	44	/* 44 - 47 MSI IRQ */
-#define PIC_PCIE_LINK_MSI_IRQ(i)	(44 + (i))
-
-/* MSI-X with second link-level dispatch */
-#define PIC_PCIE_MSIX_IRQ_BASE		48	/* 48 - 51 MSI-X IRQ */
-#define PIC_PCIE_MSIX_IRQ(i)		(48 + (i))
-
-/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */
-#define NLM_MSIX_VEC_BASE		96	/* 96 - 223 - MSIX mapped */
-#define NLM_MSI_VEC_BASE		224	/* 224 -351 - MSI mapped */
-
-#define NLM_PIC_INDIRECT_VEC_BASE	512
-#define NLM_GPIO_VEC_BASE		768
-
-#define PIC_IRQ_BASE			8
-#define PIC_IRT_FIRST_IRQ		PIC_IRQ_BASE
-#define PIC_IRT_LAST_IRQ		63
-
-#ifndef __ASSEMBLY__
-
-/* SMP support functions */
-void xlp_boot_core0_siblings(void);
-void xlp_wakeup_secondary_cpus(void);
-
-void xlp_mmu_init(void);
-void nlm_hal_init(void);
-int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
-
-struct pci_dev;
-int xlp_socdev_to_node(const struct pci_dev *dev);
-
-/* Device tree related */
-void xlp_early_init_devtree(void);
-void *xlp_dt_init(void *fdtp);
-
-static inline int cpu_is_xlpii(void)
-{
-	int chip = read_c0_prid() & PRID_IMP_MASK;
-
-	return chip == PRID_IMP_NETLOGIC_XLP2XX ||
-		chip == PRID_IMP_NETLOGIC_XLP9XX ||
-		chip == PRID_IMP_NETLOGIC_XLP5XX;
-}
-
-static inline int cpu_is_xlp9xx(void)
-{
-	int chip = read_c0_prid() & PRID_IMP_MASK;
-
-	return chip == PRID_IMP_NETLOGIC_XLP9XX ||
-		chip == PRID_IMP_NETLOGIC_XLP5XX;
-}
-#endif /* !__ASSEMBLY__ */
-#endif /* _ASM_NLM_XLP_H */

arch/mips/include/asm/netlogic/xlr/bridge.h

-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _ASM_NLM_BRIDGE_H_
-#define _ASM_NLM_BRIDGE_H_
-
-#define BRIDGE_DRAM_0_BAR		0
-#define BRIDGE_DRAM_1_BAR		1
-#define BRIDGE_DRAM_2_BAR		2
-#define BRIDGE_DRAM_3_BAR		3
-#define BRIDGE_DRAM_4_BAR		4
-#define BRIDGE_DRAM_5_BAR		5
-#define BRIDGE_DRAM_6_BAR		6
-#define BRIDGE_DRAM_7_BAR		7
-#define BRIDGE_DRAM_CHN_0_MTR_0_BAR	8
-#define BRIDGE_DRAM_CHN_0_MTR_1_BAR	9
-#define BRIDGE_DRAM_CHN_0_MTR_2_BAR	10
-#define BRIDGE_DRAM_CHN_0_MTR_3_BAR	11
-#define BRIDGE_DRAM_CHN_0_MTR_4_BAR	12
-#define BRIDGE_DRAM_CHN_0_MTR_5_BAR	13
-#define BRIDGE_DRAM_CHN_0_MTR_6_BAR	14
-#define BRIDGE_DRAM_CHN_0_MTR_7_BAR	15
-#define BRIDGE_DRAM_CHN_1_MTR_0_BAR	16
-#define BRIDGE_DRAM_CHN_1_MTR_1_BAR	17
-#define BRIDGE_DRAM_CHN_1_MTR_2_BAR	18
-#define BRIDGE_DRAM_CHN_1_MTR_3_BAR	19
-#define BRIDGE_DRAM_CHN_1_MTR_4_BAR	20
-#define BRIDGE_DRAM_CHN_1_MTR_5_BAR	21
-#define BRIDGE_DRAM_CHN_1_MTR_6_BAR	22
-#define BRIDGE_DRAM_CHN_1_MTR_7_BAR	23
-#define BRIDGE_CFG_BAR			24
-#define BRIDGE_PHNX_IO_BAR		25
-#define BRIDGE_FLASH_BAR		26
-#define BRIDGE_SRAM_BAR			27
-#define BRIDGE_HTMEM_BAR		28
-#define BRIDGE_HTINT_BAR		29
-#define BRIDGE_HTPIC_BAR		30
-#define BRIDGE_HTSM_BAR			31
-#define BRIDGE_HTIO_BAR			32
-#define BRIDGE_HTCFG_BAR		33
-#define BRIDGE_PCIXCFG_BAR		34
-#define BRIDGE_PCIXMEM_BAR		35
-#define BRIDGE_PCIXIO_BAR		36
-#define BRIDGE_DEVICE_MASK		37
-#define BRIDGE_AERR_INTR_LOG1		38
-#define BRIDGE_AERR_INTR_LOG2		39
-#define BRIDGE_AERR_INTR_LOG3		40
-#define BRIDGE_AERR_DEV_STAT		41
-#define BRIDGE_AERR1_LOG1		42
-#define BRIDGE_AERR1_LOG2		43
-#define BRIDGE_AERR1_LOG3		44
-#define BRIDGE_AERR1_DEV_STAT		45
-#define BRIDGE_AERR_INTR_EN		46
-#define BRIDGE_AERR_UPG			47
-#define BRIDGE_AERR_CLEAR		48
-#define BRIDGE_AERR1_CLEAR		49
-#define BRIDGE_SBE_COUNTS		50
-#define BRIDGE_DBE_COUNTS		51
-#define BRIDGE_BITERR_INT_EN		52
-
-#define BRIDGE_SYS2IO_CREDITS		53
-#define BRIDGE_EVNT_CNT_CTRL1		54
-#define BRIDGE_EVNT_COUNTER1		55
-#define BRIDGE_EVNT_CNT_CTRL2		56
-#define BRIDGE_EVNT_COUNTER2		57
-#define BRIDGE_RESERVED1		58
-
-#define BRIDGE_DEFEATURE		59
-#define BRIDGE_SCRATCH0			60
-#define BRIDGE_SCRATCH1			61
-#define BRIDGE_SCRATCH2			62
-#define BRIDGE_SCRATCH3			63
-
-#endif

arch/mips/include/asm/netlogic/xlr/flash.h

-/*
- * Copyright (c) 2003-2012 Broadcom Corporation
- * All Rights Reserved
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the Broadcom
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _ASM_NLM_FLASH_H_
-#define _ASM_NLM_FLASH_H_
-
-#define FLASH_CSBASE_ADDR(cs)		(cs)
-#define FLASH_CSADDR_MASK(cs)		(0x10 + (cs))
-#define FLASH_CSDEV_PARM(cs)		(0x20 + (cs))
-#define FLASH_CSTIME_PARMA(cs)		(0x30 + (cs))
-#define FLASH_CSTIME_PARMB(cs)		(0x40 + (cs))
-
-#define FLASH_INT_MASK			0x50
-#define FLASH_INT_STATUS		0x60
-#define FLASH_ERROR_STATUS		0x70
-#define FLASH_ERROR_ADDR		0x80
-
-#define FLASH_NAND_CLE(cs)		(0x90 + (cs))
-#define FLASH_NAND_ALE(cs)		(0xa0 + (cs))
-
-#define FLASH_NAND_CSDEV_PARAM		0x000041e6
-#define FLASH_NAND_CSTIME_PARAMA	0x4f400e22
-#define FLASH_NAND_CSTIME_PARAMB	0x000083cf
-
-#endif

arch/mips/include/asm/octeon/cvmx-helper.h

@@ -93,13 +93,6 @@ extern int cvmx_helper_ipd_and_packet_input_enable(void);
  */
 extern int cvmx_helper_initialize_packet_io_global(void);
 
-/**
- * Does core local initialization for packet io
- *
- * Returns Zero on success, non-zero on failure
- */
-extern int cvmx_helper_initialize_packet_io_local(void);
-
 /**
  * Returns the number of ports on the given interface.
  * The interface must be initialized before the port count

arch/mips/include/asm/octeon/cvmx-pko.h

@@ -277,7 +277,6 @@ typedef struct {
  * output system.
  */
 extern void cvmx_pko_initialize_global(void);
-extern int cvmx_pko_initialize_local(void);
 
 /**
  * Enables the packet output hardware. It must already be

arch/mips/include/asm/processor.h

@@ -207,16 +207,6 @@ struct octeon_cvmseg_state {
 			    [cpu_dcache_line_size() / sizeof(unsigned long)];
 };
 
-#elif defined(CONFIG_CPU_XLP)
-struct nlm_cop2_state {
-	u64	rx[4];
-	u64	tx[4];
-	u32	tx_msg_status;
-	u32	rx_msg_status;
-};
-
-#define COP2_INIT						\
-	.cp2			= {{0}, {0}, 0, 0},
 #else
 #define COP2_INIT
 #endif
@@ -274,9 +264,6 @@ struct thread_struct {
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 	struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
 	struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
-#endif
-#ifdef CONFIG_CPU_XLP
-	struct nlm_cop2_state cp2;
 #endif
 	struct mips_abi *abi;
 };