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Commit a515abd7 authored by David S. Miller's avatar David S. Miller
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Merge branch 'cxgb4-next' 

Hariprasad Shenai says:

====================
RDMA/cxgb4/cxgb4vf/csiostor: Cleanup register defines

This series continues to cleanup all the macros/register defines related to
SGE, PCIE, MC, MA, TCAM, MAC, etc that are defined in t4_regs.h and the
affected files.

Will post another 1 or 2 series so that we can cover all the macros so that
they all follow the same style to be consistent.

The patches series is created against 'net-next' tree.
And includes patches on cxgb4, cxgb4vf, iw_cxgb4 and csiostor driver.

We have included all the maintainers of respective drivers. Kindly review the
change and let us know in case of any review comments.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 5f07b3c5 0d804338
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Showing with 3151 additions and 2325 deletions
drivers/infiniband/hw/cxgb4/t4.h
View file @ a515abd7
......@@ -465,14 +465,14 @@ static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5,
} else {
PDBG("%s: DB wq->sq.pidx = %d\n",
__func__, wq->sq.pidx);
writel(PIDX_T5(inc), wq->sq.udb);
writel(PIDX_T5_V(inc), wq->sq.udb);
}
/* Flush user doorbell area writes. */
wmb();
return;
}
writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db);
}
static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
......@@ -489,14 +489,14 @@ static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5,
} else {
PDBG("%s: DB wq->rq.pidx = %d\n",
__func__, wq->rq.pidx);
writel(PIDX_T5(inc), wq->rq.udb);
writel(PIDX_T5_V(inc), wq->rq.udb);
}
/* Flush user doorbell area writes. */
wmb();
return;
}
writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db);
}
static inline int t4_wq_in_error(struct t4_wq *wq)
......@@ -561,14 +561,14 @@ static inline int t4_arm_cq(struct t4_cq *cq, int se)
u32 val;
set_bit(CQ_ARMED, &cq->flags);
while (cq->cidx_inc > CIDXINC_MASK) {
val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |
INGRESSQID(cq->cqid);
while (cq->cidx_inc > CIDXINC_M) {
val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7) |
INGRESSQID_V(cq->cqid);
writel(val, cq->gts);
cq->cidx_inc -= CIDXINC_MASK;
cq->cidx_inc -= CIDXINC_M;
}
val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |
INGRESSQID(cq->cqid);
val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6) |
INGRESSQID_V(cq->cqid);
writel(val, cq->gts);
cq->cidx_inc = 0;
return 0;
......@@ -597,11 +597,11 @@ static inline void t4_swcq_consume(struct t4_cq *cq)
static inline void t4_hwcq_consume(struct t4_cq *cq)
{
cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_MASK) {
if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) {
u32 val;
val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) |
INGRESSQID(cq->cqid);
val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7) |
INGRESSQID_V(cq->cqid);
writel(val, cq->gts);
cq->cidx_inc = 0;
}
......
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
View file @ a515abd7
......@@ -66,6 +66,7 @@
#include "cxgb4.h"
#include "t4_regs.h"
#include "t4_values.h"
#include "t4_msg.h"
#include "t4fw_api.h"
#include "cxgb4_dcb.h"
......@@ -358,8 +359,8 @@ MODULE_PARM_DESC(select_queue,
*/
enum {
TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
TP_VLAN_PRI_MAP_FIRST = FCOE_S,
TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_S,
};
static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
......@@ -833,11 +834,11 @@ static void disable_msi(struct adapter *adapter)
static irqreturn_t t4_nondata_intr(int irq, void *cookie)
{
struct adapter *adap = cookie;
u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
if (v & PFSW) {
if (v & PFSW_F) {
adap->swintr = 1;
t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
}
t4_slow_intr_handler(adap);
return IRQ_HANDLED;
......@@ -1050,9 +1051,9 @@ static void enable_rx(struct adapter *adap)
if (q->handler)
napi_enable(&q->napi);
/* 0-increment GTS to start the timer and enable interrupts */
t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
SEINTARM(q->intr_params) |
INGRESSQID(q->cntxt_id));
t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
SEINTARM_V(q->intr_params) |
INGRESSQID_V(q->cntxt_id));
}
}
......@@ -1176,10 +1177,10 @@ freeout: t4_free_sge_resources(adap);
}
t4_write_reg(adap, is_t4(adap->params.chip) ?
MPS_TRC_RSS_CONTROL :
MPS_T5_TRC_RSS_CONTROL,
RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
MPS_TRC_RSS_CONTROL_A :
MPS_T5_TRC_RSS_CONTROL_A,
RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
return 0;
}
......@@ -1589,9 +1590,9 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
data += sizeof(struct queue_port_stats) / sizeof(u64);
if (!is_t4(adapter->params.chip)) {
t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7));
val1 = t4_read_reg(adapter, SGE_STAT_TOTAL_A);
val2 = t4_read_reg(adapter, SGE_STAT_MATCH_A);
*data = val1 - val2;
data++;
*data = val2;
......@@ -3600,14 +3601,14 @@ unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
struct adapter *adap = netdev2adap(dev);
u32 v1, v2, lp_count, hp_count;
v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
if (is_t4(adap->params.chip)) {
lp_count = G_LP_COUNT(v1);
hp_count = G_HP_COUNT(v1);
lp_count = LP_COUNT_G(v1);
hp_count = HP_COUNT_G(v1);
} else {
lp_count = G_LP_COUNT_T5(v1);
hp_count = G_HP_COUNT_T5(v2);
lp_count = LP_COUNT_T5_G(v1);
hp_count = HP_COUNT_T5_G(v2);
}
return lpfifo ? lp_count : hp_count;
}
......@@ -3653,10 +3654,10 @@ void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
{
struct adapter *adap = netdev2adap(dev);
t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
HPZ3(pgsz_order[3]));
t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
HPZ3_V(pgsz_order[3]));
}
EXPORT_SYMBOL(cxgb4_iscsi_init);
......@@ -3666,14 +3667,14 @@ int cxgb4_flush_eq_cache(struct net_device *dev)
int ret;
ret = t4_fwaddrspace_write(adap, adap->mbox,
0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
0xe1000000 + SGE_CTXT_CMD_A, 0x20000000);
return ret;
}
EXPORT_SYMBOL(cxgb4_flush_eq_cache);
static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
{
u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
__be64 indices;
int ret;
......@@ -3702,14 +3703,20 @@ int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
if (pidx != hw_pidx) {
u16 delta;
u32 val;
if (pidx >= hw_pidx)
delta = pidx - hw_pidx;
else
delta = size - hw_pidx + pidx;
if (is_t4(adap->params.chip))
val = PIDX_V(delta);
else
val = PIDX_T5_V(delta);
wmb();
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
QID(qid) | PIDX(delta));
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
QID_V(qid) | val);
}
out:
return ret;
......@@ -3721,8 +3728,8 @@ void cxgb4_disable_db_coalescing(struct net_device *dev)
struct adapter *adap;
adap = netdev2adap(dev);
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
F_NOCOALESCE);
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F,
NOCOALESCE_F);
}
EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
......@@ -3731,7 +3738,7 @@ void cxgb4_enable_db_coalescing(struct net_device *dev)
struct adapter *adap;
adap = netdev2adap(dev);
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F, 0);
}
EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
......@@ -3809,8 +3816,8 @@ u64 cxgb4_read_sge_timestamp(struct net_device *dev)
struct adapter *adap;
adap = netdev2adap(dev);
lo = t4_read_reg(adap, SGE_TIMESTAMP_LO);
hi = GET_TSVAL(t4_read_reg(adap, SGE_TIMESTAMP_HI));
lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
return ((u64)hi << 32) | (u64)lo;
}
......@@ -3870,14 +3877,14 @@ static void drain_db_fifo(struct adapter *adap, int usecs)
u32 v1, v2, lp_count, hp_count;
do {
v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
if (is_t4(adap->params.chip)) {
lp_count = G_LP_COUNT(v1);
hp_count = G_HP_COUNT(v1);
lp_count = LP_COUNT_G(v1);
hp_count = HP_COUNT_G(v1);
} else {
lp_count = G_LP_COUNT_T5(v1);
hp_count = G_HP_COUNT_T5(v2);
lp_count = LP_COUNT_T5_G(v1);
hp_count = HP_COUNT_T5_G(v2);
}
if (lp_count == 0 && hp_count == 0)
......@@ -3904,8 +3911,8 @@ static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
* are committed before we tell HW about them.
*/
wmb();
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
q->db_pidx_inc = 0;
}
q->db_disabled = 0;
......@@ -3952,9 +3959,9 @@ static void process_db_full(struct work_struct *work)
drain_db_fifo(adap, dbfifo_drain_delay);
enable_dbs(adap);
notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
t4_set_reg_field(adap, SGE_INT_ENABLE3,
DBFIFO_HP_INT | DBFIFO_LP_INT,
DBFIFO_HP_INT | DBFIFO_LP_INT);
t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
}
static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
......@@ -3968,14 +3975,20 @@ static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
goto out;
if (q->db_pidx != hw_pidx) {
u16 delta;
u32 val;
if (q->db_pidx >= hw_pidx)
delta = q->db_pidx - hw_pidx;
else
delta = q->size - hw_pidx + q->db_pidx;
if (is_t4(adap->params.chip))
val = PIDX_V(delta);
else
val = PIDX_T5_V(delta);
wmb();
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
QID(q->cntxt_id) | PIDX(delta));
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
QID_V(q->cntxt_id) | val);
}
out:
q->db_disabled = 0;
......@@ -4024,14 +4037,14 @@ static void process_db_drop(struct work_struct *work)
dev_err(adap->pdev_dev, "doorbell drop recovery: "
"qid=%d, pidx_inc=%d\n", qid, pidx_inc);
else
writel(PIDX_T5(pidx_inc) | QID(bar2_qid),
writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
/* Re-enable BAR2 WC */
t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
}
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
}
void t4_db_full(struct adapter *adap)
......@@ -4039,8 +4052,8 @@ void t4_db_full(struct adapter *adap)
if (is_t4(adap->params.chip)) {
disable_dbs(adap);
notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
t4_set_reg_field(adap, SGE_INT_ENABLE3,
DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
queue_work(adap->workq, &adap->db_full_task);
}
}
......@@ -4081,7 +4094,7 @@ static void uld_attach(struct adapter *adap, unsigned int uld)
lli.nports = adap->params.nports;
lli.wr_cred = adap->params.ofldq_wr_cred;
lli.adapter_type = adap->params.chip;
lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
lli.udb_density = 1 << adap->params.sge.eq_qpp;
lli.ucq_density = 1 << adap->params.sge.iq_qpp;
......@@ -4089,8 +4102,8 @@ static void uld_attach(struct adapter *adap, unsigned int uld)
/* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
for (i = 0; i < NCHAN; i++)
lli.tx_modq[i] = i;
lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
lli.fw_vers = adap->params.fw_vers;
lli.dbfifo_int_thresh = dbfifo_int_thresh;
lli.sge_ingpadboundary = adap->sge.fl_align;
......@@ -4567,13 +4580,13 @@ int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
f->fs.val.lip[i] = val[i];
f->fs.mask.lip[i] = ~0;
}
if (adap->params.tp.vlan_pri_map & F_PORT) {
if (adap->params.tp.vlan_pri_map & PORT_F) {
f->fs.val.iport = port;
f->fs.mask.iport = mask;
}
}
if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
f->fs.val.proto = IPPROTO_TCP;
f->fs.mask.proto = ~0;
}
......@@ -4783,7 +4796,7 @@ static const struct net_device_ops cxgb4_netdev_ops = {
void t4_fatal_err(struct adapter *adap)
{
t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
t4_intr_disable(adap);
dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
}
......@@ -4858,16 +4871,16 @@ static void setup_memwin(struct adapter *adap)
mem_win2_base = MEMWIN2_BASE_T5;
mem_win2_aperture = MEMWIN2_APERTURE_T5;
}
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
mem_win0_base | BIR(0) |
WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
mem_win1_base | BIR(0) |
WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
mem_win2_base | BIR(0) |
WINDOW(ilog2(mem_win2_aperture) - 10));
t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 0),
mem_win0_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN0_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 1),
mem_win1_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN1_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2),
mem_win2_base | BIR_V(0) |
WINDOW_V(ilog2(mem_win2_aperture) - 10));
t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2));
}
static void setup_memwin_rdma(struct adapter *adap)
......@@ -4881,13 +4894,13 @@ static void setup_memwin_rdma(struct adapter *adap)
start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
t4_write_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
start | BIR(1) | WINDOW(ilog2(sz_kb)));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
t4_write_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
adap->vres.ocq.start);
t4_read_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
}
}
......@@ -4936,38 +4949,38 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
t4_sge_init(adap);
/* tweak some settings */
t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
v = t4_read_reg(adap, TP_PIO_DATA);
t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
v = t4_read_reg(adap, TP_PIO_DATA_A);
t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
/* first 4 Tx modulation queues point to consecutive Tx channels */
adap->params.tp.tx_modq_map = 0xE4;
t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
/* associate each Tx modulation queue with consecutive Tx channels */
v = 0x84218421;
t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
&v, 1, A_TP_TX_SCHED_HDR);
t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
&v, 1, A_TP_TX_SCHED_FIFO);
t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
&v, 1, A_TP_TX_SCHED_PCMD);
t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
&v, 1, TP_TX_SCHED_HDR_A);
t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
&v, 1, TP_TX_SCHED_FIFO_A);
t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
&v, 1, TP_TX_SCHED_PCMD_A);
#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
if (is_offload(adap)) {
t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
}
/* get basic stuff going */
......@@ -5013,16 +5026,16 @@ static int adap_init0_tweaks(struct adapter *adapter)
rx_dma_offset);
rx_dma_offset = 2;
}
t4_set_reg_field(adapter, SGE_CONTROL,
PKTSHIFT_MASK,
PKTSHIFT(rx_dma_offset));
t4_set_reg_field(adapter, SGE_CONTROL_A,
PKTSHIFT_V(PKTSHIFT_M),
PKTSHIFT_V(rx_dma_offset));
/*
* Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
* adds the pseudo header itself.
*/
t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
CSUM_HAS_PSEUDO_HDR, 0);
t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
CSUM_HAS_PSEUDO_HDR_F, 0);
return 0;
}
......@@ -5046,7 +5059,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
*/
if (reset) {
ret = t4_fw_reset(adapter, adapter->mbox,
PIORSTMODE | PIORST);
PIORSTMODE_F | PIORST_F);
if (ret < 0)
goto bye;
}
......@@ -5251,7 +5264,7 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
*/
if (reset) {
ret = t4_fw_reset(adapter, adapter->mbox,
PIORSTMODE | PIORST);
PIORSTMODE_F | PIORST_F);
if (ret < 0)
goto bye;
}
......@@ -5332,8 +5345,7 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
s->counter_val[0] = 1;
for (i = 1; i < SGE_NCOUNTERS; i++)
s->counter_val[i] = min(intr_cnt[i - 1],
THRESHOLD_0_GET(THRESHOLD_0_MASK));
s->counter_val[i] = min(intr_cnt[i - 1], THRESHOLD_0_M);
t4_sge_init(adapter);
#ifdef CONFIG_PCI_IOV
......@@ -5389,34 +5401,34 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
case 0:
/* compressed filter field not enabled */
break;
case FCOE_MASK:
case FCOE_F:
bits += 1;
break;
case PORT_MASK:
case PORT_F:
bits += 3;
break;
case VNIC_ID_MASK:
case VNIC_F:
bits += 17;
break;
case VLAN_MASK:
case VLAN_F:
bits += 17;
break;
case TOS_MASK:
case TOS_F:
bits += 8;
break;
case PROTOCOL_MASK:
case PROTOCOL_F:
bits += 8;
break;
case ETHERTYPE_MASK:
case ETHERTYPE_F:
bits += 16;
break;
case MACMATCH_MASK:
case MACMATCH_F:
bits += 9;
break;
case MPSHITTYPE_MASK:
case MPSHITTYPE_F:
bits += 3;
break;
case FRAGMENTATION_MASK:
case FRAGMENTATION_F:
bits += 1;
break;
}
......@@ -5430,8 +5442,8 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
}
}
v = tp_vlan_pri_map;
t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
&v, 1, TP_VLAN_PRI_MAP);
t4_write_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
&v, 1, TP_VLAN_PRI_MAP_A);
/*
* We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
......@@ -5444,17 +5456,17 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
* performance impact).
*/
if (tp_vlan_pri_map)
t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
FIVETUPLELOOKUP_MASK,
FIVETUPLELOOKUP_MASK);
t4_set_reg_field(adapter, TP_GLOBAL_CONFIG_A,
FIVETUPLELOOKUP_V(FIVETUPLELOOKUP_M),
FIVETUPLELOOKUP_V(FIVETUPLELOOKUP_M));
/*
* Tweak some settings.
*/
t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
t4_write_reg(adapter, TP_SHIFT_CNT_A, SYNSHIFTMAX_V(6) |
RXTSHIFTMAXR1_V(4) | RXTSHIFTMAXR2_V(15) |
PERSHIFTBACKOFFMAX_V(8) | PERSHIFTMAX_V(8) |
KEEPALIVEMAXR1_V(4) | KEEPALIVEMAXR2_V(9));
/*
* Get basic stuff going by issuing the Firmware Initialize command.
......@@ -6401,7 +6413,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
goto out_unmap_bar0;
/* We control everything through one PF */
func = SOURCEPF_GET(readl(regs + PL_WHOAMI));
func = SOURCEPF_G(readl(regs + PL_WHOAMI_A));
if (func != ent->driver_data) {
iounmap(regs);
pci_disable_device(pdev);
......@@ -6467,9 +6479,11 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
if (!is_t4(adapter->params.chip)) {
s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
s_qpp = (QUEUESPERPAGEPF0_S +
(QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
adapter->fn);
qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
num_seg = PAGE_SIZE / SEGMENT_SIZE;
/* Each segment size is 128B. Write coalescing is enabled only
......
drivers/net/ethernet/chelsio/cxgb4/l2t.c
View file @ a515abd7
......@@ -46,6 +46,7 @@
#include "t4_msg.h"
#include "t4fw_api.h"
#include "t4_regs.h"
#include "t4_values.h"
#define VLAN_NONE 0xfff
......@@ -425,7 +426,7 @@ u64 cxgb4_select_ntuple(struct net_device *dev,
* in the Compressed Filter Tuple.
*/
if (tp->vlan_shift >= 0 && l2t->vlan != VLAN_NONE)
ntuple |= (u64)(F_FT_VLAN_VLD | l2t->vlan) << tp->vlan_shift;
ntuple |= (u64)(FT_VLAN_VLD_F | l2t->vlan) << tp->vlan_shift;
if (tp->port_shift >= 0)
ntuple |= (u64)l2t->lport << tp->port_shift;
......@@ -439,9 +440,9 @@ u64 cxgb4_select_ntuple(struct net_device *dev,
u32 pf = FW_VIID_PFN_G(viid);
u32 vld = FW_VIID_VIVLD_G(viid);
ntuple |= (u64)(V_FT_VNID_ID_VF(vf) |
V_FT_VNID_ID_PF(pf) |
V_FT_VNID_ID_VLD(vld)) << tp->vnic_shift;
ntuple |= (u64)(FT_VNID_ID_VF_V(vf) |
FT_VNID_ID_PF_V(pf) |
FT_VNID_ID_VLD_V(vld)) << tp->vnic_shift;
}
return ntuple;
......
drivers/net/ethernet/chelsio/cxgb4/sge.c
View file @ a515abd7
......@@ -45,6 +45,7 @@
#include <net/tcp.h>
#include "cxgb4.h"
#include "t4_regs.h"
#include "t4_values.h"
#include "t4_msg.h"
#include "t4fw_api.h"
......@@ -521,10 +522,12 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
{
u32 val;
if (q->pend_cred >= 8) {
val = PIDX(q->pend_cred / 8);
if (!is_t4(adap->params.chip))
val |= DBTYPE(1);
val |= DBPRIO(1);
if (is_t4(adap->params.chip))
val = PIDX_V(q->pend_cred / 8);
else
val = PIDX_T5_V(q->pend_cred / 8) |
DBTYPE_F;
val |= DBPRIO_F;
wmb();
/* If we don't have access to the new User Doorbell (T5+), use
......@@ -532,10 +535,10 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
* mechanism.
*/
if (unlikely(q->bar2_addr == NULL)) {
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
val | QID(q->cntxt_id));
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
val | QID_V(q->cntxt_id));
} else {
writel(val | QID(q->bar2_qid),
writel(val | QID_V(q->bar2_qid),
q->bar2_addr + SGE_UDB_KDOORBELL);
/* This Write memory Barrier will force the write to
......@@ -884,7 +887,7 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
* doorbell mechanism; otherwise use the new BAR2 mechanism.
*/
if (unlikely(q->bar2_addr == NULL)) {
u32 val = PIDX(n);
u32 val = PIDX_V(n);
unsigned long flags;
/* For T4 we need to participate in the Doorbell Recovery
......@@ -892,14 +895,14 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
*/
spin_lock_irqsave(&q->db_lock, flags);
if (!q->db_disabled)
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
QID(q->cntxt_id) | val);
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
QID_V(q->cntxt_id) | val);
else
q->db_pidx_inc += n;
q->db_pidx = q->pidx;
spin_unlock_irqrestore(&q->db_lock, flags);
} else {
u32 val = PIDX_T5(n);
u32 val = PIDX_T5_V(n);
/* T4 and later chips share the same PIDX field offset within
* the doorbell, but T5 and later shrank the field in order to
......@@ -907,7 +910,7 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
* large in the first place (14 bits) so we just use the T5
* and later limits and warn if a Queue ID is too large.
*/
WARN_ON(val & DBPRIO(1));
WARN_ON(val & DBPRIO_F);
/* If we're only writing a single TX Descriptor and we can use
* Inferred QID registers, we can use the Write Combining
......@@ -923,7 +926,7 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
(q->bar2_addr + SGE_UDB_WCDOORBELL),
wr);
} else {
writel(val | QID(q->bar2_qid),
writel(val | QID_V(q->bar2_qid),
q->bar2_addr + SGE_UDB_KDOORBELL);
}
......@@ -2001,16 +2004,16 @@ static int napi_rx_handler(struct napi_struct *napi, int budget)
} else
params = QINTR_TIMER_IDX(7);
val = CIDXINC(work_done) | SEINTARM(params);
val = CIDXINC_V(work_done) | SEINTARM_V(params);
/* If we don't have access to the new User GTS (T5+), use the old
* doorbell mechanism; otherwise use the new BAR2 mechanism.
*/
if (unlikely(q->bar2_addr == NULL)) {
t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS),
val | INGRESSQID((u32)q->cntxt_id));
t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),
val | INGRESSQID_V((u32)q->cntxt_id));
} else {
writel(val | INGRESSQID(q->bar2_qid),
writel(val | INGRESSQID_V(q->bar2_qid),
q->bar2_addr + SGE_UDB_GTS);
wmb();
}
......@@ -2056,16 +2059,16 @@ static unsigned int process_intrq(struct adapter *adap)
rspq_next(q);
}
val = CIDXINC(credits) | SEINTARM(q->intr_params);
val = CIDXINC_V(credits) | SEINTARM_V(q->intr_params);
/* If we don't have access to the new User GTS (T5+), use the old
* doorbell mechanism; otherwise use the new BAR2 mechanism.
*/
if (unlikely(q->bar2_addr == NULL)) {
t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
val | INGRESSQID(q->cntxt_id));
t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
val | INGRESSQID_V(q->cntxt_id));
} else {
writel(val | INGRESSQID(q->bar2_qid),
writel(val | INGRESSQID_V(q->bar2_qid),
q->bar2_addr + SGE_UDB_GTS);
wmb();
}
......@@ -2095,7 +2098,7 @@ static irqreturn_t t4_intr_intx(int irq, void *cookie)
{
struct adapter *adap = cookie;
t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI), 0);
t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);
if (t4_slow_intr_handler(adap) | process_intrq(adap))
return IRQ_HANDLED;
return IRQ_NONE; /* probably shared interrupt */
......@@ -2142,9 +2145,9 @@ static void sge_rx_timer_cb(unsigned long data)
}
}
t4_write_reg(adap, SGE_DEBUG_INDEX, 13);
idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH);
idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
t4_write_reg(adap, SGE_DEBUG_INDEX_A, 13);
idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH_A);
idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
for (i = 0; i < 2; i++) {
u32 debug0, debug11;
......@@ -2188,12 +2191,12 @@ static void sge_rx_timer_cb(unsigned long data)
/* Read and save the SGE IDMA State and Queue ID information.
* We do this every time in case it changes across time ...
*/
t4_write_reg(adap, SGE_DEBUG_INDEX, 0);
debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
t4_write_reg(adap, SGE_DEBUG_INDEX_A, 0);
debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
t4_write_reg(adap, SGE_DEBUG_INDEX, 11);
debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
t4_write_reg(adap, SGE_DEBUG_INDEX_A, 11);
debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n",
......@@ -2770,8 +2773,8 @@ static int t4_sge_init_soft(struct adapter *adap)
* process_responses() and that only packet data is going to the
* Free Lists.
*/
if ((t4_read_reg(adap, SGE_CONTROL) & RXPKTCPLMODE_MASK) !=
RXPKTCPLMODE(X_RXPKTCPLMODE_SPLIT)) {
if ((t4_read_reg(adap, SGE_CONTROL_A) & RXPKTCPLMODE_F) !=
RXPKTCPLMODE_V(RXPKTCPLMODE_SPLIT_X)) {
dev_err(adap->pdev_dev, "bad SGE CPL MODE\n");
return -EINVAL;
}
......@@ -2785,7 +2788,7 @@ static int t4_sge_init_soft(struct adapter *adap)
* XXX meet our needs!
*/
#define READ_FL_BUF(x) \
t4_read_reg(adap, SGE_FL_BUFFER_SIZE0+(x)*sizeof(u32))
t4_read_reg(adap, SGE_FL_BUFFER_SIZE0_A+(x)*sizeof(u32))
fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF);
fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF);
......@@ -2823,27 +2826,27 @@ static int t4_sge_init_soft(struct adapter *adap)
* Retrieve our RX interrupt holdoff timer values and counter
* threshold values from the SGE parameters.
*/
timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1);
timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3);
timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5);
timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A);
timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A);
timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A);
s->timer_val[0] = core_ticks_to_us(adap,
TIMERVALUE0_GET(timer_value_0_and_1));
TIMERVALUE0_G(timer_value_0_and_1));
s->timer_val[1] = core_ticks_to_us(adap,
TIMERVALUE1_GET(timer_value_0_and_1));
TIMERVALUE1_G(timer_value_0_and_1));
s->timer_val[2] = core_ticks_to_us(adap,
TIMERVALUE2_GET(timer_value_2_and_3));
TIMERVALUE2_G(timer_value_2_and_3));
s->timer_val[3] = core_ticks_to_us(adap,
TIMERVALUE3_GET(timer_value_2_and_3));
TIMERVALUE3_G(timer_value_2_and_3));
s->timer_val[4] = core_ticks_to_us(adap,
TIMERVALUE4_GET(timer_value_4_and_5));
TIMERVALUE4_G(timer_value_4_and_5));
s->timer_val[5] = core_ticks_to_us(adap,
TIMERVALUE5_GET(timer_value_4_and_5));
TIMERVALUE5_G(timer_value_4_and_5));
ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD);
s->counter_val[0] = THRESHOLD_0_GET(ingress_rx_threshold);
s->counter_val[1] = THRESHOLD_1_GET(ingress_rx_threshold);
s->counter_val[2] = THRESHOLD_2_GET(ingress_rx_threshold);
s->counter_val[3] = THRESHOLD_3_GET(ingress_rx_threshold);
ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A);
s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
s->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold);
s->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold);
s->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold);
return 0;
}
......@@ -2856,29 +2859,28 @@ static int t4_sge_init_hard(struct adapter *adap)
* Set up our basic SGE mode to deliver CPL messages to our Ingress
* Queue and Packet Date to the Free List.
*/
t4_set_reg_field(adap, SGE_CONTROL, RXPKTCPLMODE_MASK,
RXPKTCPLMODE_MASK);
t4_set_reg_field(adap, SGE_CONTROL_A, RXPKTCPLMODE_F, RXPKTCPLMODE_F);
/*
* Set up to drop DOORBELL writes when the DOORBELL FIFO overflows
* and generate an interrupt when this occurs so we can recover.
*/
if (is_t4(adap->params.chip)) {
t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
V_HP_INT_THRESH(M_HP_INT_THRESH) |
V_LP_INT_THRESH(M_LP_INT_THRESH),
V_HP_INT_THRESH(dbfifo_int_thresh) |
V_LP_INT_THRESH(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS_A,
HP_INT_THRESH_V(HP_INT_THRESH_M) |
LP_INT_THRESH_V(LP_INT_THRESH_M),
HP_INT_THRESH_V(dbfifo_int_thresh) |
LP_INT_THRESH_V(dbfifo_int_thresh));
} else {
t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
V_LP_INT_THRESH_T5(M_LP_INT_THRESH_T5),
V_LP_INT_THRESH_T5(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS2,
V_HP_INT_THRESH_T5(M_HP_INT_THRESH_T5),
V_HP_INT_THRESH_T5(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS_A,
LP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M),
LP_INT_THRESH_T5_V(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS2_A,
HP_INT_THRESH_T5_V(HP_INT_THRESH_T5_M),
HP_INT_THRESH_T5_V(dbfifo_int_thresh));
}
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP,
F_ENABLE_DROP);
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F,
ENABLE_DROP_F);
/*
* SGE_FL_BUFFER_SIZE0 (RX_SMALL_PG_BUF) is set up by
......@@ -2887,31 +2889,31 @@ static int t4_sge_init_hard(struct adapter *adap)
s->fl_pg_order = FL_PG_ORDER;
if (s->fl_pg_order)
t4_write_reg(adap,
SGE_FL_BUFFER_SIZE0+RX_LARGE_PG_BUF*sizeof(u32),
SGE_FL_BUFFER_SIZE0_A+RX_LARGE_PG_BUF*sizeof(u32),
PAGE_SIZE << FL_PG_ORDER);
t4_write_reg(adap, SGE_FL_BUFFER_SIZE0+RX_SMALL_MTU_BUF*sizeof(u32),
t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A+RX_SMALL_MTU_BUF*sizeof(u32),
FL_MTU_SMALL_BUFSIZE(adap));
t4_write_reg(adap, SGE_FL_BUFFER_SIZE0+RX_LARGE_MTU_BUF*sizeof(u32),
t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A+RX_LARGE_MTU_BUF*sizeof(u32),
FL_MTU_LARGE_BUFSIZE(adap));
/*
* Note that the SGE Ingress Packet Count Interrupt Threshold and
* Timer Holdoff values must be supplied by our caller.
*/
t4_write_reg(adap, SGE_INGRESS_RX_THRESHOLD,
THRESHOLD_0(s->counter_val[0]) |
THRESHOLD_1(s->counter_val[1]) |
THRESHOLD_2(s->counter_val[2]) |
THRESHOLD_3(s->counter_val[3]));
t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1,
TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[0])) |
TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[1])));
t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3,
TIMERVALUE2(us_to_core_ticks(adap, s->timer_val[2])) |
TIMERVALUE3(us_to_core_ticks(adap, s->timer_val[3])));
t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5,
TIMERVALUE4(us_to_core_ticks(adap, s->timer_val[4])) |
TIMERVALUE5(us_to_core_ticks(adap, s->timer_val[5])));
t4_write_reg(adap, SGE_INGRESS_RX_THRESHOLD_A,
THRESHOLD_0_V(s->counter_val[0]) |
THRESHOLD_1_V(s->counter_val[1]) |
THRESHOLD_2_V(s->counter_val[2]) |
THRESHOLD_3_V(s->counter_val[3]));
t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1_A,
TIMERVALUE0_V(us_to_core_ticks(adap, s->timer_val[0])) |
TIMERVALUE1_V(us_to_core_ticks(adap, s->timer_val[1])));
t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3_A,
TIMERVALUE2_V(us_to_core_ticks(adap, s->timer_val[2])) |
TIMERVALUE3_V(us_to_core_ticks(adap, s->timer_val[3])));
t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5_A,
TIMERVALUE4_V(us_to_core_ticks(adap, s->timer_val[4])) |
TIMERVALUE5_V(us_to_core_ticks(adap, s->timer_val[5])));
return 0;
}
......@@ -2927,9 +2929,9 @@ int t4_sge_init(struct adapter *adap)
* Ingress Padding Boundary and Egress Status Page Size are set up by
* t4_fixup_host_params().
*/
sge_control = t4_read_reg(adap, SGE_CONTROL);
s->pktshift = PKTSHIFT_GET(sge_control);
s->stat_len = (sge_control & EGRSTATUSPAGESIZE_MASK) ? 128 : 64;
sge_control = t4_read_reg(adap, SGE_CONTROL_A);
s->pktshift = PKTSHIFT_G(sge_control);
s->stat_len = (sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64;
/* T4 uses a single control field to specify both the PCIe Padding and
* Packing Boundary. T5 introduced the ability to specify these
......@@ -2937,8 +2939,8 @@ int t4_sge_init(struct adapter *adap)
* within Packed Buffer Mode is the maximum of these two
* specifications.
*/
ingpadboundary = 1 << (INGPADBOUNDARY_GET(sge_control) +
X_INGPADBOUNDARY_SHIFT);
ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) +
INGPADBOUNDARY_SHIFT_X);
if (is_t4(adap->params.chip)) {
s->fl_align = ingpadboundary;
} else {
......@@ -2975,11 +2977,11 @@ int t4_sge_init(struct adapter *adap)
* buffers and a new field which only applies to Packed Mode Free List
* buffers.
*/
sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL);
sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A);
if (is_t4(adap->params.chip))
egress_threshold = EGRTHRESHOLD_GET(sge_conm_ctrl);
egress_threshold = EGRTHRESHOLD_G(sge_conm_ctrl);
else
egress_threshold = EGRTHRESHOLDPACKING_GET(sge_conm_ctrl);
egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl);
s->fl_starve_thres = 2*egress_threshold + 1;
setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap);
......
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
View file @ a515abd7
......@@ -35,6 +35,7 @@
#include <linux/delay.h>
#include "cxgb4.h"
#include "t4_regs.h"
#include "t4_values.h"
#include "t4fw_api.h"
/**
......@@ -149,20 +150,20 @@ void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
*/
void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
{
u32 req = ENABLE | FUNCTION(adap->fn) | reg;
u32 req = ENABLE_F | FUNCTION_V(adap->fn) | REGISTER_V(reg);
if (is_t4(adap->params.chip))
req |= F_LOCALCFG;
req |= LOCALCFG_F;
t4_write_reg(adap, PCIE_CFG_SPACE_REQ, req);
*val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA);
t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
*val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
/* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
* Configuration Space read. (None of the other fields matter when
* ENABLE is 0 so a simple register write is easier than a
* read-modify-write via t4_set_reg_field().)
*/
t4_write_reg(adap, PCIE_CFG_SPACE_REQ, 0);
t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
}
/*
......@@ -187,8 +188,8 @@ static void t4_report_fw_error(struct adapter *adap)
};
u32 pcie_fw;
pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
if (pcie_fw & PCIE_FW_ERR)
pcie_fw = t4_read_reg(adap, PCIE_FW_A);
if (pcie_fw & PCIE_FW_ERR_F)
dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
reason[PCIE_FW_EVAL_G(pcie_fw)]);
}
......@@ -264,8 +265,8 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
u64 res;
int i, ms, delay_idx;
const __be64 *p = cmd;
u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA);
u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL);
u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
if ((size & 15) || size > MBOX_LEN)
return -EINVAL;
......@@ -277,9 +278,9 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
if (adap->pdev->error_state != pci_channel_io_normal)
return -EIO;
v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
if (v != MBOX_OWNER_DRV)
return v ? -EBUSY : -ETIMEDOUT;
......@@ -287,7 +288,7 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
for (i = 0; i < size; i += 8)
t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
t4_read_reg(adap, ctl_reg); /* flush write */
delay_idx = 0;
......@@ -303,8 +304,8 @@ int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
mdelay(ms);
v = t4_read_reg(adap, ctl_reg);
if (MBOWNER_GET(v) == MBOX_OWNER_DRV) {
if (!(v & MBMSGVALID)) {
if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
if (!(v & MBMSGVALID_F)) {
t4_write_reg(adap, ctl_reg, 0);
continue;
}
......@@ -350,27 +351,27 @@ int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
u32 mc_bist_status_rdata, mc_bist_data_pattern;
if (is_t4(adap->params.chip)) {
mc_bist_cmd = MC_BIST_CMD;
mc_bist_cmd_addr = MC_BIST_CMD_ADDR;
mc_bist_cmd_len = MC_BIST_CMD_LEN;
mc_bist_status_rdata = MC_BIST_STATUS_RDATA;
mc_bist_data_pattern = MC_BIST_DATA_PATTERN;
mc_bist_cmd = MC_BIST_CMD_A;
mc_bist_cmd_addr = MC_BIST_CMD_ADDR_A;
mc_bist_cmd_len = MC_BIST_CMD_LEN_A;
mc_bist_status_rdata = MC_BIST_STATUS_RDATA_A;
mc_bist_data_pattern = MC_BIST_DATA_PATTERN_A;
} else {
mc_bist_cmd = MC_REG(MC_P_BIST_CMD, idx);
mc_bist_cmd_addr = MC_REG(MC_P_BIST_CMD_ADDR, idx);
mc_bist_cmd_len = MC_REG(MC_P_BIST_CMD_LEN, idx);
mc_bist_status_rdata = MC_REG(MC_P_BIST_STATUS_RDATA, idx);
mc_bist_data_pattern = MC_REG(MC_P_BIST_DATA_PATTERN, idx);
mc_bist_cmd = MC_REG(MC_P_BIST_CMD_A, idx);
mc_bist_cmd_addr = MC_REG(MC_P_BIST_CMD_ADDR_A, idx);
mc_bist_cmd_len = MC_REG(MC_P_BIST_CMD_LEN_A, idx);
mc_bist_status_rdata = MC_REG(MC_P_BIST_STATUS_RDATA_A, idx);
mc_bist_data_pattern = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx);
}
if (t4_read_reg(adap, mc_bist_cmd) & START_BIST)
if (t4_read_reg(adap, mc_bist_cmd) & START_BIST_F)
return -EBUSY;
t4_write_reg(adap, mc_bist_cmd_addr, addr & ~0x3fU);
t4_write_reg(adap, mc_bist_cmd_len, 64);
t4_write_reg(adap, mc_bist_data_pattern, 0xc);
t4_write_reg(adap, mc_bist_cmd, BIST_OPCODE(1) | START_BIST |
BIST_CMD_GAP(1));
i = t4_wait_op_done(adap, mc_bist_cmd, START_BIST, 0, 10, 1);
t4_write_reg(adap, mc_bist_cmd, BIST_OPCODE_V(1) | START_BIST_F |
BIST_CMD_GAP_V(1));
i = t4_wait_op_done(adap, mc_bist_cmd, START_BIST_F, 0, 10, 1);
if (i)
return i;
......@@ -403,31 +404,31 @@ int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata;
if (is_t4(adap->params.chip)) {
edc_bist_cmd = EDC_REG(EDC_BIST_CMD, idx);
edc_bist_cmd_addr = EDC_REG(EDC_BIST_CMD_ADDR, idx);
edc_bist_cmd_len = EDC_REG(EDC_BIST_CMD_LEN, idx);
edc_bist_cmd_data_pattern = EDC_REG(EDC_BIST_DATA_PATTERN,
idx);
edc_bist_status_rdata = EDC_REG(EDC_BIST_STATUS_RDATA,
edc_bist_cmd = EDC_REG(EDC_BIST_CMD_A, idx);
edc_bist_cmd_addr = EDC_REG(EDC_BIST_CMD_ADDR_A, idx);
edc_bist_cmd_len = EDC_REG(EDC_BIST_CMD_LEN_A, idx);
edc_bist_cmd_data_pattern = EDC_REG(EDC_BIST_DATA_PATTERN_A,
idx);
edc_bist_status_rdata = EDC_REG(EDC_BIST_STATUS_RDATA_A,
idx);
} else {
edc_bist_cmd = EDC_REG_T5(EDC_H_BIST_CMD, idx);
edc_bist_cmd_addr = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx);
edc_bist_cmd_len = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx);
edc_bist_cmd = EDC_REG_T5(EDC_H_BIST_CMD_A, idx);
edc_bist_cmd_addr = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx);
edc_bist_cmd_len = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx);
edc_bist_cmd_data_pattern =
EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx);
EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx);
edc_bist_status_rdata =
EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx);
EDC_REG_T5(EDC_H_BIST_STATUS_RDATA_A, idx);
}
if (t4_read_reg(adap, edc_bist_cmd) & START_BIST)
if (t4_read_reg(adap, edc_bist_cmd) & START_BIST_F)
return -EBUSY;
t4_write_reg(adap, edc_bist_cmd_addr, addr & ~0x3fU);
t4_write_reg(adap, edc_bist_cmd_len, 64);
t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
t4_write_reg(adap, edc_bist_cmd,
BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST);
i = t4_wait_op_done(adap, edc_bist_cmd, START_BIST, 0, 10, 1);
BIST_OPCODE_V(1) | BIST_CMD_GAP_V(1) | START_BIST_F);
i = t4_wait_op_done(adap, edc_bist_cmd, START_BIST_F, 0, 10, 1);
if (i)
return i;
......@@ -505,13 +506,13 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
* the address is relative to BAR0.
*/
mem_reg = t4_read_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
win));
mem_aperture = 1 << (GET_WINDOW(mem_reg) + 10);
mem_base = GET_PCIEOFST(mem_reg) << 10;
mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
if (is_t4(adap->params.chip))
mem_base -= adap->t4_bar0;
win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->fn);
/* Calculate our initial PCI-E Memory Window Position and Offset into
* that Window.
......@@ -524,10 +525,10 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
* attempt to use the new value.)
*/
t4_write_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
pos | win_pf);
t4_read_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
/* Transfer data to/from the adapter as long as there's an integral
* number of 32-bit transfers to complete.
......@@ -552,11 +553,11 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
pos += mem_aperture;
offset = 0;
t4_write_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
win), pos | win_pf);
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
win), pos | win_pf);
t4_read_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
win));
}
}
......@@ -760,14 +761,13 @@ static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
if (!byte_cnt || byte_cnt > 4)
return -EINVAL;
if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
return -EBUSY;
cont = cont ? SF_CONT : 0;
lock = lock ? SF_LOCK : 0;
t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1));
ret = t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
if (!ret)
*valp = t4_read_reg(adapter, SF_DATA);
*valp = t4_read_reg(adapter, SF_DATA_A);
return ret;
}
......@@ -788,14 +788,12 @@ static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
{
if (!byte_cnt || byte_cnt > 4)
return -EINVAL;
if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
return -EBUSY;
cont = cont ? SF_CONT : 0;
lock = lock ? SF_LOCK : 0;
t4_write_reg(adapter, SF_DATA, val);
t4_write_reg(adapter, SF_OP, lock |
cont | BYTECNT(byte_cnt - 1) | OP_WR);
return t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
t4_write_reg(adapter, SF_DATA_A, val);
t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
}
/**
......@@ -854,7 +852,7 @@ static int t4_read_flash(struct adapter *adapter, unsigned int addr,
for ( ; nwords; nwords--, data++) {
ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
if (nwords == 1)
t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
if (ret)
return ret;
if (byte_oriented)
......@@ -902,7 +900,7 @@ static int t4_write_flash(struct adapter *adapter, unsigned int addr,
if (ret)
goto unlock;
t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
/* Read the page to verify the write succeeded */
ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
......@@ -918,7 +916,7 @@ static int t4_write_flash(struct adapter *adapter, unsigned int addr,
return 0;
unlock:
t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
return ret;
}
......@@ -1113,7 +1111,7 @@ static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
}
start++;
}
t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
return ret;
}
......@@ -1365,95 +1363,97 @@ static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
static void pcie_intr_handler(struct adapter *adapter)
{
static const struct intr_info sysbus_intr_info[] = {
{ RNPP, "RXNP array parity error", -1, 1 },
{ RPCP, "RXPC array parity error", -1, 1 },
{ RCIP, "RXCIF array parity error", -1, 1 },
{ RCCP, "Rx completions control array parity error", -1, 1 },
{ RFTP, "RXFT array parity error", -1, 1 },
{ RNPP_F, "RXNP array parity error", -1, 1 },
{ RPCP_F, "RXPC array parity error", -1, 1 },
{ RCIP_F, "RXCIF array parity error", -1, 1 },
{ RCCP_F, "Rx completions control array parity error", -1, 1 },
{ RFTP_F, "RXFT array parity error", -1, 1 },
{ 0 }
};
static const struct intr_info pcie_port_intr_info[] = {
{ TPCP, "TXPC array parity error", -1, 1 },
{ TNPP, "TXNP array parity error", -1, 1 },
{ TFTP, "TXFT array parity error", -1, 1 },
{ TCAP, "TXCA array parity error", -1, 1 },
{ TCIP, "TXCIF array parity error", -1, 1 },
{ RCAP, "RXCA array parity error", -1, 1 },
{ OTDD, "outbound request TLP discarded", -1, 1 },
{ RDPE, "Rx data parity error", -1, 1 },
{ TDUE, "Tx uncorrectable data error", -1, 1 },
{ TPCP_F, "TXPC array parity error", -1, 1 },
{ TNPP_F, "TXNP array parity error", -1, 1 },
{ TFTP_F, "TXFT array parity error", -1, 1 },
{ TCAP_F, "TXCA array parity error", -1, 1 },
{ TCIP_F, "TXCIF array parity error", -1, 1 },
{ RCAP_F, "RXCA array parity error", -1, 1 },
{ OTDD_F, "outbound request TLP discarded", -1, 1 },
{ RDPE_F, "Rx data parity error", -1, 1 },
{ TDUE_F, "Tx uncorrectable data error", -1, 1 },
{ 0 }
};
static const struct intr_info pcie_intr_info[] = {
{ MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
{ MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
{ MSIDATAPERR, "MSI data parity error", -1, 1 },
{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
{ PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
{ PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
{ CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
{ DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
{ HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR, "PCI FID parity error", -1, 1 },
{ INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
{ MATAGPERR, "PCI MA tag parity error", -1, 1 },
{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
{ RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
{ RXWRPERR, "PCI Rx write parity error", -1, 1 },
{ RPLPERR, "PCI replay buffer parity error", -1, 1 },
{ PCIESINT, "PCI core secondary fault", -1, 1 },
{ PCIEPINT, "PCI core primary fault", -1, 1 },
{ UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 },
{ MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
{ MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
{ MSIDATAPERR_F, "MSI data parity error", -1, 1 },
{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
{ PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
{ PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
{ CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
{ DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
{ HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR_F, "PCI FID parity error", -1, 1 },
{ INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
{ MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
{ RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
{ RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
{ RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
{ PCIESINT_F, "PCI core secondary fault", -1, 1 },
{ PCIEPINT_F, "PCI core primary fault", -1, 1 },
{ UNXSPLCPLERR_F, "PCI unexpected split completion error",
-1, 0 },
{ 0 }
};
static struct intr_info t5_pcie_intr_info[] = {
{ MSTGRPPERR, "Master Response Read Queue parity error",
{ MSTGRPPERR_F, "Master Response Read Queue parity error",
-1, 1 },
{ MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
{ MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
{ PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
-1, 1 },
{ MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
{ MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
{ PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
{ PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
-1, 1 },
{ PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
{ MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
{ DREQWRPERR_F, "PCI DMA channel write request parity error",
-1, 1 },
{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
{ MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
{ DREQWRPERR, "PCI DMA channel write request parity error",
{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
{ HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR_F, "PCI FID parity error", -1, 1 },
{ VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
{ MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
{ IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
-1, 1 },
{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
{ HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR, "PCI FID parity error", -1, 1 },
{ VFIDPERR, "PCI INTx clear parity error", -1, 1 },
{ MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
{ IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
{ IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
-1, 1 },
{ IPRXDATAGRPPERR, "PCI IP Rx data group parity error", -1, 1 },
{ RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
{ IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
{ TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
{ READRSPERR, "Outbound read error", -1, 0 },
{ RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
{ IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
{ TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
{ READRSPERR_F, "Outbound read error", -1, 0 },
{ 0 }
};
......@@ -1461,15 +1461,15 @@ static void pcie_intr_handler(struct adapter *adapter)
if (is_t4(adapter->params.chip))
fat = t4_handle_intr_status(adapter,
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
sysbus_intr_info) +
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
sysbus_intr_info) +
t4_handle_intr_status(adapter,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
pcie_port_intr_info) +
t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
pcie_port_intr_info) +
t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
pcie_intr_info);
else
fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
t5_pcie_intr_info);
if (fat)
......@@ -1483,11 +1483,11 @@ static void tp_intr_handler(struct adapter *adapter)
{
static const struct intr_info tp_intr_info[] = {
{ 0x3fffffff, "TP parity error", -1, 1 },
{ FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
{ FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
{ 0 }
};
if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info))
if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
t4_fatal_err(adapter);
}
......@@ -1499,102 +1499,107 @@ static void sge_intr_handler(struct adapter *adapter)
u64 v;
static const struct intr_info sge_intr_info[] = {
{ ERR_CPL_EXCEED_IQE_SIZE,
{ ERR_CPL_EXCEED_IQE_SIZE_F,
"SGE received CPL exceeding IQE size", -1, 1 },
{ ERR_INVALID_CIDX_INC,
{ ERR_INVALID_CIDX_INC_F,
"SGE GTS CIDX increment too large", -1, 0 },
{ ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
{ DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
{ DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
{ ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
{ ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,
{ ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
{ DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
{ DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
{ ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
{ ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
"SGE IQID > 1023 received CPL for FL", -1, 0 },
{ ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
{ ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
0 },
{ ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
{ ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
0 },
{ ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
{ ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
0 },
{ ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
{ ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
0 },
{ ERR_ING_CTXT_PRIO,
{ ERR_ING_CTXT_PRIO_F,
"SGE too many priority ingress contexts", -1, 0 },
{ ERR_EGR_CTXT_PRIO,
{ ERR_EGR_CTXT_PRIO_F,
"SGE too many priority egress contexts", -1, 0 },
{ INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
{ EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
{ INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
{ EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
{ 0 }
};
v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) |
((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32);
v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
if (v) {
dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
(unsigned long long)v);
t4_write_reg(adapter, SGE_INT_CAUSE1, v);
t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32);
t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
}
if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) ||
if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info) ||
v != 0)
t4_fatal_err(adapter);
}
#define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
#define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
/*
* CIM interrupt handler.
*/
static void cim_intr_handler(struct adapter *adapter)
{
static const struct intr_info cim_intr_info[] = {
{ PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
{ OBQPARERR, "CIM OBQ parity error", -1, 1 },
{ IBQPARERR, "CIM IBQ parity error", -1, 1 },
{ MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
{ MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
{ TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
{ TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
{ PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
{ CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
{ CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
{ MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
{ MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
{ TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
{ TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
{ 0 }
};
static const struct intr_info cim_upintr_info[] = {
{ RSVDSPACEINT, "CIM reserved space access", -1, 1 },
{ ILLTRANSINT, "CIM illegal transaction", -1, 1 },
{ ILLWRINT, "CIM illegal write", -1, 1 },
{ ILLRDINT, "CIM illegal read", -1, 1 },
{ ILLRDBEINT, "CIM illegal read BE", -1, 1 },
{ ILLWRBEINT, "CIM illegal write BE", -1, 1 },
{ SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
{ SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
{ BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
{ SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
{ SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
{ BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
{ SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
{ SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
{ BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
{ BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
{ SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
{ SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
{ BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
{ BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
{ SGLRDPLINT , "CIM single read from PL space", -1, 1 },
{ SGLWRPLINT , "CIM single write to PL space", -1, 1 },
{ BLKRDPLINT , "CIM block read from PL space", -1, 1 },
{ BLKWRPLINT , "CIM block write to PL space", -1, 1 },
{ REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
{ RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
{ TIMEOUTINT , "CIM PIF timeout", -1, 1 },
{ TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
{ RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
{ ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
{ ILLWRINT_F, "CIM illegal write", -1, 1 },
{ ILLRDINT_F, "CIM illegal read", -1, 1 },
{ ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
{ ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
{ SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
{ SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
{ BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
{ SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
{ SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
{ BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
{ SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
{ SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
{ BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
{ BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
{ SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
{ SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
{ BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
{ BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
{ SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
{ SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
{ BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
{ BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
{ REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
{ RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
{ TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
{ TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
{ 0 }
};
int fat;
if (t4_read_reg(adapter, MA_PCIE_FW) & PCIE_FW_ERR)
if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
t4_report_fw_error(adapter);
fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
cim_intr_info) +
t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE,
t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
cim_upintr_info);
if (fat)
t4_fatal_err(adapter);
......@@ -1611,7 +1616,7 @@ static void ulprx_intr_handler(struct adapter *adapter)
{ 0 }
};
if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info))
if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
t4_fatal_err(adapter);
}
......@@ -1621,19 +1626,19 @@ static void ulprx_intr_handler(struct adapter *adapter)
static void ulptx_intr_handler(struct adapter *adapter)
{
static const struct intr_info ulptx_intr_info[] = {
{ PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
0 },
{ PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
0 },
{ PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
0 },
{ PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
0 },
{ 0xfffffff, "ULPTX parity error", -1, 1 },
{ 0 }
};
if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info))
if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
t4_fatal_err(adapter);
}
......@@ -1643,19 +1648,20 @@ static void ulptx_intr_handler(struct adapter *adapter)
static void pmtx_intr_handler(struct adapter *adapter)
{
static const struct intr_info pmtx_intr_info[] = {
{ PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
{ ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
{ PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 },
{ OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 },
{ ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
{ C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
{ PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
{ ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
{ PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
{ OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
-1, 1 },
{ ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
{ PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
{ 0 }
};
if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info))
if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
t4_fatal_err(adapter);
}
......@@ -1665,16 +1671,17 @@ static void pmtx_intr_handler(struct adapter *adapter)
static void pmrx_intr_handler(struct adapter *adapter)
{
static const struct intr_info pmrx_intr_info[] = {
{ ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
{ PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 },
{ OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 },
{ IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
{ E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
{ ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
{ PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
{ OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
-1, 1 },
{ IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
{ PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
{ 0 }
};
if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info))
if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
t4_fatal_err(adapter);
}
......@@ -1684,16 +1691,16 @@ static void pmrx_intr_handler(struct adapter *adapter)
static void cplsw_intr_handler(struct adapter *adapter)
{
static const struct intr_info cplsw_intr_info[] = {
{ CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
{ CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
{ TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
{ SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
{ CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
{ ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
{ CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
{ CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
{ TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
{ SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
{ CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
{ ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
{ 0 }
};
if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info))
if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
t4_fatal_err(adapter);
}
......@@ -1703,15 +1710,15 @@ static void cplsw_intr_handler(struct adapter *adapter)
static void le_intr_handler(struct adapter *adap)
{
static const struct intr_info le_intr_info[] = {
{ LIPMISS, "LE LIP miss", -1, 0 },
{ LIP0, "LE 0 LIP error", -1, 0 },
{ PARITYERR, "LE parity error", -1, 1 },
{ UNKNOWNCMD, "LE unknown command", -1, 1 },
{ REQQPARERR, "LE request queue parity error", -1, 1 },
{ LIPMISS_F, "LE LIP miss", -1, 0 },
{ LIP0_F, "LE 0 LIP error", -1, 0 },
{ PARITYERR_F, "LE parity error", -1, 1 },
{ UNKNOWNCMD_F, "LE unknown command", -1, 1 },
{ REQQPARERR_F, "LE request queue parity error", -1, 1 },
{ 0 }
};
if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info))
if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, le_intr_info))
t4_fatal_err(adap);
}
......@@ -1725,19 +1732,22 @@ static void mps_intr_handler(struct adapter *adapter)
{ 0 }
};
static const struct intr_info mps_tx_intr_info[] = {
{ TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
{ NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
{ TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
{ TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 },
{ BUBBLE, "MPS Tx underflow", -1, 1 },
{ SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
{ FRMERR, "MPS Tx framing error", -1, 1 },
{ TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
{ NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
{ TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
-1, 1 },
{ TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
-1, 1 },
{ BUBBLE_F, "MPS Tx underflow", -1, 1 },
{ SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
{ FRMERR_F, "MPS Tx framing error", -1, 1 },
{ 0 }
};
static const struct intr_info mps_trc_intr_info[] = {
{ FILTMEM, "MPS TRC filter parity error", -1, 1 },
{ PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
{ MISCPERR, "MPS TRC misc parity error", -1, 1 },
{ FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
{ PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
-1, 1 },
{ MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
{ 0 }
};
static const struct intr_info mps_stat_sram_intr_info[] = {
......@@ -1753,37 +1763,37 @@ static void mps_intr_handler(struct adapter *adapter)
{ 0 }
};
static const struct intr_info mps_cls_intr_info[] = {
{ MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
{ MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
{ HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
{ MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
{ MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
{ HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
{ 0 }
};
int fat;
fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE,
fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
mps_rx_intr_info) +
t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE,
t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
mps_tx_intr_info) +
t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE,
t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
mps_trc_intr_info) +
t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM,
t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
mps_stat_sram_intr_info) +
t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
mps_stat_tx_intr_info) +
t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
mps_stat_rx_intr_info) +
t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE,
t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
mps_cls_intr_info);
t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT |
RXINT | TXINT | STATINT);
t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */
t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
if (fat)
t4_fatal_err(adapter);
}
#define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE)
#define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
ECC_UE_INT_CAUSE_F)
/*
* EDC/MC interrupt handler.
......@@ -1795,40 +1805,40 @@ static void mem_intr_handler(struct adapter *adapter, int idx)
unsigned int addr, cnt_addr, v;
if (idx <= MEM_EDC1) {
addr = EDC_REG(EDC_INT_CAUSE, idx);
cnt_addr = EDC_REG(EDC_ECC_STATUS, idx);
addr = EDC_REG(EDC_INT_CAUSE_A, idx);
cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
} else if (idx == MEM_MC) {
if (is_t4(adapter->params.chip)) {
addr = MC_INT_CAUSE;
cnt_addr = MC_ECC_STATUS;
addr = MC_INT_CAUSE_A;
cnt_addr = MC_ECC_STATUS_A;
} else {
addr = MC_P_INT_CAUSE;
cnt_addr = MC_P_ECC_STATUS;
addr = MC_P_INT_CAUSE_A;
cnt_addr = MC_P_ECC_STATUS_A;
}
} else {
addr = MC_REG(MC_P_INT_CAUSE, 1);
cnt_addr = MC_REG(MC_P_ECC_STATUS, 1);
addr = MC_REG(MC_P_INT_CAUSE_A, 1);
cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
}
v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
if (v & PERR_INT_CAUSE)
if (v & PERR_INT_CAUSE_F)
dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
name[idx]);
if (v & ECC_CE_INT_CAUSE) {
u32 cnt = ECC_CECNT_GET(t4_read_reg(adapter, cnt_addr));
if (v & ECC_CE_INT_CAUSE_F) {
u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
t4_write_reg(adapter, cnt_addr, ECC_CECNT_MASK);
t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
if (printk_ratelimit())
dev_warn(adapter->pdev_dev,
"%u %s correctable ECC data error%s\n",
cnt, name[idx], cnt > 1 ? "s" : "");
}
if (v & ECC_UE_INT_CAUSE)
if (v & ECC_UE_INT_CAUSE_F)
dev_alert(adapter->pdev_dev,
"%s uncorrectable ECC data error\n", name[idx]);
t4_write_reg(adapter, addr, v);
if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE))
if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
t4_fatal_err(adapter);
}
......@@ -1837,26 +1847,26 @@ static void mem_intr_handler(struct adapter *adapter, int idx)
*/
static void ma_intr_handler(struct adapter *adap)
{
u32 v, status = t4_read_reg(adap, MA_INT_CAUSE);
u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
if (status & MEM_PERR_INT_CAUSE) {
if (status & MEM_PERR_INT_CAUSE_F) {
dev_alert(adap->pdev_dev,
"MA parity error, parity status %#x\n",
t4_read_reg(adap, MA_PARITY_ERROR_STATUS));
t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
if (is_t5(adap->params.chip))
dev_alert(adap->pdev_dev,
"MA parity error, parity status %#x\n",
t4_read_reg(adap,
MA_PARITY_ERROR_STATUS2));
MA_PARITY_ERROR_STATUS2_A));
}
if (status & MEM_WRAP_INT_CAUSE) {
v = t4_read_reg(adap, MA_INT_WRAP_STATUS);
if (status & MEM_WRAP_INT_CAUSE_F) {
v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
dev_alert(adap->pdev_dev, "MA address wrap-around error by "
"client %u to address %#x\n",
MEM_WRAP_CLIENT_NUM_GET(v),
MEM_WRAP_ADDRESS_GET(v) << 4);
MEM_WRAP_CLIENT_NUM_G(v),
MEM_WRAP_ADDRESS_G(v) << 4);
}
t4_write_reg(adap, MA_INT_CAUSE, status);
t4_write_reg(adap, MA_INT_CAUSE_A, status);
t4_fatal_err(adap);
}
......@@ -1866,13 +1876,13 @@ static void ma_intr_handler(struct adapter *adap)
static void smb_intr_handler(struct adapter *adap)
{
static const struct intr_info smb_intr_info[] = {
{ MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
{ MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
{ SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
{ MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
{ MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
{ SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
{ 0 }
};
if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info))
if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
t4_fatal_err(adap);
}
......@@ -1882,14 +1892,14 @@ static void smb_intr_handler(struct adapter *adap)
static void ncsi_intr_handler(struct adapter *adap)
{
static const struct intr_info ncsi_intr_info[] = {
{ CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
{ MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
{ TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
{ RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
{ CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
{ MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
{ TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
{ RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
{ 0 }
};
if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info))
if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
t4_fatal_err(adap);
}
......@@ -1901,23 +1911,23 @@ static void xgmac_intr_handler(struct adapter *adap, int port)
u32 v, int_cause_reg;
if (is_t4(adap->params.chip))
int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE);
int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
else
int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE);
int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
v = t4_read_reg(adap, int_cause_reg);
v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR;
v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
if (!v)
return;
if (v & TXFIFO_PRTY_ERR)
if (v & TXFIFO_PRTY_ERR_F)
dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
port);
if (v & RXFIFO_PRTY_ERR)
if (v & RXFIFO_PRTY_ERR_F)
dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
port);
t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v);
t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
t4_fatal_err(adap);
}
......@@ -1927,19 +1937,19 @@ static void xgmac_intr_handler(struct adapter *adap, int port)
static void pl_intr_handler(struct adapter *adap)
{
static const struct intr_info pl_intr_info[] = {
{ FATALPERR, "T4 fatal parity error", -1, 1 },
{ PERRVFID, "PL VFID_MAP parity error", -1, 1 },
{ FATALPERR_F, "T4 fatal parity error", -1, 1 },
{ PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
{ 0 }
};
if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info))
if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
t4_fatal_err(adap);
}
#define PF_INTR_MASK (PFSW)
#define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \
CPL_SWITCH | SGE | ULP_TX)
#define PF_INTR_MASK (PFSW_F)
#define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
CPL_SWITCH_F | SGE_F | ULP_TX_F)
/**
* t4_slow_intr_handler - control path interrupt handler
......@@ -1951,60 +1961,60 @@ static void pl_intr_handler(struct adapter *adap)
*/
int t4_slow_intr_handler(struct adapter *adapter)
{
u32 cause = t4_read_reg(adapter, PL_INT_CAUSE);
u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
if (!(cause & GLBL_INTR_MASK))
return 0;
if (cause & CIM)
if (cause & CIM_F)
cim_intr_handler(adapter);
if (cause & MPS)
if (cause & MPS_F)
mps_intr_handler(adapter);
if (cause & NCSI)
if (cause & NCSI_F)
ncsi_intr_handler(adapter);
if (cause & PL)
if (cause & PL_F)
pl_intr_handler(adapter);
if (cause & SMB)
if (cause & SMB_F)
smb_intr_handler(adapter);
if (cause & XGMAC0)
if (cause & XGMAC0_F)
xgmac_intr_handler(adapter, 0);
if (cause & XGMAC1)
if (cause & XGMAC1_F)
xgmac_intr_handler(adapter, 1);
if (cause & XGMAC_KR0)
if (cause & XGMAC_KR0_F)
xgmac_intr_handler(adapter, 2);
if (cause & XGMAC_KR1)
if (cause & XGMAC_KR1_F)
xgmac_intr_handler(adapter, 3);
if (cause & PCIE)
if (cause & PCIE_F)
pcie_intr_handler(adapter);
if (cause & MC)
if (cause & MC_F)
mem_intr_handler(adapter, MEM_MC);
if (!is_t4(adapter->params.chip) && (cause & MC1))
if (!is_t4(adapter->params.chip) && (cause & MC1_S))
mem_intr_handler(adapter, MEM_MC1);
if (cause & EDC0)
if (cause & EDC0_F)
mem_intr_handler(adapter, MEM_EDC0);
if (cause & EDC1)
if (cause & EDC1_F)
mem_intr_handler(adapter, MEM_EDC1);
if (cause & LE)
if (cause & LE_F)
le_intr_handler(adapter);
if (cause & TP)
if (cause & TP_F)
tp_intr_handler(adapter);
if (cause & MA)
if (cause & MA_F)
ma_intr_handler(adapter);
if (cause & PM_TX)
if (cause & PM_TX_F)
pmtx_intr_handler(adapter);
if (cause & PM_RX)
if (cause & PM_RX_F)
pmrx_intr_handler(adapter);
if (cause & ULP_RX)
if (cause & ULP_RX_F)
ulprx_intr_handler(adapter);
if (cause & CPL_SWITCH)
if (cause & CPL_SWITCH_F)
cplsw_intr_handler(adapter);
if (cause & SGE)
if (cause & SGE_F)
sge_intr_handler(adapter);
if (cause & ULP_TX)
if (cause & ULP_TX_F)
ulptx_intr_handler(adapter);
/* Clear the interrupts just processed for which we are the master. */
t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK);
(void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */
t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
(void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
return 1;
}
......@@ -2023,19 +2033,19 @@ int t4_slow_intr_handler(struct adapter *adapter)
*/
void t4_intr_enable(struct adapter *adapter)
{
u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE |
ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 |
ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 |
ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 |
ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |
ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |
ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR |
DBFIFO_HP_INT | DBFIFO_LP_INT |
EGRESS_SIZE_ERR);
t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK);
t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf);
u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A));
t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
ERR_DROPPED_DB_F | ERR_DATA_CPL_ON_HIGH_QID1_F |
ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F |
DBFIFO_HP_INT_F | DBFIFO_LP_INT_F |
EGRESS_SIZE_ERR_F);
t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
}
/**
......@@ -2048,10 +2058,10 @@ void t4_intr_enable(struct adapter *adapter)
*/
void t4_intr_disable(struct adapter *adapter)
{
u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A));
t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0);
t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0);
t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
}
/**
......@@ -2178,23 +2188,23 @@ int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
struct tp_tcp_stats *v6)
{
u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1];
u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
#define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST)
#define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
#define STAT(x) val[STAT_IDX(x)]
#define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
if (v4) {
t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST);
t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
v4->tcpOutRsts = STAT(OUT_RST);
v4->tcpInSegs = STAT64(IN_SEG);
v4->tcpOutSegs = STAT64(OUT_SEG);
v4->tcpRetransSegs = STAT64(RXT_SEG);
}
if (v6) {
t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST);
t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
v6->tcpOutRsts = STAT(OUT_RST);
v6->tcpInSegs = STAT64(IN_SEG);
v6->tcpOutSegs = STAT64(OUT_SEG);
......@@ -2219,12 +2229,12 @@ void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
int i;
for (i = 0; i < NMTUS; ++i) {
t4_write_reg(adap, TP_MTU_TABLE,
MTUINDEX(0xff) | MTUVALUE(i));
v = t4_read_reg(adap, TP_MTU_TABLE);
mtus[i] = MTUVALUE_GET(v);
t4_write_reg(adap, TP_MTU_TABLE_A,
MTUINDEX_V(0xff) | MTUVALUE_V(i));
v = t4_read_reg(adap, TP_MTU_TABLE_A);
mtus[i] = MTUVALUE_G(v);
if (mtu_log)
mtu_log[i] = MTUWIDTH_GET(v);
mtu_log[i] = MTUWIDTH_G(v);
}
}
......@@ -2240,9 +2250,9 @@ void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
unsigned int mask, unsigned int val)
{
t4_write_reg(adap, TP_PIO_ADDR, addr);
val |= t4_read_reg(adap, TP_PIO_DATA) & ~mask;
t4_write_reg(adap, TP_PIO_DATA, val);
t4_write_reg(adap, TP_PIO_ADDR_A, addr);
val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
t4_write_reg(adap, TP_PIO_DATA_A, val);
}
/**
......@@ -2321,8 +2331,8 @@ void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
if (!(mtu & ((1 << log2) >> 2))) /* round */
log2--;
t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) |
MTUWIDTH(log2) | MTUVALUE(mtu));
t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
for (w = 0; w < NCCTRL_WIN; ++w) {
unsigned int inc;
......@@ -2330,7 +2340,7 @@ void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
CC_MIN_INCR);
t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) |
t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
(w << 16) | (beta[w] << 13) | inc);
}
}
......@@ -2347,7 +2357,7 @@ void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
*/
static unsigned int get_mps_bg_map(struct adapter *adap, int idx)
{
u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL));
u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
if (n == 0)
return idx == 0 ? 0xf : 0;
......@@ -2485,11 +2495,11 @@ void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
if (is_t4(adap->params.chip)) {
mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO);
mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI);
port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2_A);
} else {
mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO);
mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI);
port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2_A);
}
if (addr) {
......@@ -2499,8 +2509,8 @@ void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
t4_write_reg(adap, mag_id_reg_h,
(addr[0] << 8) | addr[1]);
}
t4_set_reg_field(adap, port_cfg_reg, MAGICEN,
addr ? MAGICEN : 0);
t4_set_reg_field(adap, port_cfg_reg, MAGICEN_F,
addr ? MAGICEN_F : 0);
}
/**
......@@ -2525,20 +2535,21 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
u32 port_cfg_reg;
if (is_t4(adap->params.chip))
port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2_A);
else
port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2);
port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2_A);
if (!enable) {
t4_set_reg_field(adap, port_cfg_reg, PATEN, 0);
t4_set_reg_field(adap, port_cfg_reg, PATEN_F, 0);
return 0;
}
if (map > 0xff)
return -EINVAL;
#define EPIO_REG(name) \
(is_t4(adap->params.chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \
T5_PORT_REG(port, MAC_PORT_EPIO_##name))
(is_t4(adap->params.chip) ? \
PORT_REG(port, XGMAC_PORT_EPIO_##name##_A) : \
T5_PORT_REG(port, MAC_PORT_EPIO_##name##_A))
t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
t4_write_reg(adap, EPIO_REG(DATA2), mask1);
......@@ -2550,21 +2561,21 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
/* write byte masks */
t4_write_reg(adap, EPIO_REG(DATA0), mask0);
t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR);
t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i) | EPIOWR_F);
t4_read_reg(adap, EPIO_REG(OP)); /* flush */
if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F)
return -ETIMEDOUT;
/* write CRC */
t4_write_reg(adap, EPIO_REG(DATA0), crc);
t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR);
t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i + 32) | EPIOWR_F);
t4_read_reg(adap, EPIO_REG(OP)); /* flush */
if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F)
return -ETIMEDOUT;
}
#undef EPIO_REG
t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN);
t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2_A), 0, PATEN_F);
return 0;
}
......@@ -2749,9 +2760,9 @@ void t4_sge_decode_idma_state(struct adapter *adapter, int state)
"IDMA_FL_SEND_COMPLETION_TO_IMSG",
};
static const u32 sge_regs[] = {
SGE_DEBUG_DATA_LOW_INDEX_2,
SGE_DEBUG_DATA_LOW_INDEX_3,
SGE_DEBUG_DATA_HIGH_INDEX_10,
SGE_DEBUG_DATA_LOW_INDEX_2_A,
SGE_DEBUG_DATA_LOW_INDEX_3_A,
SGE_DEBUG_DATA_HIGH_INDEX_10_A,
};
const char **sge_idma_decode;
int sge_idma_decode_nstates;
......@@ -2818,7 +2829,7 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
if (ret < 0) {
if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
goto retry;
if (t4_read_reg(adap, MA_PCIE_FW) & PCIE_FW_ERR)
if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
t4_report_fw_error(adap);
return ret;
}
......@@ -2868,8 +2879,8 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
* timeout ... and then retry if we haven't exhausted
* our retries ...
*/
pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
if (!(pcie_fw & (PCIE_FW_ERR|PCIE_FW_INIT))) {
pcie_fw = t4_read_reg(adap, PCIE_FW_A);
if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
if (waiting <= 0) {
if (retries-- > 0)
goto retry;
......@@ -2884,9 +2895,9 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
* report errors preferentially.
*/
if (state) {
if (pcie_fw & PCIE_FW_ERR)
if (pcie_fw & PCIE_FW_ERR_F)
*state = DEV_STATE_ERR;
else if (pcie_fw & PCIE_FW_INIT)
else if (pcie_fw & PCIE_FW_INIT_F)
*state = DEV_STATE_INIT;
}
......@@ -2896,7 +2907,7 @@ int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
* for our caller.
*/
if (master_mbox == PCIE_FW_MASTER_M &&
(pcie_fw & PCIE_FW_MASTER_VLD))
(pcie_fw & PCIE_FW_MASTER_VLD_F))
master_mbox = PCIE_FW_MASTER_G(pcie_fw);
break;
}
......@@ -2985,7 +2996,7 @@ static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
memset(&c, 0, sizeof(c));
INIT_CMD(c, RESET, WRITE);
c.val = htonl(PIORST | PIORSTMODE);
c.val = htonl(PIORST_F | PIORSTMODE_F);
c.halt_pkd = htonl(FW_RESET_CMD_HALT_F);
ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
}
......@@ -3004,8 +3015,8 @@ static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
* rather than a RESET ... if it's new enough to understand that ...
*/
if (ret == 0 || force) {
t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);
t4_set_reg_field(adap, PCIE_FW, PCIE_FW_HALT_F,
t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
PCIE_FW_HALT_F);
}
......@@ -3045,7 +3056,7 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
* doing it automatically, we need to clear the PCIE_FW.HALT
* bit.
*/
t4_set_reg_field(adap, PCIE_FW, PCIE_FW_HALT_F, 0);
t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
/*
* If we've been given a valid mailbox, first try to get the
......@@ -3055,21 +3066,21 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
* hitting the chip with a hammer.
*/
if (mbox <= PCIE_FW_MASTER_M) {
t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
msleep(100);
if (t4_fw_reset(adap, mbox,
PIORST | PIORSTMODE) == 0)
PIORST_F | PIORSTMODE_F) == 0)
return 0;
}
t4_write_reg(adap, PL_RST, PIORST | PIORSTMODE);
t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
msleep(2000);
} else {
int ms;
t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
if (!(t4_read_reg(adap, PCIE_FW) & PCIE_FW_HALT_F))
if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
return 0;
msleep(100);
ms += 100;
......@@ -3148,22 +3159,23 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
unsigned int fl_align_log = fls(fl_align) - 1;
t4_write_reg(adap, SGE_HOST_PAGE_SIZE,
HOSTPAGESIZEPF0(sge_hps) |
HOSTPAGESIZEPF1(sge_hps) |
HOSTPAGESIZEPF2(sge_hps) |
HOSTPAGESIZEPF3(sge_hps) |
HOSTPAGESIZEPF4(sge_hps) |
HOSTPAGESIZEPF5(sge_hps) |
HOSTPAGESIZEPF6(sge_hps) |
HOSTPAGESIZEPF7(sge_hps));
t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
HOSTPAGESIZEPF0_V(sge_hps) |
HOSTPAGESIZEPF1_V(sge_hps) |
HOSTPAGESIZEPF2_V(sge_hps) |
HOSTPAGESIZEPF3_V(sge_hps) |
HOSTPAGESIZEPF4_V(sge_hps) |
HOSTPAGESIZEPF5_V(sge_hps) |
HOSTPAGESIZEPF6_V(sge_hps) |
HOSTPAGESIZEPF7_V(sge_hps));
if (is_t4(adap->params.chip)) {
t4_set_reg_field(adap, SGE_CONTROL,
INGPADBOUNDARY_MASK |
EGRSTATUSPAGESIZE_MASK,
INGPADBOUNDARY(fl_align_log - 5) |
EGRSTATUSPAGESIZE(stat_len != 64));
t4_set_reg_field(adap, SGE_CONTROL_A,
INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
EGRSTATUSPAGESIZE_F,
INGPADBOUNDARY_V(fl_align_log -
INGPADBOUNDARY_SHIFT_X) |
EGRSTATUSPAGESIZE_V(stat_len != 64));
} else {
/* T5 introduced the separation of the Free List Padding and
* Packing Boundaries. Thus, we can select a smaller Padding
......@@ -3193,15 +3205,15 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
fl_align = 64;
fl_align_log = 6;
}
t4_set_reg_field(adap, SGE_CONTROL,
INGPADBOUNDARY_MASK |
EGRSTATUSPAGESIZE_MASK,
INGPADBOUNDARY(INGPCIEBOUNDARY_32B_X) |
EGRSTATUSPAGESIZE(stat_len != 64));
t4_set_reg_field(adap, SGE_CONTROL_A,
INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
EGRSTATUSPAGESIZE_F,
INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X) |
EGRSTATUSPAGESIZE_V(stat_len != 64));
t4_set_reg_field(adap, SGE_CONTROL2_A,
INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
INGPACKBOUNDARY_V(fl_align_log -
INGPACKBOUNDARY_SHIFT_X));
INGPACKBOUNDARY_SHIFT_X));
}
/*
* Adjust various SGE Free List Host Buffer Sizes.
......@@ -3224,15 +3236,15 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
* Default Firmware Configuration File but we need to adjust it for
* this host's cache line size.
*/
t4_write_reg(adap, SGE_FL_BUFFER_SIZE0, page_size);
t4_write_reg(adap, SGE_FL_BUFFER_SIZE2,
(t4_read_reg(adap, SGE_FL_BUFFER_SIZE2) + fl_align-1)
t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
(t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
& ~(fl_align-1));
t4_write_reg(adap, SGE_FL_BUFFER_SIZE3,
(t4_read_reg(adap, SGE_FL_BUFFER_SIZE3) + fl_align-1)
t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
(t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
& ~(fl_align-1));
t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(page_shift - 12));
t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
return 0;
}
......@@ -3917,12 +3929,12 @@ int t4_wait_dev_ready(void __iomem *regs)
{
u32 whoami;
whoami = readl(regs + PL_WHOAMI);
whoami = readl(regs + PL_WHOAMI_A);
if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
return 0;
msleep(500);
whoami = readl(regs + PL_WHOAMI);
whoami = readl(regs + PL_WHOAMI_A);
return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
}
......@@ -3946,7 +3958,7 @@ static int get_flash_params(struct adapter *adap)
ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
if (!ret)
ret = sf1_read(adap, 3, 0, 1, &info);
t4_write_reg(adap, SF_OP, 0); /* unlock SF */
t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
if (ret)
return ret;
......@@ -3969,7 +3981,7 @@ static int get_flash_params(struct adapter *adap)
return -EINVAL;
adap->params.sf_size = 1 << info;
adap->params.sf_fw_start =
t4_read_reg(adap, CIM_BOOT_CFG) & BOOTADDR_MASK;
t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
if (adap->params.sf_size < FLASH_MIN_SIZE)
dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
......@@ -3993,7 +4005,7 @@ int t4_prep_adapter(struct adapter *adapter)
u32 pl_rev;
get_pci_mode(adapter, &adapter->params.pci);
pl_rev = G_REV(t4_read_reg(adapter, PL_REV));
pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
ret = get_flash_params(adapter);
if (ret < 0) {
......@@ -4133,7 +4145,7 @@ int t4_init_sge_params(struct adapter *adapter)
/* Extract the SGE Page Size for our PF.
*/
hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE);
hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
s_hps = (HOSTPAGESIZEPF0_S +
(HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->fn);
sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
......@@ -4142,10 +4154,10 @@ int t4_init_sge_params(struct adapter *adapter)
*/
s_qpp = (QUEUESPERPAGEPF0_S +
(QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->fn);
qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF);
sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_MASK);
qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF);
sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_MASK);
qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
return 0;
}
......@@ -4161,9 +4173,9 @@ int t4_init_tp_params(struct adapter *adap)
int chan;
u32 v;
v = t4_read_reg(adap, TP_TIMER_RESOLUTION);
adap->params.tp.tre = TIMERRESOLUTION_GET(v);
adap->params.tp.dack_re = DELAYEDACKRESOLUTION_GET(v);
v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
adap->params.tp.tre = TIMERRESOLUTION_G(v);
adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
for (chan = 0; chan < NCHAN; chan++)
......@@ -4172,27 +4184,27 @@ int t4_init_tp_params(struct adapter *adap)
/* Cache the adapter's Compressed Filter Mode and global Incress
* Configuration.
*/
t4_read_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
&adap->params.tp.vlan_pri_map, 1,
TP_VLAN_PRI_MAP);
t4_read_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
TP_VLAN_PRI_MAP_A);
t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
&adap->params.tp.ingress_config, 1,
TP_INGRESS_CONFIG);
TP_INGRESS_CONFIG_A);
/* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
* shift positions of several elements of the Compressed Filter Tuple
* for this adapter which we need frequently ...
*/
adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
F_PROTOCOL);
PROTOCOL_F);
/* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
* represents the presense of an Outer VLAN instead of a VNIC ID.
*/
if ((adap->params.tp.ingress_config & F_VNIC) == 0)
if ((adap->params.tp.ingress_config & VNIC_F) == 0)
adap->params.tp.vnic_shift = -1;
return 0;
......@@ -4218,35 +4230,35 @@ int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
switch (filter_mode & sel) {
case F_FCOE:
field_shift += W_FT_FCOE;
case FCOE_F:
field_shift += FT_FCOE_W;
break;
case F_PORT:
field_shift += W_FT_PORT;
case PORT_F:
field_shift += FT_PORT_W;
break;
case F_VNIC_ID:
field_shift += W_FT_VNIC_ID;
case VNIC_ID_F:
field_shift += FT_VNIC_ID_W;
break;
case F_VLAN:
field_shift += W_FT_VLAN;
case VLAN_F:
field_shift += FT_VLAN_W;
break;
case F_TOS:
field_shift += W_FT_TOS;
case TOS_F:
field_shift += FT_TOS_W;
break;
case F_PROTOCOL:
field_shift += W_FT_PROTOCOL;
case PROTOCOL_F:
field_shift += FT_PROTOCOL_W;
break;
case F_ETHERTYPE:
field_shift += W_FT_ETHERTYPE;
case ETHERTYPE_F:
field_shift += FT_ETHERTYPE_W;
break;
case F_MACMATCH:
field_shift += W_FT_MACMATCH;
case MACMATCH_F:
field_shift += FT_MACMATCH_W;
break;
case F_MPSHITTYPE:
field_shift += W_FT_MPSHITTYPE;
case MPSHITTYPE_F:
field_shift += FT_MPSHITTYPE_W;
break;
case F_FRAGMENTATION:
field_shift += W_FT_FRAGMENTATION;
case FRAGMENTATION_F:
field_shift += FT_FRAGMENTATION_W;
break;
}
}
......
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View file @ a515abd7
......@@ -63,460 +63,779 @@
#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
#define SGE_PF_KDOORBELL 0x0
#define QID_MASK 0xffff8000U
#define QID_SHIFT 15
#define QID(x) ((x) << QID_SHIFT)
#define DBPRIO(x) ((x) << 14)
#define DBTYPE(x) ((x) << 13)
#define PIDX_MASK 0x00003fffU
#define PIDX_SHIFT 0
#define PIDX(x) ((x) << PIDX_SHIFT)
#define PIDX_SHIFT_T5 0
#define PIDX_T5(x) ((x) << PIDX_SHIFT_T5)
#define SGE_TIMERREGS 6
#define SGE_PF_GTS 0x4
#define INGRESSQID_MASK 0xffff0000U
#define INGRESSQID_SHIFT 16
#define INGRESSQID(x) ((x) << INGRESSQID_SHIFT)
#define TIMERREG_MASK 0x0000e000U
#define TIMERREG_SHIFT 13
#define TIMERREG(x) ((x) << TIMERREG_SHIFT)
#define SEINTARM_MASK 0x00001000U
#define SEINTARM_SHIFT 12
#define SEINTARM(x) ((x) << SEINTARM_SHIFT)
#define CIDXINC_MASK 0x00000fffU
#define CIDXINC_SHIFT 0
#define CIDXINC(x) ((x) << CIDXINC_SHIFT)
#define X_RXPKTCPLMODE_SPLIT 1
#define X_INGPADBOUNDARY_SHIFT 5
#define SGE_CONTROL 0x1008
#define SGE_CONTROL2_A 0x1124
#define DCASYSTYPE 0x00080000U
#define RXPKTCPLMODE_MASK 0x00040000U
#define RXPKTCPLMODE_SHIFT 18
#define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT)
#define EGRSTATUSPAGESIZE_MASK 0x00020000U
#define EGRSTATUSPAGESIZE_SHIFT 17
#define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT)
#define PKTSHIFT_MASK 0x00001c00U
#define PKTSHIFT_SHIFT 10
#define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT)
#define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT)
#define INGPCIEBOUNDARY_32B_X 0
#define INGPCIEBOUNDARY_MASK 0x00000380U
#define INGPCIEBOUNDARY_SHIFT 7
#define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT)
#define INGPADBOUNDARY_MASK 0x00000070U
#define INGPADBOUNDARY_SHIFT 4
#define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT)
#define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \
>> INGPADBOUNDARY_SHIFT)
#define INGPACKBOUNDARY_16B_X 0
#define INGPACKBOUNDARY_SHIFT_X 5
#define SGE_PF_KDOORBELL_A 0x0
#define QID_S 15
#define QID_V(x) ((x) << QID_S)
#define DBPRIO_S 14
#define DBPRIO_V(x) ((x) << DBPRIO_S)
#define DBPRIO_F DBPRIO_V(1U)
#define PIDX_S 0
#define PIDX_V(x) ((x) << PIDX_S)
#define SGE_VF_KDOORBELL_A 0x0
#define DBTYPE_S 13
#define DBTYPE_V(x) ((x) << DBTYPE_S)
#define DBTYPE_F DBTYPE_V(1U)
#define PIDX_T5_S 0
#define PIDX_T5_M 0x1fffU
#define PIDX_T5_V(x) ((x) << PIDX_T5_S)
#define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M)
#define SGE_PF_GTS_A 0x4
#define INGRESSQID_S 16
#define INGRESSQID_V(x) ((x) << INGRESSQID_S)
#define TIMERREG_S 13
#define TIMERREG_V(x) ((x) << TIMERREG_S)
#define SEINTARM_S 12
#define SEINTARM_V(x) ((x) << SEINTARM_S)
#define CIDXINC_S 0
#define CIDXINC_M 0xfffU
#define CIDXINC_V(x) ((x) << CIDXINC_S)
#define SGE_CONTROL_A 0x1008
#define SGE_CONTROL2_A 0x1124
#define RXPKTCPLMODE_S 18
#define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S)
#define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U)
#define EGRSTATUSPAGESIZE_S 17
#define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S)
#define EGRSTATUSPAGESIZE_F EGRSTATUSPAGESIZE_V(1U)
#define PKTSHIFT_S 10
#define PKTSHIFT_M 0x7U
#define PKTSHIFT_V(x) ((x) << PKTSHIFT_S)
#define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M)
#define INGPCIEBOUNDARY_S 7
#define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S)
#define INGPADBOUNDARY_S 4
#define INGPADBOUNDARY_M 0x7U
#define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S)
#define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M)
#define EGRPCIEBOUNDARY_S 1
#define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S)
#define INGPACKBOUNDARY_S 16
#define INGPACKBOUNDARY_M 0x7U
#define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S)
#define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \
& INGPACKBOUNDARY_M)
#define EGRPCIEBOUNDARY_MASK 0x0000000eU
#define EGRPCIEBOUNDARY_SHIFT 1
#define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT)
#define GLOBALENABLE 0x00000001U
#define SGE_HOST_PAGE_SIZE 0x100c
#define GLOBALENABLE_S 0
#define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)
#define GLOBALENABLE_F GLOBALENABLE_V(1U)
#define SGE_HOST_PAGE_SIZE_A 0x100c
#define HOSTPAGESIZEPF7_S 28
#define HOSTPAGESIZEPF7_M 0xfU
#define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S)
#define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M)
#define HOSTPAGESIZEPF6_S 24
#define HOSTPAGESIZEPF6_M 0xfU
#define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S)
#define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M)
#define HOSTPAGESIZEPF5_S 20
#define HOSTPAGESIZEPF5_M 0xfU
#define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S)
#define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M)
#define HOSTPAGESIZEPF4_S 16
#define HOSTPAGESIZEPF4_M 0xfU
#define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S)
#define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M)
#define HOSTPAGESIZEPF3_S 12
#define HOSTPAGESIZEPF3_M 0xfU
#define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S)
#define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M)
#define HOSTPAGESIZEPF2_S 8
#define HOSTPAGESIZEPF2_M 0xfU
#define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S)
#define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M)
#define HOSTPAGESIZEPF1_S 4
#define HOSTPAGESIZEPF1_M 0xfU
#define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S)
#define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M)
#define HOSTPAGESIZEPF0_S 0
#define HOSTPAGESIZEPF0_M 0xfU
#define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S)
#define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M)
#define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010
#define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
#define QUEUESPERPAGEPF1_S 4
#define QUEUESPERPAGEPF0_S 0
#define QUEUESPERPAGEPF0_M 0xfU
#define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S)
#define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M)
#define HOSTPAGESIZEPF7_MASK 0x0000000fU
#define HOSTPAGESIZEPF7_SHIFT 28
#define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT)
#define SGE_INT_CAUSE1_A 0x1024
#define SGE_INT_CAUSE2_A 0x1030
#define SGE_INT_CAUSE3_A 0x103c
#define ERR_FLM_DBP_S 31
#define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S)
#define ERR_FLM_DBP_F ERR_FLM_DBP_V(1U)
#define ERR_FLM_IDMA1_S 30
#define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S)
#define ERR_FLM_IDMA1_F ERR_FLM_IDMA1_V(1U)
#define ERR_FLM_IDMA0_S 29
#define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S)
#define ERR_FLM_IDMA0_F ERR_FLM_IDMA0_V(1U)
#define ERR_FLM_HINT_S 28
#define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S)
#define ERR_FLM_HINT_F ERR_FLM_HINT_V(1U)
#define ERR_PCIE_ERROR3_S 27
#define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S)
#define ERR_PCIE_ERROR3_F ERR_PCIE_ERROR3_V(1U)
#define ERR_PCIE_ERROR2_S 26
#define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S)
#define ERR_PCIE_ERROR2_F ERR_PCIE_ERROR2_V(1U)
#define ERR_PCIE_ERROR1_S 25
#define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S)
#define ERR_PCIE_ERROR1_F ERR_PCIE_ERROR1_V(1U)
#define ERR_PCIE_ERROR0_S 24
#define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S)
#define ERR_PCIE_ERROR0_F ERR_PCIE_ERROR0_V(1U)
#define ERR_CPL_EXCEED_IQE_SIZE_S 22
#define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S)
#define ERR_CPL_EXCEED_IQE_SIZE_F ERR_CPL_EXCEED_IQE_SIZE_V(1U)
#define ERR_INVALID_CIDX_INC_S 21
#define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S)
#define ERR_INVALID_CIDX_INC_F ERR_INVALID_CIDX_INC_V(1U)
#define ERR_CPL_OPCODE_0_S 19
#define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S)
#define ERR_CPL_OPCODE_0_F ERR_CPL_OPCODE_0_V(1U)
#define ERR_DROPPED_DB_S 18
#define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S)
#define ERR_DROPPED_DB_F ERR_DROPPED_DB_V(1U)
#define ERR_DATA_CPL_ON_HIGH_QID1_S 17
#define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S)
#define ERR_DATA_CPL_ON_HIGH_QID1_F ERR_DATA_CPL_ON_HIGH_QID1_V(1U)
#define ERR_DATA_CPL_ON_HIGH_QID0_S 16
#define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S)
#define ERR_DATA_CPL_ON_HIGH_QID0_F ERR_DATA_CPL_ON_HIGH_QID0_V(1U)
#define ERR_BAD_DB_PIDX3_S 15
#define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S)
#define ERR_BAD_DB_PIDX3_F ERR_BAD_DB_PIDX3_V(1U)
#define ERR_BAD_DB_PIDX2_S 14
#define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S)
#define ERR_BAD_DB_PIDX2_F ERR_BAD_DB_PIDX2_V(1U)
#define ERR_BAD_DB_PIDX1_S 13
#define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S)
#define ERR_BAD_DB_PIDX1_F ERR_BAD_DB_PIDX1_V(1U)
#define ERR_BAD_DB_PIDX0_S 12
#define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S)
#define ERR_BAD_DB_PIDX0_F ERR_BAD_DB_PIDX0_V(1U)
#define ERR_ING_CTXT_PRIO_S 10
#define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S)
#define ERR_ING_CTXT_PRIO_F ERR_ING_CTXT_PRIO_V(1U)
#define ERR_EGR_CTXT_PRIO_S 9
#define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S)
#define ERR_EGR_CTXT_PRIO_F ERR_EGR_CTXT_PRIO_V(1U)
#define DBFIFO_HP_INT_S 8
#define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S)
#define DBFIFO_HP_INT_F DBFIFO_HP_INT_V(1U)
#define DBFIFO_LP_INT_S 7
#define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S)
#define DBFIFO_LP_INT_F DBFIFO_LP_INT_V(1U)
#define INGRESS_SIZE_ERR_S 5
#define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S)
#define INGRESS_SIZE_ERR_F INGRESS_SIZE_ERR_V(1U)
#define EGRESS_SIZE_ERR_S 4
#define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S)
#define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U)
#define SGE_INT_ENABLE3_A 0x1040
#define SGE_FL_BUFFER_SIZE0_A 0x1044
#define SGE_FL_BUFFER_SIZE1_A 0x1048
#define SGE_FL_BUFFER_SIZE2_A 0x104c
#define SGE_FL_BUFFER_SIZE3_A 0x1050
#define SGE_FL_BUFFER_SIZE4_A 0x1054
#define SGE_FL_BUFFER_SIZE5_A 0x1058
#define SGE_FL_BUFFER_SIZE6_A 0x105c
#define SGE_FL_BUFFER_SIZE7_A 0x1060
#define SGE_FL_BUFFER_SIZE8_A 0x1064
#define SGE_INGRESS_RX_THRESHOLD_A 0x10a0
#define THRESHOLD_0_S 24
#define THRESHOLD_0_M 0x3fU
#define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S)
#define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M)
#define THRESHOLD_1_S 16
#define THRESHOLD_1_M 0x3fU
#define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S)
#define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M)
#define THRESHOLD_2_S 8
#define THRESHOLD_2_M 0x3fU
#define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S)
#define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M)
#define THRESHOLD_3_S 0
#define THRESHOLD_3_M 0x3fU
#define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S)
#define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M)
#define SGE_CONM_CTRL_A 0x1094
#define EGRTHRESHOLD_S 8
#define EGRTHRESHOLD_M 0x3fU
#define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S)
#define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M)
#define EGRTHRESHOLDPACKING_S 14
#define EGRTHRESHOLDPACKING_M 0x3fU
#define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S)
#define EGRTHRESHOLDPACKING_G(x) \
(((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M)
#define SGE_TIMESTAMP_LO_A 0x1098
#define SGE_TIMESTAMP_HI_A 0x109c
#define TSOP_S 28
#define TSOP_M 0x3U
#define TSOP_V(x) ((x) << TSOP_S)
#define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M)
#define TSVAL_S 0
#define TSVAL_M 0xfffffffU
#define TSVAL_V(x) ((x) << TSVAL_S)
#define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M)
#define SGE_DBFIFO_STATUS_A 0x10a4
#define HP_INT_THRESH_S 28
#define HP_INT_THRESH_M 0xfU
#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
#define LP_INT_THRESH_S 12
#define LP_INT_THRESH_M 0xfU
#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
#define SGE_DOORBELL_CONTROL_A 0x10a8
#define NOCOALESCE_S 26
#define NOCOALESCE_V(x) ((x) << NOCOALESCE_S)
#define NOCOALESCE_F NOCOALESCE_V(1U)
#define ENABLE_DROP_S 13
#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
#define ENABLE_DROP_F ENABLE_DROP_V(1U)
#define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
#define TIMERVALUE0_S 16
#define TIMERVALUE0_M 0xffffU
#define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S)
#define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M)
#define TIMERVALUE1_S 0
#define TIMERVALUE1_M 0xffffU
#define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S)
#define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M)
#define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
#define TIMERVALUE2_S 16
#define TIMERVALUE2_M 0xffffU
#define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S)
#define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M)
#define TIMERVALUE3_S 0
#define TIMERVALUE3_M 0xffffU
#define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S)
#define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M)
#define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
#define TIMERVALUE4_S 16
#define TIMERVALUE4_M 0xffffU
#define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S)
#define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M)
#define HOSTPAGESIZEPF6_MASK 0x0000000fU
#define HOSTPAGESIZEPF6_SHIFT 24
#define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT)
#define TIMERVALUE5_S 0
#define TIMERVALUE5_M 0xffffU
#define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S)
#define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M)
#define HOSTPAGESIZEPF5_MASK 0x0000000fU
#define HOSTPAGESIZEPF5_SHIFT 20
#define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT)
#define SGE_DEBUG_INDEX_A 0x10cc
#define SGE_DEBUG_DATA_HIGH_A 0x10d0
#define SGE_DEBUG_DATA_LOW_A 0x10d4
#define HOSTPAGESIZEPF4_MASK 0x0000000fU
#define HOSTPAGESIZEPF4_SHIFT 16
#define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT)
#define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8
#define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc
#define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8
#define HOSTPAGESIZEPF3_MASK 0x0000000fU
#define HOSTPAGESIZEPF3_SHIFT 12
#define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT)
#define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
#define HOSTPAGESIZEPF2_MASK 0x0000000fU
#define HOSTPAGESIZEPF2_SHIFT 8
#define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT)
#define HP_INT_THRESH_S 28
#define HP_INT_THRESH_M 0xfU
#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
#define HOSTPAGESIZEPF1_M 0x0000000fU
#define HOSTPAGESIZEPF1_S 4
#define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_S)
#define HP_COUNT_S 16
#define HP_COUNT_M 0x7ffU
#define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)
#define HOSTPAGESIZEPF0_M 0x0000000fU
#define HOSTPAGESIZEPF0_S 0
#define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_S)
#define LP_INT_THRESH_S 12
#define LP_INT_THRESH_M 0xfU
#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
#define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
#define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
#define LP_COUNT_S 0
#define LP_COUNT_M 0x7ffU
#define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)
#define QUEUESPERPAGEPF1_S 4
#define LP_INT_THRESH_T5_S 18
#define LP_INT_THRESH_T5_M 0xfffU
#define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S)
#define QUEUESPERPAGEPF0_S 0
#define QUEUESPERPAGEPF0_MASK 0x0000000fU
#define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK)
#define LP_COUNT_T5_S 0
#define LP_COUNT_T5_M 0x3ffffU
#define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M)
#define QUEUESPERPAGEPF0 0
#define QUEUESPERPAGEPF1 4
#define SGE_DOORBELL_CONTROL_A 0x10a8
/* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
* The User Doorbells are each 128 bytes in length with a Simple Doorbell at
* offsets 8x and a Write Combining single 64-byte Egress Queue Unit
* (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues,
* we have a Going To Sleep register at offsets 8x+4.
*
* As noted above, we have many instances of the Simple Doorbell and Going To
* Sleep registers at offsets 8x and 8x+4, respectively. We want to use a
* non-64-byte aligned offset for the Simple Doorbell in order to attempt to
* avoid buffering of the writes to the Simple Doorbell and we want to use a
* non-contiguous offset for the Going To Sleep writes in order to avoid
* possible combining between them.
*/
#define SGE_UDB_SIZE 128
#define SGE_UDB_KDOORBELL 8
#define SGE_UDB_GTS 20
#define SGE_UDB_WCDOORBELL 64
#define SGE_INT_CAUSE1 0x1024
#define SGE_INT_CAUSE2 0x1030
#define SGE_INT_CAUSE3 0x103c
#define ERR_FLM_DBP 0x80000000U
#define ERR_FLM_IDMA1 0x40000000U
#define ERR_FLM_IDMA0 0x20000000U
#define ERR_FLM_HINT 0x10000000U
#define ERR_PCIE_ERROR3 0x08000000U
#define ERR_PCIE_ERROR2 0x04000000U
#define ERR_PCIE_ERROR1 0x02000000U
#define ERR_PCIE_ERROR0 0x01000000U
#define ERR_TIMER_ABOVE_MAX_QID 0x00800000U
#define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U
#define ERR_INVALID_CIDX_INC 0x00200000U
#define ERR_ITP_TIME_PAUSED 0x00100000U
#define ERR_CPL_OPCODE_0 0x00080000U
#define ERR_DROPPED_DB 0x00040000U
#define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U
#define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U
#define ERR_BAD_DB_PIDX3 0x00008000U
#define ERR_BAD_DB_PIDX2 0x00004000U
#define ERR_BAD_DB_PIDX1 0x00002000U
#define ERR_BAD_DB_PIDX0 0x00001000U
#define ERR_ING_PCIE_CHAN 0x00000800U
#define ERR_ING_CTXT_PRIO 0x00000400U
#define ERR_EGR_CTXT_PRIO 0x00000200U
#define DBFIFO_HP_INT 0x00000100U
#define DBFIFO_LP_INT 0x00000080U
#define REG_ADDRESS_ERR 0x00000040U
#define INGRESS_SIZE_ERR 0x00000020U
#define EGRESS_SIZE_ERR 0x00000010U
#define ERR_INV_CTXT3 0x00000008U
#define ERR_INV_CTXT2 0x00000004U
#define ERR_INV_CTXT1 0x00000002U
#define ERR_INV_CTXT0 0x00000001U
#define SGE_INT_ENABLE3 0x1040
#define SGE_FL_BUFFER_SIZE0 0x1044
#define SGE_FL_BUFFER_SIZE1 0x1048
#define SGE_FL_BUFFER_SIZE2 0x104c
#define SGE_FL_BUFFER_SIZE3 0x1050
#define SGE_FL_BUFFER_SIZE4 0x1054
#define SGE_FL_BUFFER_SIZE5 0x1058
#define SGE_FL_BUFFER_SIZE6 0x105c
#define SGE_FL_BUFFER_SIZE7 0x1060
#define SGE_FL_BUFFER_SIZE8 0x1064
#define SGE_INGRESS_RX_THRESHOLD 0x10a0
#define THRESHOLD_0_MASK 0x3f000000U
#define THRESHOLD_0_SHIFT 24
#define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT)
#define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT)
#define THRESHOLD_1_MASK 0x003f0000U
#define THRESHOLD_1_SHIFT 16
#define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT)
#define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT)
#define THRESHOLD_2_MASK 0x00003f00U
#define THRESHOLD_2_SHIFT 8
#define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT)
#define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT)
#define THRESHOLD_3_MASK 0x0000003fU
#define THRESHOLD_3_SHIFT 0
#define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT)
#define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)
#define SGE_CONM_CTRL 0x1094
#define EGRTHRESHOLD_MASK 0x00003f00U
#define EGRTHRESHOLDshift 8
#define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift)
#define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
#define EGRTHRESHOLDPACKING_MASK 0x3fU
#define EGRTHRESHOLDPACKING_SHIFT 14
#define EGRTHRESHOLDPACKING(x) ((x) << EGRTHRESHOLDPACKING_SHIFT)
#define EGRTHRESHOLDPACKING_GET(x) (((x) >> EGRTHRESHOLDPACKING_SHIFT) & \
EGRTHRESHOLDPACKING_MASK)
#define SGE_DBFIFO_STATUS 0x10a4
#define HP_INT_THRESH_SHIFT 28
#define HP_INT_THRESH_MASK 0xfU
#define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT)
#define LP_INT_THRESH_SHIFT 12
#define LP_INT_THRESH_MASK 0xfU
#define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT)
#define SGE_DOORBELL_CONTROL 0x10a8
#define ENABLE_DROP (1 << 13)
#define S_NOCOALESCE 26
#define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
#define F_NOCOALESCE V_NOCOALESCE(1U)
#define SGE_TIMESTAMP_LO 0x1098
#define SGE_TIMESTAMP_HI 0x109c
#define S_TSVAL 0
#define M_TSVAL 0xfffffffU
#define GET_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
#define SGE_TIMER_VALUE_0_AND_1 0x10b8
#define TIMERVALUE0_MASK 0xffff0000U
#define TIMERVALUE0_SHIFT 16
#define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT)
#define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)
#define TIMERVALUE1_MASK 0x0000ffffU
#define TIMERVALUE1_SHIFT 0
#define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT)
#define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
#define SGE_TIMER_VALUE_2_AND_3 0x10bc
#define TIMERVALUE2_MASK 0xffff0000U
#define TIMERVALUE2_SHIFT 16
#define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT)
#define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)
#define TIMERVALUE3_MASK 0x0000ffffU
#define TIMERVALUE3_SHIFT 0
#define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT)
#define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)
#define SGE_TIMER_VALUE_4_AND_5 0x10c0
#define TIMERVALUE4_MASK 0xffff0000U
#define TIMERVALUE4_SHIFT 16
#define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT)
#define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)
#define TIMERVALUE5_MASK 0x0000ffffU
#define TIMERVALUE5_SHIFT 0
#define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT)
#define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)
#define SGE_DEBUG_INDEX 0x10cc
#define SGE_DEBUG_DATA_HIGH 0x10d0
#define SGE_DEBUG_DATA_LOW 0x10d4
#define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
#define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
#define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
#define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
#define SGE_STAT_TOTAL_A 0x10e4
#define SGE_STAT_MATCH_A 0x10e8
#define SGE_STAT_CFG_A 0x10ec
#define STATSOURCE_T5_S 9
#define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S)
#define SGE_DBFIFO_STATUS2_A 0x1118
#define HP_INT_THRESH_T5_S 10
#define HP_INT_THRESH_T5_M 0xfU
#define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)
#define HP_COUNT_T5_S 0
#define HP_COUNT_T5_M 0x3ffU
#define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M)
#define ENABLE_DROP_S 13
#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
#define ENABLE_DROP_F ENABLE_DROP_V(1U)
#define DROPPED_DB_S 0
#define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)
#define DROPPED_DB_F DROPPED_DB_V(1U)
#define SGE_CTXT_CMD_A 0x11fc
#define SGE_DBQ_CTXT_BADDR_A 0x1084
/* registers for module PCIE */
#define PCIE_PF_CFG_A 0x40
#define AIVEC_S 4
#define AIVEC_M 0x3ffU
#define AIVEC_V(x) ((x) << AIVEC_S)
#define PCIE_PF_CLI_A 0x44
#define PCIE_INT_CAUSE_A 0x3004
#define UNXSPLCPLERR_S 29
#define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)
#define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U)
#define PCIEPINT_S 28
#define PCIEPINT_V(x) ((x) << PCIEPINT_S)
#define PCIEPINT_F PCIEPINT_V(1U)
#define PCIESINT_S 27
#define PCIESINT_V(x) ((x) << PCIESINT_S)
#define PCIESINT_F PCIESINT_V(1U)
#define RPLPERR_S 26
#define RPLPERR_V(x) ((x) << RPLPERR_S)
#define RPLPERR_F RPLPERR_V(1U)
#define RXWRPERR_S 25
#define RXWRPERR_V(x) ((x) << RXWRPERR_S)
#define RXWRPERR_F RXWRPERR_V(1U)
#define RXCPLPERR_S 24
#define RXCPLPERR_V(x) ((x) << RXCPLPERR_S)
#define RXCPLPERR_F RXCPLPERR_V(1U)
#define PIOTAGPERR_S 23
#define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S)
#define PIOTAGPERR_F PIOTAGPERR_V(1U)
#define MATAGPERR_S 22
#define MATAGPERR_V(x) ((x) << MATAGPERR_S)
#define MATAGPERR_F MATAGPERR_V(1U)
#define INTXCLRPERR_S 21
#define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S)
#define INTXCLRPERR_F INTXCLRPERR_V(1U)
#define FIDPERR_S 20
#define FIDPERR_V(x) ((x) << FIDPERR_S)
#define FIDPERR_F FIDPERR_V(1U)
#define CFGSNPPERR_S 19
#define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S)
#define CFGSNPPERR_F CFGSNPPERR_V(1U)
#define HRSPPERR_S 18
#define HRSPPERR_V(x) ((x) << HRSPPERR_S)
#define HRSPPERR_F HRSPPERR_V(1U)
#define HREQPERR_S 17
#define HREQPERR_V(x) ((x) << HREQPERR_S)
#define HREQPERR_F HREQPERR_V(1U)
#define HCNTPERR_S 16
#define HCNTPERR_V(x) ((x) << HCNTPERR_S)
#define HCNTPERR_F HCNTPERR_V(1U)
#define DRSPPERR_S 15
#define DRSPPERR_V(x) ((x) << DRSPPERR_S)
#define DRSPPERR_F DRSPPERR_V(1U)
#define DREQPERR_S 14
#define DREQPERR_V(x) ((x) << DREQPERR_S)
#define DREQPERR_F DREQPERR_V(1U)
#define DCNTPERR_S 13
#define DCNTPERR_V(x) ((x) << DCNTPERR_S)
#define DCNTPERR_F DCNTPERR_V(1U)
#define CRSPPERR_S 12
#define CRSPPERR_V(x) ((x) << CRSPPERR_S)
#define CRSPPERR_F CRSPPERR_V(1U)
#define CREQPERR_S 11
#define CREQPERR_V(x) ((x) << CREQPERR_S)
#define CREQPERR_F CREQPERR_V(1U)
#define CCNTPERR_S 10
#define CCNTPERR_V(x) ((x) << CCNTPERR_S)
#define CCNTPERR_F CCNTPERR_V(1U)
#define TARTAGPERR_S 9
#define TARTAGPERR_V(x) ((x) << TARTAGPERR_S)
#define TARTAGPERR_F TARTAGPERR_V(1U)
#define PIOREQPERR_S 8
#define PIOREQPERR_V(x) ((x) << PIOREQPERR_S)
#define PIOREQPERR_F PIOREQPERR_V(1U)
#define PIOCPLPERR_S 7
#define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S)
#define PIOCPLPERR_F PIOCPLPERR_V(1U)
#define MSIXDIPERR_S 6
#define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S)
#define MSIXDIPERR_F MSIXDIPERR_V(1U)
#define MSIXDATAPERR_S 5
#define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S)
#define MSIXDATAPERR_F MSIXDATAPERR_V(1U)
#define MSIXADDRHPERR_S 4
#define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S)
#define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U)
#define MSIXADDRLPERR_S 3
#define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S)
#define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U)
#define MSIDATAPERR_S 2
#define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S)
#define MSIDATAPERR_F MSIDATAPERR_V(1U)
#define MSIADDRHPERR_S 1
#define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S)
#define MSIADDRHPERR_F MSIADDRHPERR_V(1U)
#define MSIADDRLPERR_S 0
#define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)
#define MSIADDRLPERR_F MSIADDRLPERR_V(1U)
#define READRSPERR_S 29
#define READRSPERR_V(x) ((x) << READRSPERR_S)
#define READRSPERR_F READRSPERR_V(1U)
#define TRGT1GRPPERR_S 28
#define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S)
#define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U)
#define IPSOTPERR_S 27
#define IPSOTPERR_V(x) ((x) << IPSOTPERR_S)
#define IPSOTPERR_F IPSOTPERR_V(1U)
#define IPRETRYPERR_S 26
#define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S)
#define IPRETRYPERR_F IPRETRYPERR_V(1U)
#define IPRXDATAGRPPERR_S 25
#define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S)
#define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U)
#define IPRXHDRGRPPERR_S 24
#define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)
#define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U)
#define MAGRPPERR_S 22
#define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)
#define MAGRPPERR_F MAGRPPERR_V(1U)
#define VFIDPERR_S 21
#define VFIDPERR_V(x) ((x) << VFIDPERR_S)
#define VFIDPERR_F VFIDPERR_V(1U)
#define HREQWRPERR_S 16
#define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)
#define HREQWRPERR_F HREQWRPERR_V(1U)
#define DREQWRPERR_S 13
#define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)
#define DREQWRPERR_F DREQWRPERR_V(1U)
#define CREQRDPERR_S 11
#define CREQRDPERR_V(x) ((x) << CREQRDPERR_S)
#define CREQRDPERR_F CREQRDPERR_V(1U)
#define MSTTAGQPERR_S 10
#define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)
#define MSTTAGQPERR_F MSTTAGQPERR_V(1U)
#define PIOREQGRPPERR_S 8
#define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)
#define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U)
#define PIOCPLGRPPERR_S 7
#define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S)
#define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U)
#define MSIXSTIPERR_S 2
#define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S)
#define MSIXSTIPERR_F MSIXSTIPERR_V(1U)
#define MSTTIMEOUTPERR_S 1
#define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S)
#define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U)
#define MSTGRPPERR_S 0
#define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)
#define MSTGRPPERR_F MSTGRPPERR_V(1U)
#define PCIE_NONFAT_ERR_A 0x3010
#define PCIE_CFG_SPACE_REQ_A 0x3060
#define PCIE_CFG_SPACE_DATA_A 0x3064
#define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
#define S_HP_INT_THRESH 28
#define M_HP_INT_THRESH 0xfU
#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
#define S_LP_INT_THRESH_T5 18
#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
#define M_LP_COUNT_T5 0x3ffffU
#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5)
#define M_HP_COUNT 0x7ffU
#define S_HP_COUNT 16
#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
#define S_LP_INT_THRESH 12
#define M_LP_INT_THRESH 0xfU
#define M_LP_INT_THRESH_T5 0xfffU
#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
#define M_LP_COUNT 0x7ffU
#define S_LP_COUNT 0
#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
#define A_SGE_DBFIFO_STATUS 0x10a4
#define SGE_STAT_TOTAL 0x10e4
#define SGE_STAT_MATCH 0x10e8
#define SGE_STAT_CFG 0x10ec
#define S_STATSOURCE_T5 9
#define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
#define SGE_DBFIFO_STATUS2 0x1118
#define M_HP_COUNT_T5 0x3ffU
#define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5)
#define S_HP_INT_THRESH_T5 10
#define M_HP_INT_THRESH_T5 0xfU
#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
#define S_ENABLE_DROP 13
#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
#define F_ENABLE_DROP V_ENABLE_DROP(1U)
#define S_DROPPED_DB 0
#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
#define F_DROPPED_DB V_DROPPED_DB(1U)
#define A_SGE_DOORBELL_CONTROL 0x10a8
#define A_SGE_CTXT_CMD 0x11fc
#define A_SGE_DBQ_CTXT_BADDR 0x1084
#define PCIE_PF_CFG 0x40
#define AIVEC(x) ((x) << 4)
#define AIVEC_MASK 0x3ffU
#define PCIE_PF_CLI 0x44
#define PCIE_INT_CAUSE 0x3004
#define UNXSPLCPLERR 0x20000000U
#define PCIEPINT 0x10000000U
#define PCIESINT 0x08000000U
#define RPLPERR 0x04000000U
#define RXWRPERR 0x02000000U
#define RXCPLPERR 0x01000000U
#define PIOTAGPERR 0x00800000U
#define MATAGPERR 0x00400000U
#define INTXCLRPERR 0x00200000U
#define FIDPERR 0x00100000U
#define CFGSNPPERR 0x00080000U
#define HRSPPERR 0x00040000U
#define HREQPERR 0x00020000U
#define HCNTPERR 0x00010000U
#define DRSPPERR 0x00008000U
#define DREQPERR 0x00004000U
#define DCNTPERR 0x00002000U
#define CRSPPERR 0x00001000U
#define CREQPERR 0x00000800U
#define CCNTPERR 0x00000400U
#define TARTAGPERR 0x00000200U
#define PIOREQPERR 0x00000100U
#define PIOCPLPERR 0x00000080U
#define MSIXDIPERR 0x00000040U
#define MSIXDATAPERR 0x00000020U
#define MSIXADDRHPERR 0x00000010U
#define MSIXADDRLPERR 0x00000008U
#define MSIDATAPERR 0x00000004U
#define MSIADDRHPERR 0x00000002U
#define MSIADDRLPERR 0x00000001U
#define READRSPERR 0x20000000U
#define TRGT1GRPPERR 0x10000000U
#define IPSOTPERR 0x08000000U
#define IPRXDATAGRPPERR 0x02000000U
#define IPRXHDRGRPPERR 0x01000000U
#define MAGRPPERR 0x00400000U
#define VFIDPERR 0x00200000U
#define HREQWRPERR 0x00010000U
#define DREQWRPERR 0x00002000U
#define MSTTAGQPERR 0x00000400U
#define PIOREQGRPPERR 0x00000100U
#define PIOCPLGRPPERR 0x00000080U
#define MSIXSTIPERR 0x00000004U
#define MSTTIMEOUTPERR 0x00000002U
#define MSTGRPPERR 0x00000001U
#define PCIE_NONFAT_ERR 0x3010
#define PCIE_CFG_SPACE_REQ 0x3060
#define PCIE_CFG_SPACE_DATA 0x3064
#define PCIE_MEM_ACCESS_BASE_WIN 0x3068
#define S_PCIEOFST 10
#define M_PCIEOFST 0x3fffffU
#define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
#define PCIEOFST_MASK 0xfffffc00U
#define BIR_MASK 0x00000300U
#define BIR_SHIFT 8
#define BIR(x) ((x) << BIR_SHIFT)
#define WINDOW_MASK 0x000000ffU
#define WINDOW_SHIFT 0
#define WINDOW(x) ((x) << WINDOW_SHIFT)
#define GET_WINDOW(x) (((x) >> WINDOW_SHIFT) & WINDOW_MASK)
#define PCIE_MEM_ACCESS_OFFSET 0x306c
#define ENABLE (1U << 30)
#define FUNCTION(x) ((x) << 12)
#define F_LOCALCFG (1U << 28)
#define S_PFNUM 0
#define V_PFNUM(x) ((x) << S_PFNUM)
#define PCIE_FW 0x30b8
#define PCIE_FW_ERR 0x80000000U
#define PCIE_FW_INIT 0x40000000U
#define PCIE_FW_HALT 0x20000000U
#define PCIE_FW_MASTER_VLD 0x00008000U
#define PCIE_FW_MASTER(x) ((x) << 12)
#define PCIE_FW_MASTER_MASK 0x7
#define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK)
#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
#define RNPP 0x80000000U
#define RPCP 0x20000000U
#define RCIP 0x08000000U
#define RCCP 0x04000000U
#define RFTP 0x00800000U
#define PTRP 0x00100000U
#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
#define TPCP 0x40000000U
#define TNPP 0x20000000U
#define TFTP 0x10000000U
#define TCAP 0x08000000U
#define TCIP 0x04000000U
#define RCAP 0x02000000U
#define PLUP 0x00800000U
#define PLDN 0x00400000U
#define OTDD 0x00200000U
#define GTRP 0x00100000U
#define RDPE 0x00040000U
#define TDCE 0x00020000U
#define TDUE 0x00010000U
#define MC_INT_CAUSE 0x7518
#define MC_P_INT_CAUSE 0x41318
#define ECC_UE_INT_CAUSE 0x00000004U
#define ECC_CE_INT_CAUSE 0x00000002U
#define PERR_INT_CAUSE 0x00000001U
#define MC_ECC_STATUS 0x751c
#define MC_P_ECC_STATUS 0x4131c
#define ECC_CECNT_MASK 0xffff0000U
#define ECC_CECNT_SHIFT 16
#define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT)
#define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT)
#define ECC_UECNT_MASK 0x0000ffffU
#define ECC_UECNT_SHIFT 0
#define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT)
#define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT)
#define MC_BIST_CMD 0x7600
#define START_BIST 0x80000000U
#define BIST_CMD_GAP_MASK 0x0000ff00U
#define BIST_CMD_GAP_SHIFT 8
#define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT)
#define BIST_OPCODE_MASK 0x00000003U
#define BIST_OPCODE_SHIFT 0
#define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT)
#define MC_BIST_CMD_ADDR 0x7604
#define MC_BIST_CMD_LEN 0x7608
#define MC_BIST_DATA_PATTERN 0x760c
#define BIST_DATA_TYPE_MASK 0x0000000fU
#define BIST_DATA_TYPE_SHIFT 0
#define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT)
#define MC_BIST_STATUS_RDATA 0x7688
#define PCIEOFST_S 10
#define PCIEOFST_M 0x3fffffU
#define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)
#define BIR_S 8
#define BIR_M 0x3U
#define BIR_V(x) ((x) << BIR_S)
#define BIR_G(x) (((x) >> BIR_S) & BIR_M)
#define WINDOW_S 0
#define WINDOW_M 0xffU
#define WINDOW_V(x) ((x) << WINDOW_S)
#define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M)
#define PCIE_MEM_ACCESS_OFFSET_A 0x306c
#define ENABLE_S 30
#define ENABLE_V(x) ((x) << ENABLE_S)
#define ENABLE_F ENABLE_V(1U)
#define LOCALCFG_S 28
#define LOCALCFG_V(x) ((x) << LOCALCFG_S)
#define LOCALCFG_F LOCALCFG_V(1U)
#define FUNCTION_S 12
#define FUNCTION_V(x) ((x) << FUNCTION_S)
#define REGISTER_S 0
#define REGISTER_V(x) ((x) << REGISTER_S)
#define PFNUM_S 0
#define PFNUM_V(x) ((x) << PFNUM_S)
#define PCIE_FW_A 0x30b8
#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
#define RNPP_S 31
#define RNPP_V(x) ((x) << RNPP_S)
#define RNPP_F RNPP_V(1U)
#define RPCP_S 29
#define RPCP_V(x) ((x) << RPCP_S)
#define RPCP_F RPCP_V(1U)
#define RCIP_S 27
#define RCIP_V(x) ((x) << RCIP_S)
#define RCIP_F RCIP_V(1U)
#define RCCP_S 26
#define RCCP_V(x) ((x) << RCCP_S)
#define RCCP_F RCCP_V(1U)
#define RFTP_S 23
#define RFTP_V(x) ((x) << RFTP_S)
#define RFTP_F RFTP_V(1U)
#define PTRP_S 20
#define PTRP_V(x) ((x) << PTRP_S)
#define PTRP_F PTRP_V(1U)
#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
#define TPCP_S 30
#define TPCP_V(x) ((x) << TPCP_S)
#define TPCP_F TPCP_V(1U)
#define TNPP_S 29
#define TNPP_V(x) ((x) << TNPP_S)
#define TNPP_F TNPP_V(1U)
#define TFTP_S 28
#define TFTP_V(x) ((x) << TFTP_S)
#define TFTP_F TFTP_V(1U)
#define TCAP_S 27
#define TCAP_V(x) ((x) << TCAP_S)
#define TCAP_F TCAP_V(1U)
#define TCIP_S 26
#define TCIP_V(x) ((x) << TCIP_S)
#define TCIP_F TCIP_V(1U)
#define RCAP_S 25
#define RCAP_V(x) ((x) << RCAP_S)
#define RCAP_F RCAP_V(1U)
#define PLUP_S 23
#define PLUP_V(x) ((x) << PLUP_S)
#define PLUP_F PLUP_V(1U)
#define PLDN_S 22
#define PLDN_V(x) ((x) << PLDN_S)
#define PLDN_F PLDN_V(1U)
#define OTDD_S 21
#define OTDD_V(x) ((x) << OTDD_S)
#define OTDD_F OTDD_V(1U)
#define GTRP_S 20
#define GTRP_V(x) ((x) << GTRP_S)
#define GTRP_F GTRP_V(1U)
#define RDPE_S 18
#define RDPE_V(x) ((x) << RDPE_S)
#define RDPE_F RDPE_V(1U)
#define TDCE_S 17
#define TDCE_V(x) ((x) << TDCE_S)
#define TDCE_F TDCE_V(1U)
#define TDUE_S 16
#define TDUE_V(x) ((x) << TDUE_S)
#define TDUE_F TDUE_V(1U)
/* registers for module MC */
#define MC_INT_CAUSE_A 0x7518
#define MC_P_INT_CAUSE_A 0x41318
#define ECC_UE_INT_CAUSE_S 2
#define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S)
#define ECC_UE_INT_CAUSE_F ECC_UE_INT_CAUSE_V(1U)
#define ECC_CE_INT_CAUSE_S 1
#define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S)
#define ECC_CE_INT_CAUSE_F ECC_CE_INT_CAUSE_V(1U)
#define PERR_INT_CAUSE_S 0
#define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S)
#define PERR_INT_CAUSE_F PERR_INT_CAUSE_V(1U)
#define MC_ECC_STATUS_A 0x751c
#define MC_P_ECC_STATUS_A 0x4131c
#define ECC_CECNT_S 16
#define ECC_CECNT_M 0xffffU
#define ECC_CECNT_V(x) ((x) << ECC_CECNT_S)
#define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M)
#define ECC_UECNT_S 0
#define ECC_UECNT_M 0xffffU
#define ECC_UECNT_V(x) ((x) << ECC_UECNT_S)
#define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M)
#define MC_BIST_CMD_A 0x7600
#define START_BIST_S 31
#define START_BIST_V(x) ((x) << START_BIST_S)
#define START_BIST_F START_BIST_V(1U)
#define BIST_CMD_GAP_S 8
#define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S)
#define BIST_OPCODE_S 0
#define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S)
#define MC_BIST_CMD_ADDR_A 0x7604
#define MC_BIST_CMD_LEN_A 0x7608
#define MC_BIST_DATA_PATTERN_A 0x760c
#define MC_BIST_STATUS_RDATA_A 0x7688
/* registers for module MA */
#define MA_EDRAM0_BAR_A 0x77c0
#define EDRAM0_SIZE_S 0
......@@ -574,263 +893,547 @@
#define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
#define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)
#define MA_INT_CAUSE 0x77e0
#define MEM_PERR_INT_CAUSE 0x00000002U
#define MEM_WRAP_INT_CAUSE 0x00000001U
#define MA_INT_WRAP_STATUS 0x77e4
#define MEM_WRAP_ADDRESS_MASK 0xfffffff0U
#define MEM_WRAP_ADDRESS_SHIFT 4
#define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT)
#define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU
#define MEM_WRAP_CLIENT_NUM_SHIFT 0
#define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
#define MA_PCIE_FW 0x30b8
#define MA_PARITY_ERROR_STATUS 0x77f4
#define MA_PARITY_ERROR_STATUS2 0x7804
#define EDC_0_BASE_ADDR 0x7900
#define EDC_BIST_CMD 0x7904
#define EDC_BIST_CMD_ADDR 0x7908
#define EDC_BIST_CMD_LEN 0x790c
#define EDC_BIST_DATA_PATTERN 0x7910
#define EDC_BIST_STATUS_RDATA 0x7928
#define EDC_INT_CAUSE 0x7978
#define ECC_UE_PAR 0x00000020U
#define ECC_CE_PAR 0x00000010U
#define PERR_PAR_CAUSE 0x00000008U
#define EDC_ECC_STATUS 0x797c
#define EDC_1_BASE_ADDR 0x7980
#define CIM_BOOT_CFG 0x7b00
#define BOOTADDR_MASK 0xffffff00U
#define UPCRST 0x1U
#define CIM_PF_MAILBOX_DATA 0x240
#define CIM_PF_MAILBOX_CTRL 0x280
#define MBMSGVALID 0x00000008U
#define MBINTREQ 0x00000004U
#define MBOWNER_MASK 0x00000003U
#define MBOWNER_SHIFT 0
#define MBOWNER(x) ((x) << MBOWNER_SHIFT)
#define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)
#define CIM_PF_HOST_INT_ENABLE 0x288
#define MBMSGRDYINTEN(x) ((x) << 19)
#define CIM_PF_HOST_INT_CAUSE 0x28c
#define MBMSGRDYINT 0x00080000U
#define CIM_HOST_INT_CAUSE 0x7b2c
#define TIEQOUTPARERRINT 0x00100000U
#define TIEQINPARERRINT 0x00080000U
#define MBHOSTPARERR 0x00040000U
#define MBUPPARERR 0x00020000U
#define IBQPARERR 0x0001f800U
#define IBQTP0PARERR 0x00010000U
#define IBQTP1PARERR 0x00008000U
#define IBQULPPARERR 0x00004000U
#define IBQSGELOPARERR 0x00002000U
#define IBQSGEHIPARERR 0x00001000U
#define IBQNCSIPARERR 0x00000800U
#define OBQPARERR 0x000007e0U
#define OBQULP0PARERR 0x00000400U
#define OBQULP1PARERR 0x00000200U
#define OBQULP2PARERR 0x00000100U
#define OBQULP3PARERR 0x00000080U
#define OBQSGEPARERR 0x00000040U
#define OBQNCSIPARERR 0x00000020U
#define PREFDROPINT 0x00000002U
#define UPACCNONZERO 0x00000001U
#define CIM_HOST_UPACC_INT_CAUSE 0x7b34
#define EEPROMWRINT 0x40000000U
#define TIMEOUTMAINT 0x20000000U
#define TIMEOUTINT 0x10000000U
#define RSPOVRLOOKUPINT 0x08000000U
#define REQOVRLOOKUPINT 0x04000000U
#define BLKWRPLINT 0x02000000U
#define BLKRDPLINT 0x01000000U
#define SGLWRPLINT 0x00800000U
#define SGLRDPLINT 0x00400000U
#define BLKWRCTLINT 0x00200000U
#define BLKRDCTLINT 0x00100000U
#define SGLWRCTLINT 0x00080000U
#define SGLRDCTLINT 0x00040000U
#define BLKWREEPROMINT 0x00020000U
#define BLKRDEEPROMINT 0x00010000U
#define SGLWREEPROMINT 0x00008000U
#define SGLRDEEPROMINT 0x00004000U
#define BLKWRFLASHINT 0x00002000U
#define BLKRDFLASHINT 0x00001000U
#define SGLWRFLASHINT 0x00000800U
#define SGLRDFLASHINT 0x00000400U
#define BLKWRBOOTINT 0x00000200U
#define BLKRDBOOTINT 0x00000100U
#define SGLWRBOOTINT 0x00000080U
#define SGLRDBOOTINT 0x00000040U
#define ILLWRBEINT 0x00000020U
#define ILLRDBEINT 0x00000010U
#define ILLRDINT 0x00000008U
#define ILLWRINT 0x00000004U
#define ILLTRANSINT 0x00000002U
#define RSVDSPACEINT 0x00000001U
#define TP_OUT_CONFIG 0x7d04
#define VLANEXTENABLE_MASK 0x0000f000U
#define VLANEXTENABLE_SHIFT 12
#define TP_GLOBAL_CONFIG 0x7d08
#define FIVETUPLELOOKUP_SHIFT 17
#define FIVETUPLELOOKUP_MASK 0x00060000U
#define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT)
#define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \
FIVETUPLELOOKUP_SHIFT)
#define TP_PARA_REG2 0x7d68
#define MAXRXDATA_MASK 0xffff0000U
#define MAXRXDATA_SHIFT 16
#define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT)
#define TP_TIMER_RESOLUTION 0x7d90
#define TIMERRESOLUTION_MASK 0x00ff0000U
#define TIMERRESOLUTION_SHIFT 16
#define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)
#define DELAYEDACKRESOLUTION_MASK 0x000000ffU
#define DELAYEDACKRESOLUTION_SHIFT 0
#define DELAYEDACKRESOLUTION_GET(x) \
(((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT)
#define TP_SHIFT_CNT 0x7dc0
#define SYNSHIFTMAX_SHIFT 24
#define SYNSHIFTMAX_MASK 0xff000000U
#define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT)
#define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \
SYNSHIFTMAX_SHIFT)
#define RXTSHIFTMAXR1_SHIFT 20
#define RXTSHIFTMAXR1_MASK 0x00f00000U
#define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT)
#define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \
RXTSHIFTMAXR1_SHIFT)
#define RXTSHIFTMAXR2_SHIFT 16
#define RXTSHIFTMAXR2_MASK 0x000f0000U
#define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT)
#define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \
RXTSHIFTMAXR2_SHIFT)
#define PERSHIFTBACKOFFMAX_SHIFT 12
#define PERSHIFTBACKOFFMAX_MASK 0x0000f000U
#define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT)
#define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \
PERSHIFTBACKOFFMAX_SHIFT)
#define PERSHIFTMAX_SHIFT 8
#define PERSHIFTMAX_MASK 0x00000f00U
#define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT)
#define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \
PERSHIFTMAX_SHIFT)
#define KEEPALIVEMAXR1_SHIFT 4
#define KEEPALIVEMAXR1_MASK 0x000000f0U
#define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT)
#define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \
KEEPALIVEMAXR1_SHIFT)
#define KEEPALIVEMAXR2_SHIFT 0
#define KEEPALIVEMAXR2_MASK 0x0000000fU
#define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT)
#define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \
KEEPALIVEMAXR2_SHIFT)
#define TP_CCTRL_TABLE 0x7ddc
#define TP_MTU_TABLE 0x7de4
#define MTUINDEX_MASK 0xff000000U
#define MTUINDEX_SHIFT 24
#define MTUINDEX(x) ((x) << MTUINDEX_SHIFT)
#define MTUWIDTH_MASK 0x000f0000U
#define MTUWIDTH_SHIFT 16
#define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT)
#define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT)
#define MTUVALUE_MASK 0x00003fffU
#define MTUVALUE_SHIFT 0
#define MTUVALUE(x) ((x) << MTUVALUE_SHIFT)
#define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT)
#define TP_RSS_LKP_TABLE 0x7dec
#define LKPTBLROWVLD 0x80000000U
#define LKPTBLQUEUE1_MASK 0x000ffc00U
#define LKPTBLQUEUE1_SHIFT 10
#define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT)
#define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT)
#define LKPTBLQUEUE0_MASK 0x000003ffU
#define LKPTBLQUEUE0_SHIFT 0
#define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT)
#define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT)
#define TP_PIO_ADDR 0x7e40
#define TP_PIO_DATA 0x7e44
#define TP_MIB_INDEX 0x7e50
#define TP_MIB_DATA 0x7e54
#define TP_INT_CAUSE 0x7e74
#define FLMTXFLSTEMPTY 0x40000000U
#define TP_VLAN_PRI_MAP 0x140
#define FRAGMENTATION_SHIFT 9
#define FRAGMENTATION_MASK 0x00000200U
#define MPSHITTYPE_MASK 0x00000100U
#define MACMATCH_MASK 0x00000080U
#define ETHERTYPE_MASK 0x00000040U
#define PROTOCOL_MASK 0x00000020U
#define TOS_MASK 0x00000010U
#define VLAN_MASK 0x00000008U
#define VNIC_ID_MASK 0x00000004U
#define PORT_MASK 0x00000002U
#define FCOE_SHIFT 0
#define FCOE_MASK 0x00000001U
#define TP_INGRESS_CONFIG 0x141
#define VNIC 0x00000800U
#define CSUM_HAS_PSEUDO_HDR 0x00000400U
#define RM_OVLAN 0x00000200U
#define LOOKUPEVERYPKT 0x00000100U
#define TP_MIB_MAC_IN_ERR_0 0x0
#define TP_MIB_TCP_OUT_RST 0xc
#define TP_MIB_TCP_IN_SEG_HI 0x10
#define TP_MIB_TCP_IN_SEG_LO 0x11
#define TP_MIB_TCP_OUT_SEG_HI 0x12
#define TP_MIB_TCP_OUT_SEG_LO 0x13
#define TP_MIB_TCP_RXT_SEG_HI 0x14
#define TP_MIB_TCP_RXT_SEG_LO 0x15
#define TP_MIB_TNL_CNG_DROP_0 0x18
#define TP_MIB_TCP_V6IN_ERR_0 0x28
#define TP_MIB_TCP_V6OUT_RST 0x2c
#define TP_MIB_OFD_ARP_DROP 0x36
#define TP_MIB_TNL_DROP_0 0x44
#define TP_MIB_OFD_VLN_DROP_0 0x58
#define ULP_TX_INT_CAUSE 0x8dcc
#define PBL_BOUND_ERR_CH3 0x80000000U
#define PBL_BOUND_ERR_CH2 0x40000000U
#define PBL_BOUND_ERR_CH1 0x20000000U
#define PBL_BOUND_ERR_CH0 0x10000000U
#define PM_RX_INT_CAUSE 0x8fdc
#define ZERO_E_CMD_ERROR 0x00400000U
#define PMRX_FRAMING_ERROR 0x003ffff0U
#define OCSPI_PAR_ERROR 0x00000008U
#define DB_OPTIONS_PAR_ERROR 0x00000004U
#define IESPI_PAR_ERROR 0x00000002U
#define E_PCMD_PAR_ERROR 0x00000001U
#define PM_TX_INT_CAUSE 0x8ffc
#define PCMD_LEN_OVFL0 0x80000000U
#define PCMD_LEN_OVFL1 0x40000000U
#define PCMD_LEN_OVFL2 0x20000000U
#define ZERO_C_CMD_ERROR 0x10000000U
#define PMTX_FRAMING_ERROR 0x0ffffff0U
#define OESPI_PAR_ERROR 0x00000008U
#define ICSPI_PAR_ERROR 0x00000002U
#define C_PCMD_PAR_ERROR 0x00000001U
#define MA_INT_CAUSE_A 0x77e0
#define MEM_PERR_INT_CAUSE_S 1
#define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S)
#define MEM_PERR_INT_CAUSE_F MEM_PERR_INT_CAUSE_V(1U)
#define MEM_WRAP_INT_CAUSE_S 0
#define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S)
#define MEM_WRAP_INT_CAUSE_F MEM_WRAP_INT_CAUSE_V(1U)
#define MA_INT_WRAP_STATUS_A 0x77e4
#define MEM_WRAP_ADDRESS_S 4
#define MEM_WRAP_ADDRESS_M 0xfffffffU
#define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M)
#define MEM_WRAP_CLIENT_NUM_S 0
#define MEM_WRAP_CLIENT_NUM_M 0xfU
#define MEM_WRAP_CLIENT_NUM_G(x) \
(((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M)
#define MA_PARITY_ERROR_STATUS_A 0x77f4
#define MA_PARITY_ERROR_STATUS1_A 0x77f4
#define MA_PARITY_ERROR_STATUS2_A 0x7804
/* registers for module EDC_0 */
#define EDC_0_BASE_ADDR 0x7900
#define EDC_BIST_CMD_A 0x7904
#define EDC_BIST_CMD_ADDR_A 0x7908
#define EDC_BIST_CMD_LEN_A 0x790c
#define EDC_BIST_DATA_PATTERN_A 0x7910
#define EDC_BIST_STATUS_RDATA_A 0x7928
#define EDC_INT_CAUSE_A 0x7978
#define ECC_UE_PAR_S 5
#define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S)
#define ECC_UE_PAR_F ECC_UE_PAR_V(1U)
#define ECC_CE_PAR_S 4
#define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S)
#define ECC_CE_PAR_F ECC_CE_PAR_V(1U)
#define PERR_PAR_CAUSE_S 3
#define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S)
#define PERR_PAR_CAUSE_F PERR_PAR_CAUSE_V(1U)
#define EDC_ECC_STATUS_A 0x797c
/* registers for module EDC_1 */
#define EDC_1_BASE_ADDR 0x7980
/* registers for module CIM */
#define CIM_BOOT_CFG_A 0x7b00
#define BOOTADDR_M 0xffffff00U
#define UPCRST_S 0
#define UPCRST_V(x) ((x) << UPCRST_S)
#define UPCRST_F UPCRST_V(1U)
#define CIM_PF_MAILBOX_DATA_A 0x240
#define CIM_PF_MAILBOX_CTRL_A 0x280
#define MBMSGVALID_S 3
#define MBMSGVALID_V(x) ((x) << MBMSGVALID_S)
#define MBMSGVALID_F MBMSGVALID_V(1U)
#define MBINTREQ_S 2
#define MBINTREQ_V(x) ((x) << MBINTREQ_S)
#define MBINTREQ_F MBINTREQ_V(1U)
#define MBOWNER_S 0
#define MBOWNER_M 0x3U
#define MBOWNER_V(x) ((x) << MBOWNER_S)
#define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M)
#define CIM_PF_HOST_INT_ENABLE_A 0x288
#define MBMSGRDYINTEN_S 19
#define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S)
#define MBMSGRDYINTEN_F MBMSGRDYINTEN_V(1U)
#define CIM_PF_HOST_INT_CAUSE_A 0x28c
#define MBMSGRDYINT_S 19
#define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S)
#define MBMSGRDYINT_F MBMSGRDYINT_V(1U)
#define CIM_HOST_INT_CAUSE_A 0x7b2c
#define TIEQOUTPARERRINT_S 20
#define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S)
#define TIEQOUTPARERRINT_F TIEQOUTPARERRINT_V(1U)
#define TIEQINPARERRINT_S 19
#define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)
#define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U)
#define PREFDROPINT_S 1
#define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
#define PREFDROPINT_F PREFDROPINT_V(1U)
#define UPACCNONZERO_S 0
#define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S)
#define UPACCNONZERO_F UPACCNONZERO_V(1U)
#define MBHOSTPARERR_S 18
#define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S)
#define MBHOSTPARERR_F MBHOSTPARERR_V(1U)
#define MBUPPARERR_S 17
#define MBUPPARERR_V(x) ((x) << MBUPPARERR_S)
#define MBUPPARERR_F MBUPPARERR_V(1U)
#define IBQTP0PARERR_S 16
#define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S)
#define IBQTP0PARERR_F IBQTP0PARERR_V(1U)
#define IBQTP1PARERR_S 15
#define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S)
#define IBQTP1PARERR_F IBQTP1PARERR_V(1U)
#define IBQULPPARERR_S 14
#define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S)
#define IBQULPPARERR_F IBQULPPARERR_V(1U)
#define IBQSGELOPARERR_S 13
#define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S)
#define IBQSGELOPARERR_F IBQSGELOPARERR_V(1U)
#define IBQSGEHIPARERR_S 12
#define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S)
#define IBQSGEHIPARERR_F IBQSGEHIPARERR_V(1U)
#define IBQNCSIPARERR_S 11
#define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S)
#define IBQNCSIPARERR_F IBQNCSIPARERR_V(1U)
#define OBQULP0PARERR_S 10
#define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S)
#define OBQULP0PARERR_F OBQULP0PARERR_V(1U)
#define OBQULP1PARERR_S 9
#define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S)
#define OBQULP1PARERR_F OBQULP1PARERR_V(1U)
#define OBQULP2PARERR_S 8
#define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S)
#define OBQULP2PARERR_F OBQULP2PARERR_V(1U)
#define OBQULP3PARERR_S 7
#define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S)
#define OBQULP3PARERR_F OBQULP3PARERR_V(1U)
#define OBQSGEPARERR_S 6
#define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S)
#define OBQSGEPARERR_F OBQSGEPARERR_V(1U)
#define OBQNCSIPARERR_S 5
#define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S)
#define OBQNCSIPARERR_F OBQNCSIPARERR_V(1U)
#define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34
#define EEPROMWRINT_S 30
#define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S)
#define EEPROMWRINT_F EEPROMWRINT_V(1U)
#define TIMEOUTMAINT_S 29
#define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S)
#define TIMEOUTMAINT_F TIMEOUTMAINT_V(1U)
#define TIMEOUTINT_S 28
#define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S)
#define TIMEOUTINT_F TIMEOUTINT_V(1U)
#define RSPOVRLOOKUPINT_S 27
#define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S)
#define RSPOVRLOOKUPINT_F RSPOVRLOOKUPINT_V(1U)
#define REQOVRLOOKUPINT_S 26
#define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S)
#define REQOVRLOOKUPINT_F REQOVRLOOKUPINT_V(1U)
#define BLKWRPLINT_S 25
#define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S)
#define BLKWRPLINT_F BLKWRPLINT_V(1U)
#define BLKRDPLINT_S 24
#define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S)
#define BLKRDPLINT_F BLKRDPLINT_V(1U)
#define SGLWRPLINT_S 23
#define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S)
#define SGLWRPLINT_F SGLWRPLINT_V(1U)
#define SGLRDPLINT_S 22
#define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S)
#define SGLRDPLINT_F SGLRDPLINT_V(1U)
#define BLKWRCTLINT_S 21
#define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S)
#define BLKWRCTLINT_F BLKWRCTLINT_V(1U)
#define BLKRDCTLINT_S 20
#define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S)
#define BLKRDCTLINT_F BLKRDCTLINT_V(1U)
#define SGLWRCTLINT_S 19
#define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S)
#define SGLWRCTLINT_F SGLWRCTLINT_V(1U)
#define SGLRDCTLINT_S 18
#define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S)
#define SGLRDCTLINT_F SGLRDCTLINT_V(1U)
#define BLKWREEPROMINT_S 17
#define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S)
#define BLKWREEPROMINT_F BLKWREEPROMINT_V(1U)
#define BLKRDEEPROMINT_S 16
#define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S)
#define BLKRDEEPROMINT_F BLKRDEEPROMINT_V(1U)
#define SGLWREEPROMINT_S 15
#define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S)
#define SGLWREEPROMINT_F SGLWREEPROMINT_V(1U)
#define SGLRDEEPROMINT_S 14
#define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S)
#define SGLRDEEPROMINT_F SGLRDEEPROMINT_V(1U)
#define BLKWRFLASHINT_S 13
#define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S)
#define BLKWRFLASHINT_F BLKWRFLASHINT_V(1U)
#define BLKRDFLASHINT_S 12
#define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S)
#define BLKRDFLASHINT_F BLKRDFLASHINT_V(1U)
#define SGLWRFLASHINT_S 11
#define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S)
#define SGLWRFLASHINT_F SGLWRFLASHINT_V(1U)
#define SGLRDFLASHINT_S 10
#define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S)
#define SGLRDFLASHINT_F SGLRDFLASHINT_V(1U)
#define BLKWRBOOTINT_S 9
#define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S)
#define BLKWRBOOTINT_F BLKWRBOOTINT_V(1U)
#define BLKRDBOOTINT_S 8
#define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S)
#define BLKRDBOOTINT_F BLKRDBOOTINT_V(1U)
#define SGLWRBOOTINT_S 7
#define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S)
#define SGLWRBOOTINT_F SGLWRBOOTINT_V(1U)
#define SGLRDBOOTINT_S 6
#define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S)
#define SGLRDBOOTINT_F SGLRDBOOTINT_V(1U)
#define ILLWRBEINT_S 5
#define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S)
#define ILLWRBEINT_F ILLWRBEINT_V(1U)
#define ILLRDBEINT_S 4
#define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S)
#define ILLRDBEINT_F ILLRDBEINT_V(1U)
#define ILLRDINT_S 3
#define ILLRDINT_V(x) ((x) << ILLRDINT_S)
#define ILLRDINT_F ILLRDINT_V(1U)
#define ILLWRINT_S 2
#define ILLWRINT_V(x) ((x) << ILLWRINT_S)
#define ILLWRINT_F ILLWRINT_V(1U)
#define ILLTRANSINT_S 1
#define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S)
#define ILLTRANSINT_F ILLTRANSINT_V(1U)
#define RSVDSPACEINT_S 0
#define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S)
#define RSVDSPACEINT_F RSVDSPACEINT_V(1U)
/* registers for module TP */
#define TP_OUT_CONFIG_A 0x7d04
#define TP_GLOBAL_CONFIG_A 0x7d08
#define FIVETUPLELOOKUP_S 17
#define FIVETUPLELOOKUP_M 0x3U
#define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S)
#define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M)
#define TP_PARA_REG2_A 0x7d68
#define MAXRXDATA_S 16
#define MAXRXDATA_M 0xffffU
#define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M)
#define TP_TIMER_RESOLUTION_A 0x7d90
#define TIMERRESOLUTION_S 16
#define TIMERRESOLUTION_M 0xffU
#define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M)
#define DELAYEDACKRESOLUTION_S 0
#define DELAYEDACKRESOLUTION_M 0xffU
#define DELAYEDACKRESOLUTION_G(x) \
(((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M)
#define TP_SHIFT_CNT_A 0x7dc0
#define SYNSHIFTMAX_S 24
#define SYNSHIFTMAX_M 0xffU
#define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S)
#define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M)
#define RXTSHIFTMAXR1_S 20
#define RXTSHIFTMAXR1_M 0xfU
#define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S)
#define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M)
#define RXTSHIFTMAXR2_S 16
#define RXTSHIFTMAXR2_M 0xfU
#define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S)
#define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M)
#define PERSHIFTBACKOFFMAX_S 12
#define PERSHIFTBACKOFFMAX_M 0xfU
#define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S)
#define PERSHIFTBACKOFFMAX_G(x) \
(((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M)
#define PERSHIFTMAX_S 8
#define PERSHIFTMAX_M 0xfU
#define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S)
#define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M)
#define KEEPALIVEMAXR1_S 4
#define KEEPALIVEMAXR1_M 0xfU
#define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S)
#define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M)
#define KEEPALIVEMAXR2_S 0
#define KEEPALIVEMAXR2_M 0xfU
#define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S)
#define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M)
#define TP_CCTRL_TABLE_A 0x7ddc
#define TP_MTU_TABLE_A 0x7de4
#define MTUINDEX_S 24
#define MTUINDEX_V(x) ((x) << MTUINDEX_S)
#define MTUWIDTH_S 16
#define MTUWIDTH_M 0xfU
#define MTUWIDTH_V(x) ((x) << MTUWIDTH_S)
#define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M)
#define MTUVALUE_S 0
#define MTUVALUE_M 0x3fffU
#define MTUVALUE_V(x) ((x) << MTUVALUE_S)
#define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M)
#define TP_RSS_LKP_TABLE_A 0x7dec
#define LKPTBLROWVLD_S 31
#define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S)
#define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U)
#define LKPTBLQUEUE1_S 10
#define LKPTBLQUEUE1_M 0x3ffU
#define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M)
#define LKPTBLQUEUE0_S 0
#define LKPTBLQUEUE0_M 0x3ffU
#define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M)
#define TP_PIO_ADDR_A 0x7e40
#define TP_PIO_DATA_A 0x7e44
#define TP_MIB_INDEX_A 0x7e50
#define TP_MIB_DATA_A 0x7e54
#define TP_INT_CAUSE_A 0x7e74
#define FLMTXFLSTEMPTY_S 30
#define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S)
#define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U)
#define TP_VLAN_PRI_MAP_A 0x140
#define FRAGMENTATION_S 9
#define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S)
#define FRAGMENTATION_F FRAGMENTATION_V(1U)
#define MPSHITTYPE_S 8
#define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S)
#define MPSHITTYPE_F MPSHITTYPE_V(1U)
#define MACMATCH_S 7
#define MACMATCH_V(x) ((x) << MACMATCH_S)
#define MACMATCH_F MACMATCH_V(1U)
#define ETHERTYPE_S 6
#define ETHERTYPE_V(x) ((x) << ETHERTYPE_S)
#define ETHERTYPE_F ETHERTYPE_V(1U)
#define PROTOCOL_S 5
#define PROTOCOL_V(x) ((x) << PROTOCOL_S)
#define PROTOCOL_F PROTOCOL_V(1U)
#define TOS_S 4
#define TOS_V(x) ((x) << TOS_S)
#define TOS_F TOS_V(1U)
#define VLAN_S 3
#define VLAN_V(x) ((x) << VLAN_S)
#define VLAN_F VLAN_V(1U)
#define VNIC_ID_S 2
#define VNIC_ID_V(x) ((x) << VNIC_ID_S)
#define VNIC_ID_F VNIC_ID_V(1U)
#define PORT_S 1
#define PORT_V(x) ((x) << PORT_S)
#define PORT_F PORT_V(1U)
#define FCOE_S 0
#define FCOE_V(x) ((x) << FCOE_S)
#define FCOE_F FCOE_V(1U)
#define FILTERMODE_S 15
#define FILTERMODE_V(x) ((x) << FILTERMODE_S)
#define FILTERMODE_F FILTERMODE_V(1U)
#define FCOEMASK_S 14
#define FCOEMASK_V(x) ((x) << FCOEMASK_S)
#define FCOEMASK_F FCOEMASK_V(1U)
#define TP_INGRESS_CONFIG_A 0x141
#define VNIC_S 11
#define VNIC_V(x) ((x) << VNIC_S)
#define VNIC_F VNIC_V(1U)
#define CSUM_HAS_PSEUDO_HDR_S 10
#define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S)
#define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U)
#define TP_MIB_MAC_IN_ERR_0_A 0x0
#define TP_MIB_TCP_OUT_RST_A 0xc
#define TP_MIB_TCP_IN_SEG_HI_A 0x10
#define TP_MIB_TCP_IN_SEG_LO_A 0x11
#define TP_MIB_TCP_OUT_SEG_HI_A 0x12
#define TP_MIB_TCP_OUT_SEG_LO_A 0x13
#define TP_MIB_TCP_RXT_SEG_HI_A 0x14
#define TP_MIB_TCP_RXT_SEG_LO_A 0x15
#define TP_MIB_TNL_CNG_DROP_0_A 0x18
#define TP_MIB_TCP_V6IN_ERR_0_A 0x28
#define TP_MIB_TCP_V6OUT_RST_A 0x2c
#define TP_MIB_OFD_ARP_DROP_A 0x36
#define TP_MIB_TNL_DROP_0_A 0x44
#define TP_MIB_OFD_VLN_DROP_0_A 0x58
#define ULP_TX_INT_CAUSE_A 0x8dcc
#define PBL_BOUND_ERR_CH3_S 31
#define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S)
#define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U)
#define PBL_BOUND_ERR_CH2_S 30
#define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S)
#define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U)
#define PBL_BOUND_ERR_CH1_S 29
#define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S)
#define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U)
#define PBL_BOUND_ERR_CH0_S 28
#define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S)
#define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U)
#define PM_RX_INT_CAUSE_A 0x8fdc
#define PMRX_FRAMING_ERROR_F 0x003ffff0U
#define ZERO_E_CMD_ERROR_S 22
#define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)
#define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U)
#define OCSPI_PAR_ERROR_S 3
#define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)
#define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U)
#define DB_OPTIONS_PAR_ERROR_S 2
#define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)
#define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U)
#define IESPI_PAR_ERROR_S 1
#define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)
#define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U)
#define PMRX_E_PCMD_PAR_ERROR_S 0
#define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)
#define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U)
#define PM_TX_INT_CAUSE_A 0x8ffc
#define PCMD_LEN_OVFL0_S 31
#define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
#define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U)
#define PCMD_LEN_OVFL1_S 30
#define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)
#define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U)
#define PCMD_LEN_OVFL2_S 29
#define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)
#define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U)
#define ZERO_C_CMD_ERROR_S 28
#define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)
#define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U)
#define PMTX_FRAMING_ERROR_F 0x0ffffff0U
#define OESPI_PAR_ERROR_S 3
#define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)
#define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U)
#define ICSPI_PAR_ERROR_S 1
#define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)
#define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U)
#define PMTX_C_PCMD_PAR_ERROR_S 0
#define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)
#define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U)
#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
......@@ -959,41 +1562,57 @@
#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
#define MAC_PORT_CFG2 0x818
#define MAC_PORT_MAGIC_MACID_LO 0x824
#define MAC_PORT_MAGIC_MACID_HI 0x828
#define MAC_PORT_EPIO_DATA0 0x8c0
#define MAC_PORT_EPIO_DATA1 0x8c4
#define MAC_PORT_EPIO_DATA2 0x8c8
#define MAC_PORT_EPIO_DATA3 0x8cc
#define MAC_PORT_EPIO_OP 0x8d0
#define MPS_CMN_CTL 0x9000
#define NUMPORTS_MASK 0x00000003U
#define NUMPORTS_SHIFT 0
#define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT)
#define MPS_INT_CAUSE 0x9008
#define STATINT 0x00000020U
#define TXINT 0x00000010U
#define RXINT 0x00000008U
#define TRCINT 0x00000004U
#define CLSINT 0x00000002U
#define PLINT 0x00000001U
#define MPS_TX_INT_CAUSE 0x9408
#define PORTERR 0x00010000U
#define FRMERR 0x00008000U
#define SECNTERR 0x00004000U
#define BUBBLE 0x00002000U
#define TXDESCFIFO 0x00001e00U
#define TXDATAFIFO 0x000001e0U
#define NCSIFIFO 0x00000010U
#define TPFIFO 0x0000000fU
#define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
#define MAC_PORT_EPIO_DATA0_A 0x8c0
#define MAC_PORT_EPIO_DATA1_A 0x8c4
#define MAC_PORT_EPIO_DATA2_A 0x8c8
#define MAC_PORT_EPIO_DATA3_A 0x8cc
#define MAC_PORT_EPIO_OP_A 0x8d0
#define MAC_PORT_CFG2_A 0x818
#define MPS_CMN_CTL_A 0x9000
#define NUMPORTS_S 0
#define NUMPORTS_M 0x3U
#define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)
#define MPS_INT_CAUSE_A 0x9008
#define MPS_TX_INT_CAUSE_A 0x9408
#define FRMERR_S 15
#define FRMERR_V(x) ((x) << FRMERR_S)
#define FRMERR_F FRMERR_V(1U)
#define SECNTERR_S 14
#define SECNTERR_V(x) ((x) << SECNTERR_S)
#define SECNTERR_F SECNTERR_V(1U)
#define BUBBLE_S 13
#define BUBBLE_V(x) ((x) << BUBBLE_S)
#define BUBBLE_F BUBBLE_V(1U)
#define TXDESCFIFO_S 9
#define TXDESCFIFO_M 0xfU
#define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)
#define TXDATAFIFO_S 5
#define TXDATAFIFO_M 0xfU
#define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)
#define NCSIFIFO_S 4
#define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)
#define NCSIFIFO_F NCSIFIFO_V(1U)
#define TPFIFO_S 0
#define TPFIFO_M 0xfU
#define TPFIFO_V(x) ((x) << TPFIFO_S)
#define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614
#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620
#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c
#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
......@@ -1027,294 +1646,385 @@
#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
#define MPS_TRC_CFG 0x9800
#define TRCFIFOEMPTY 0x00000010U
#define TRCIGNOREDROPINPUT 0x00000008U
#define TRCKEEPDUPLICATES 0x00000004U
#define TRCEN 0x00000002U
#define TRCMULTIFILTER 0x00000001U
#define MPS_TRC_RSS_CONTROL 0x9808
#define MPS_T5_TRC_RSS_CONTROL 0xa00c
#define RSSCONTROL_MASK 0x00ff0000U
#define RSSCONTROL_SHIFT 16
#define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT)
#define QUEUENUMBER_MASK 0x0000ffffU
#define QUEUENUMBER_SHIFT 0
#define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT)
#define MPS_TRC_FILTER_MATCH_CTL_A 0x9810
#define TFINVERTMATCH 0x01000000U
#define TFPKTTOOLARGE 0x00800000U
#define TFEN 0x00400000U
#define TFPORT_MASK 0x003c0000U
#define TFPORT_SHIFT 18
#define TFPORT(x) ((x) << TFPORT_SHIFT)
#define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT)
#define TFDROP 0x00020000U
#define TFSOPEOPERR 0x00010000U
#define TFLENGTH_MASK 0x00001f00U
#define TFLENGTH_SHIFT 8
#define TFLENGTH(x) ((x) << TFLENGTH_SHIFT)
#define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT)
#define TFOFFSET_MASK 0x0000001fU
#define TFOFFSET_SHIFT 0
#define TFOFFSET(x) ((x) << TFOFFSET_SHIFT)
#define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT)
#define MPS_TRC_FILTER_MATCH_CTL_B 0x9820
#define TFMINPKTSIZE_MASK 0x01ff0000U
#define TFMINPKTSIZE_SHIFT 16
#define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT)
#define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT)
#define TFCAPTUREMAX_MASK 0x00003fffU
#define TFCAPTUREMAX_SHIFT 0
#define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT)
#define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT)
#define MPS_TRC_INT_CAUSE 0x985c
#define MISCPERR 0x00000100U
#define PKTFIFO 0x000000f0U
#define FILTMEM 0x0000000fU
#define MPS_TRC_FILTER0_MATCH 0x9c00
#define MPS_TRC_FILTER0_DONT_CARE 0x9c80
#define MPS_TRC_FILTER1_MATCH 0x9d00
#define MPS_CLS_INT_CAUSE 0xd028
#define PLERRENB 0x00000008U
#define HASHSRAM 0x00000004U
#define MATCHTCAM 0x00000002U
#define MATCHSRAM 0x00000001U
#define MPS_RX_PERR_INT_CAUSE 0x11074
#define CPL_INTR_CAUSE 0x19054
#define CIM_OP_MAP_PERR 0x00000020U
#define CIM_OVFL_ERROR 0x00000010U
#define TP_FRAMING_ERROR 0x00000008U
#define SGE_FRAMING_ERROR 0x00000004U
#define CIM_FRAMING_ERROR 0x00000002U
#define ZERO_SWITCH_ERROR 0x00000001U
#define SMB_INT_CAUSE 0x19090
#define MSTTXFIFOPARINT 0x00200000U
#define MSTRXFIFOPARINT 0x00100000U
#define SLVFIFOPARINT 0x00080000U
#define ULP_RX_INT_CAUSE 0x19158
#define ULP_RX_ISCSI_TAGMASK 0x19164
#define ULP_RX_ISCSI_PSZ 0x19168
#define HPZ3_MASK 0x0f000000U
#define HPZ3_SHIFT 24
#define HPZ3(x) ((x) << HPZ3_SHIFT)
#define HPZ2_MASK 0x000f0000U
#define HPZ2_SHIFT 16
#define HPZ2(x) ((x) << HPZ2_SHIFT)
#define HPZ1_MASK 0x00000f00U
#define HPZ1_SHIFT 8
#define HPZ1(x) ((x) << HPZ1_SHIFT)
#define HPZ0_MASK 0x0000000fU
#define HPZ0_SHIFT 0
#define HPZ0(x) ((x) << HPZ0_SHIFT)
#define ULP_RX_TDDP_PSZ 0x19178
#define SF_DATA 0x193f8
#define SF_OP 0x193fc
#define SF_BUSY 0x80000000U
#define SF_LOCK 0x00000010U
#define SF_CONT 0x00000008U
#define BYTECNT_MASK 0x00000006U
#define BYTECNT_SHIFT 1
#define BYTECNT(x) ((x) << BYTECNT_SHIFT)
#define OP_WR 0x00000001U
#define PL_PF_INT_CAUSE 0x3c0
#define PFSW 0x00000008U
#define PFSGE 0x00000004U
#define PFCIM 0x00000002U
#define PFMPS 0x00000001U
#define PL_PF_INT_ENABLE 0x3c4
#define PL_PF_CTL 0x3c8
#define SWINT 0x00000001U
#define PL_WHOAMI 0x19400
#define SOURCEPF_MASK 0x00000700U
#define SOURCEPF_SHIFT 8
#define SOURCEPF(x) ((x) << SOURCEPF_SHIFT)
#define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)
#define ISVF 0x00000080U
#define VFID_MASK 0x0000007fU
#define VFID_SHIFT 0
#define VFID(x) ((x) << VFID_SHIFT)
#define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT)
#define PL_INT_CAUSE 0x1940c
#define ULP_TX 0x08000000U
#define SGE 0x04000000U
#define HMA 0x02000000U
#define CPL_SWITCH 0x01000000U
#define ULP_RX 0x00800000U
#define PM_RX 0x00400000U
#define PM_TX 0x00200000U
#define MA 0x00100000U
#define TP 0x00080000U
#define LE 0x00040000U
#define EDC1 0x00020000U
#define EDC0 0x00010000U
#define MC 0x00008000U
#define PCIE 0x00004000U
#define PMU 0x00002000U
#define XGMAC_KR1 0x00001000U
#define XGMAC_KR0 0x00000800U
#define XGMAC1 0x00000400U
#define XGMAC0 0x00000200U
#define SMB 0x00000100U
#define SF 0x00000080U
#define PL 0x00000040U
#define NCSI 0x00000020U
#define MPS 0x00000010U
#define MI 0x00000008U
#define DBG 0x00000004U
#define I2CM 0x00000002U
#define CIM 0x00000001U
#define MC1 0x31
#define PL_INT_ENABLE 0x19410
#define PL_INT_MAP0 0x19414
#define PL_RST 0x19428
#define PIORST 0x00000002U
#define PIORSTMODE 0x00000001U
#define PL_PL_INT_CAUSE 0x19430
#define FATALPERR 0x00000010U
#define PERRVFID 0x00000001U
#define PL_REV 0x1943c
#define S_REV 0
#define M_REV 0xfU
#define V_REV(x) ((x) << S_REV)
#define G_REV(x) (((x) >> S_REV) & M_REV)
#define LE_DB_CONFIG 0x19c04
#define HASHEN 0x00100000U
#define LE_DB_SERVER_INDEX 0x19c18
#define LE_DB_ACT_CNT_IPV4 0x19c20
#define LE_DB_ACT_CNT_IPV6 0x19c24
#define LE_DB_INT_CAUSE 0x19c3c
#define REQQPARERR 0x00010000U
#define UNKNOWNCMD 0x00008000U
#define PARITYERR 0x00000040U
#define LIPMISS 0x00000020U
#define LIP0 0x00000010U
#define LE_DB_TID_HASHBASE 0x19df8
#define NCSI_INT_CAUSE 0x1a0d8
#define CIM_DM_PRTY_ERR 0x00000100U
#define MPS_DM_PRTY_ERR 0x00000080U
#define TXFIFO_PRTY_ERR 0x00000002U
#define RXFIFO_PRTY_ERR 0x00000001U
#define XGMAC_PORT_CFG2 0x1018
#define PATEN 0x00040000U
#define MAGICEN 0x00020000U
#define XGMAC_PORT_MAGIC_MACID_LO 0x1024
#define XGMAC_PORT_MAGIC_MACID_HI 0x1028
#define MPS_TRC_CFG_A 0x9800
#define TRCFIFOEMPTY_S 4
#define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)
#define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U)
#define TRCIGNOREDROPINPUT_S 3
#define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)
#define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U)
#define TRCKEEPDUPLICATES_S 2
#define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)
#define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U)
#define XGMAC_PORT_EPIO_DATA0 0x10c0
#define XGMAC_PORT_EPIO_DATA1 0x10c4
#define XGMAC_PORT_EPIO_DATA2 0x10c8
#define XGMAC_PORT_EPIO_DATA3 0x10cc
#define XGMAC_PORT_EPIO_OP 0x10d0
#define EPIOWR 0x00000100U
#define ADDRESS_MASK 0x000000ffU
#define ADDRESS_SHIFT 0
#define ADDRESS(x) ((x) << ADDRESS_SHIFT)
#define TRCEN_S 1
#define TRCEN_V(x) ((x) << TRCEN_S)
#define TRCEN_F TRCEN_V(1U)
#define MAC_PORT_INT_CAUSE 0x8dc
#define XGMAC_PORT_INT_CAUSE 0x10dc
#define TRCMULTIFILTER_S 0
#define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)
#define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U)
#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
#define MPS_TRC_RSS_CONTROL_A 0x9808
#define MPS_T5_TRC_RSS_CONTROL_A 0xa00c
#define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
#define RSSCONTROL_S 16
#define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)
#define S_TX_MOD_QUEUE_REQ_MAP 0
#define M_TX_MOD_QUEUE_REQ_MAP 0xffffU
#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
#define QUEUENUMBER_S 0
#define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)
#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
#define MPS_TRC_INT_CAUSE_A 0x985c
#define S_TX_MODQ_WEIGHT3 24
#define M_TX_MODQ_WEIGHT3 0xffU
#define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
#define MISCPERR_S 8
#define MISCPERR_V(x) ((x) << MISCPERR_S)
#define MISCPERR_F MISCPERR_V(1U)
#define S_TX_MODQ_WEIGHT2 16
#define M_TX_MODQ_WEIGHT2 0xffU
#define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
#define PKTFIFO_S 4
#define PKTFIFO_M 0xfU
#define PKTFIFO_V(x) ((x) << PKTFIFO_S)
#define S_TX_MODQ_WEIGHT1 8
#define M_TX_MODQ_WEIGHT1 0xffU
#define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
#define FILTMEM_S 0
#define FILTMEM_M 0xfU
#define FILTMEM_V(x) ((x) << FILTMEM_S)
#define S_TX_MODQ_WEIGHT0 0
#define M_TX_MODQ_WEIGHT0 0xffU
#define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
#define MPS_CLS_INT_CAUSE_A 0xd028
#define A_TP_TX_SCHED_HDR 0x23
#define HASHSRAM_S 2
#define HASHSRAM_V(x) ((x) << HASHSRAM_S)
#define HASHSRAM_F HASHSRAM_V(1U)
#define A_TP_TX_SCHED_FIFO 0x24
#define MATCHTCAM_S 1
#define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)
#define MATCHTCAM_F MATCHTCAM_V(1U)
#define A_TP_TX_SCHED_PCMD 0x25
#define MATCHSRAM_S 0
#define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)
#define MATCHSRAM_F MATCHSRAM_V(1U)
#define S_VNIC 11
#define V_VNIC(x) ((x) << S_VNIC)
#define F_VNIC V_VNIC(1U)
#define MPS_RX_PERR_INT_CAUSE_A 0x11074
#define S_FRAGMENTATION 9
#define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
#define F_FRAGMENTATION V_FRAGMENTATION(1U)
#define CPL_INTR_CAUSE_A 0x19054
#define S_MPSHITTYPE 8
#define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
#define F_MPSHITTYPE V_MPSHITTYPE(1U)
#define CIM_OP_MAP_PERR_S 5
#define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)
#define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U)
#define S_MACMATCH 7
#define V_MACMATCH(x) ((x) << S_MACMATCH)
#define F_MACMATCH V_MACMATCH(1U)
#define CIM_OVFL_ERROR_S 4
#define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)
#define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U)
#define S_ETHERTYPE 6
#define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
#define F_ETHERTYPE V_ETHERTYPE(1U)
#define TP_FRAMING_ERROR_S 3
#define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)
#define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U)
#define S_PROTOCOL 5
#define V_PROTOCOL(x) ((x) << S_PROTOCOL)
#define F_PROTOCOL V_PROTOCOL(1U)
#define SGE_FRAMING_ERROR_S 2
#define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)
#define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U)
#define S_TOS 4
#define V_TOS(x) ((x) << S_TOS)
#define F_TOS V_TOS(1U)
#define CIM_FRAMING_ERROR_S 1
#define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)
#define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U)
#define S_VLAN 3
#define V_VLAN(x) ((x) << S_VLAN)
#define F_VLAN V_VLAN(1U)
#define ZERO_SWITCH_ERROR_S 0
#define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)
#define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U)
#define S_VNIC_ID 2
#define V_VNIC_ID(x) ((x) << S_VNIC_ID)
#define F_VNIC_ID V_VNIC_ID(1U)
#define SMB_INT_CAUSE_A 0x19090
#define S_PORT 1
#define V_PORT(x) ((x) << S_PORT)
#define F_PORT V_PORT(1U)
#define MSTTXFIFOPARINT_S 21
#define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)
#define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U)
#define S_FCOE 0
#define V_FCOE(x) ((x) << S_FCOE)
#define F_FCOE V_FCOE(1U)
#define MSTRXFIFOPARINT_S 20
#define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)
#define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U)
#define SLVFIFOPARINT_S 19
#define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)
#define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U)
#define ULP_RX_INT_CAUSE_A 0x19158
#define ULP_RX_ISCSI_TAGMASK_A 0x19164
#define ULP_RX_ISCSI_PSZ_A 0x19168
#define HPZ3_S 24
#define HPZ3_V(x) ((x) << HPZ3_S)
#define HPZ2_S 16
#define HPZ2_V(x) ((x) << HPZ2_S)
#define HPZ1_S 8
#define HPZ1_V(x) ((x) << HPZ1_S)
#define HPZ0_S 0
#define HPZ0_V(x) ((x) << HPZ0_S)
#define ULP_RX_TDDP_PSZ_A 0x19178
/* registers for module SF */
#define SF_DATA_A 0x193f8
#define SF_OP_A 0x193fc
#define SF_BUSY_S 31
#define SF_BUSY_V(x) ((x) << SF_BUSY_S)
#define SF_BUSY_F SF_BUSY_V(1U)
#define SF_LOCK_S 4
#define SF_LOCK_V(x) ((x) << SF_LOCK_S)
#define SF_LOCK_F SF_LOCK_V(1U)
#define SF_CONT_S 3
#define SF_CONT_V(x) ((x) << SF_CONT_S)
#define SF_CONT_F SF_CONT_V(1U)
#define BYTECNT_S 1
#define BYTECNT_V(x) ((x) << BYTECNT_S)
#define OP_S 0
#define OP_V(x) ((x) << OP_S)
#define OP_F OP_V(1U)
#define PL_PF_INT_CAUSE_A 0x3c0
#define PFSW_S 3
#define PFSW_V(x) ((x) << PFSW_S)
#define PFSW_F PFSW_V(1U)
#define PFCIM_S 1
#define PFCIM_V(x) ((x) << PFCIM_S)
#define PFCIM_F PFCIM_V(1U)
#define PL_PF_INT_ENABLE_A 0x3c4
#define PL_PF_CTL_A 0x3c8
#define PL_WHOAMI_A 0x19400
#define SOURCEPF_S 8
#define SOURCEPF_M 0x7U
#define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)
#define PL_INT_CAUSE_A 0x1940c
#define ULP_TX_S 27
#define ULP_TX_V(x) ((x) << ULP_TX_S)
#define ULP_TX_F ULP_TX_V(1U)
#define SGE_S 26
#define SGE_V(x) ((x) << SGE_S)
#define SGE_F SGE_V(1U)
#define CPL_SWITCH_S 24
#define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S)
#define CPL_SWITCH_F CPL_SWITCH_V(1U)
#define ULP_RX_S 23
#define ULP_RX_V(x) ((x) << ULP_RX_S)
#define ULP_RX_F ULP_RX_V(1U)
#define PM_RX_S 22
#define PM_RX_V(x) ((x) << PM_RX_S)
#define PM_RX_F PM_RX_V(1U)
#define PM_TX_S 21
#define PM_TX_V(x) ((x) << PM_TX_S)
#define PM_TX_F PM_TX_V(1U)
#define MA_S 20
#define MA_V(x) ((x) << MA_S)
#define MA_F MA_V(1U)
#define TP_S 19
#define TP_V(x) ((x) << TP_S)
#define TP_F TP_V(1U)
#define LE_S 18
#define LE_V(x) ((x) << LE_S)
#define LE_F LE_V(1U)
#define EDC1_S 17
#define EDC1_V(x) ((x) << EDC1_S)
#define EDC1_F EDC1_V(1U)
#define EDC0_S 16
#define EDC0_V(x) ((x) << EDC0_S)
#define EDC0_F EDC0_V(1U)
#define MC_S 15
#define MC_V(x) ((x) << MC_S)
#define MC_F MC_V(1U)
#define PCIE_S 14
#define PCIE_V(x) ((x) << PCIE_S)
#define PCIE_F PCIE_V(1U)
#define XGMAC_KR1_S 12
#define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)
#define XGMAC_KR1_F XGMAC_KR1_V(1U)
#define XGMAC_KR0_S 11
#define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S)
#define XGMAC_KR0_F XGMAC_KR0_V(1U)
#define XGMAC1_S 10
#define XGMAC1_V(x) ((x) << XGMAC1_S)
#define XGMAC1_F XGMAC1_V(1U)
#define XGMAC0_S 9
#define XGMAC0_V(x) ((x) << XGMAC0_S)
#define XGMAC0_F XGMAC0_V(1U)
#define SMB_S 8
#define SMB_V(x) ((x) << SMB_S)
#define SMB_F SMB_V(1U)
#define SF_S 7
#define SF_V(x) ((x) << SF_S)
#define SF_F SF_V(1U)
#define PL_S 6
#define PL_V(x) ((x) << PL_S)
#define PL_F PL_V(1U)
#define NCSI_S 5
#define NCSI_V(x) ((x) << NCSI_S)
#define NCSI_F NCSI_V(1U)
#define MPS_S 4
#define MPS_V(x) ((x) << MPS_S)
#define MPS_F MPS_V(1U)
#define CIM_S 0
#define CIM_V(x) ((x) << CIM_S)
#define CIM_F CIM_V(1U)
#define MC1_S 31
#define PL_INT_ENABLE_A 0x19410
#define PL_INT_MAP0_A 0x19414
#define PL_RST_A 0x19428
#define PIORST_S 1
#define PIORST_V(x) ((x) << PIORST_S)
#define PIORST_F PIORST_V(1U)
#define PIORSTMODE_S 0
#define PIORSTMODE_V(x) ((x) << PIORSTMODE_S)
#define PIORSTMODE_F PIORSTMODE_V(1U)
#define PL_PL_INT_CAUSE_A 0x19430
#define FATALPERR_S 4
#define FATALPERR_V(x) ((x) << FATALPERR_S)
#define FATALPERR_F FATALPERR_V(1U)
#define PERRVFID_S 0
#define PERRVFID_V(x) ((x) << PERRVFID_S)
#define PERRVFID_F PERRVFID_V(1U)
#define PL_REV_A 0x1943c
#define REV_S 0
#define REV_M 0xfU
#define REV_V(x) ((x) << REV_S)
#define REV_G(x) (((x) >> REV_S) & REV_M)
#define LE_DB_INT_CAUSE_A 0x19c3c
#define REQQPARERR_S 16
#define REQQPARERR_V(x) ((x) << REQQPARERR_S)
#define REQQPARERR_F REQQPARERR_V(1U)
#define UNKNOWNCMD_S 15
#define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S)
#define UNKNOWNCMD_F UNKNOWNCMD_V(1U)
#define PARITYERR_S 6
#define PARITYERR_V(x) ((x) << PARITYERR_S)
#define PARITYERR_F PARITYERR_V(1U)
#define LIPMISS_S 5
#define LIPMISS_V(x) ((x) << LIPMISS_S)
#define LIPMISS_F LIPMISS_V(1U)
#define LIP0_S 4
#define LIP0_V(x) ((x) << LIP0_S)
#define LIP0_F LIP0_V(1U)
#define NCSI_INT_CAUSE_A 0x1a0d8
#define CIM_DM_PRTY_ERR_S 8
#define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S)
#define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U)
#define MPS_DM_PRTY_ERR_S 7
#define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S)
#define MPS_DM_PRTY_ERR_F MPS_DM_PRTY_ERR_V(1U)
#define TXFIFO_PRTY_ERR_S 1
#define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S)
#define TXFIFO_PRTY_ERR_F TXFIFO_PRTY_ERR_V(1U)
#define RXFIFO_PRTY_ERR_S 0
#define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S)
#define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U)
#define XGMAC_PORT_CFG2_A 0x1018
#define PATEN_S 18
#define PATEN_V(x) ((x) << PATEN_S)
#define PATEN_F PATEN_V(1U)
#define MAGICEN_S 17
#define MAGICEN_V(x) ((x) << MAGICEN_S)
#define MAGICEN_F MAGICEN_V(1U)
#define XGMAC_PORT_MAGIC_MACID_LO 0x1024
#define XGMAC_PORT_MAGIC_MACID_HI 0x1028
#define XGMAC_PORT_EPIO_DATA0_A 0x10c0
#define XGMAC_PORT_EPIO_DATA1_A 0x10c4
#define XGMAC_PORT_EPIO_DATA2_A 0x10c8
#define XGMAC_PORT_EPIO_DATA3_A 0x10cc
#define XGMAC_PORT_EPIO_OP_A 0x10d0
#define EPIOWR_S 8
#define EPIOWR_V(x) ((x) << EPIOWR_S)
#define EPIOWR_F EPIOWR_V(1U)
#define ADDRESS_S 0
#define ADDRESS_V(x) ((x) << ADDRESS_S)
#define MAC_PORT_INT_CAUSE_A 0x8dc
#define XGMAC_PORT_INT_CAUSE_A 0x10dc
#define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
#define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
#define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34
#define TX_MOD_QUEUE_REQ_MAP_S 0
#define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S)
#define TX_MODQ_WEIGHT3_S 24
#define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S)
#define TX_MODQ_WEIGHT2_S 16
#define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S)
#define TX_MODQ_WEIGHT1_S 8
#define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S)
#define TX_MODQ_WEIGHT0_S 0
#define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S)
#define TP_TX_SCHED_HDR_A 0x23
#define TP_TX_SCHED_FIFO_A 0x24
#define TP_TX_SCHED_PCMD_A 0x25
#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
......@@ -1329,62 +2039,27 @@
#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
#define MC_P_BIST_CMD 0x41400
#define MC_P_BIST_CMD_ADDR 0x41404
#define MC_P_BIST_CMD_LEN 0x41408
#define MC_P_BIST_DATA_PATTERN 0x4140c
#define MC_P_BIST_STATUS_RDATA 0x41488
#define EDC_T50_BASE_ADDR 0x50000
#define EDC_H_BIST_CMD 0x50004
#define EDC_H_BIST_CMD_ADDR 0x50008
#define EDC_H_BIST_CMD_LEN 0x5000c
#define EDC_H_BIST_DATA_PATTERN 0x50010
#define EDC_H_BIST_STATUS_RDATA 0x50028
#define EDC_T51_BASE_ADDR 0x50800
#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
#define MC_P_BIST_CMD_A 0x41400
#define MC_P_BIST_CMD_ADDR_A 0x41404
#define MC_P_BIST_CMD_LEN_A 0x41408
#define MC_P_BIST_DATA_PATTERN_A 0x4140c
#define MC_P_BIST_STATUS_RDATA_A 0x41488
#define A_PL_VF_REV 0x4
#define A_PL_VF_WHOAMI 0x0
#define A_PL_VF_REVISION 0x8
#define EDC_T50_BASE_ADDR 0x50000
#define S_CHIPID 4
#define M_CHIPID 0xfU
#define V_CHIPID(x) ((x) << S_CHIPID)
#define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
#define EDC_H_BIST_CMD_A 0x50004
#define EDC_H_BIST_CMD_ADDR_A 0x50008
#define EDC_H_BIST_CMD_LEN_A 0x5000c
#define EDC_H_BIST_DATA_PATTERN_A 0x50010
#define EDC_H_BIST_STATUS_RDATA_A 0x50028
/* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
* Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
* selects for a particular field being present. These fields, when present
* in the Compressed Filter Tuple, have the following widths in bits.
*/
#define W_FT_FCOE 1
#define W_FT_PORT 3
#define W_FT_VNIC_ID 17
#define W_FT_VLAN 17
#define W_FT_TOS 8
#define W_FT_PROTOCOL 8
#define W_FT_ETHERTYPE 16
#define W_FT_MACMATCH 9
#define W_FT_MPSHITTYPE 3
#define W_FT_FRAGMENTATION 1
/* Some of the Compressed Filter Tuple fields have internal structure. These
* bit shifts/masks describe those structures. All shifts are relative to the
* base position of the fields within the Compressed Filter Tuple
*/
#define S_FT_VLAN_VLD 16
#define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD)
#define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U)
#define S_FT_VNID_ID_VF 0
#define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF)
#define EDC_T51_BASE_ADDR 0x50800
#define S_FT_VNID_ID_PF 7
#define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF)
#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
#define S_FT_VNID_ID_VLD 16
#define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD)
#define PL_VF_REV_A 0x4
#define PL_VF_WHOAMI_A 0x0
#define PL_VF_REVISION_A 0x8
#endif /* __T4_REGS_H */
drivers/net/ethernet/chelsio/cxgb4/t4_values.h 0 → 100644
View file @ a515abd7
/*
* This file is part of the Chelsio T4 Ethernet driver for Linux.
*
* Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __T4_VALUES_H__
#define __T4_VALUES_H__
/* This file contains definitions for various T4 register value hardware
* constants. The types of values encoded here are predominantly those for
* register fields which control "modal" behavior. For the most part, we do
* not include definitions for register fields which are simple numeric
* metrics, etc.
*/
/* SGE register field values.
*/
/* CONTROL1 register */
#define RXPKTCPLMODE_SPLIT_X 1
#define INGPCIEBOUNDARY_SHIFT_X 5
#define INGPCIEBOUNDARY_32B_X 0
#define INGPADBOUNDARY_SHIFT_X 5
/* CONTROL2 register */
#define INGPACKBOUNDARY_SHIFT_X 5
#define INGPACKBOUNDARY_16B_X 0
/* GTS register */
#define SGE_TIMERREGS 6
/* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
* The User Doorbells are each 128 bytes in length with a Simple Doorbell at
* offsets 8x and a Write Combining single 64-byte Egress Queue Unit
* (IDXSIZE_UNIT_X) Gather Buffer interface at offset 64. For Ingress Queues,
* we have a Going To Sleep register at offsets 8x+4.
*
* As noted above, we have many instances of the Simple Doorbell and Going To
* Sleep registers at offsets 8x and 8x+4, respectively. We want to use a
* non-64-byte aligned offset for the Simple Doorbell in order to attempt to
* avoid buffering of the writes to the Simple Doorbell and we want to use a
* non-contiguous offset for the Going To Sleep writes in order to avoid
* possible combining between them.
*/
#define SGE_UDB_SIZE 128
#define SGE_UDB_KDOORBELL 8
#define SGE_UDB_GTS 20
#define SGE_UDB_WCDOORBELL 64
/* PCI-E definitions */
#define WINDOW_SHIFT_X 10
#define PCIEOFST_SHIFT_X 10
/* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
* Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
* selects for a particular field being present. These fields, when present
* in the Compressed Filter Tuple, have the following widths in bits.
*/
#define FT_FCOE_W 1
#define FT_PORT_W 3
#define FT_VNIC_ID_W 17
#define FT_VLAN_W 17
#define FT_TOS_W 8
#define FT_PROTOCOL_W 8
#define FT_ETHERTYPE_W 16
#define FT_MACMATCH_W 9
#define FT_MPSHITTYPE_W 3
#define FT_FRAGMENTATION_W 1
/* Some of the Compressed Filter Tuple fields have internal structure. These
* bit shifts/masks describe those structures. All shifts are relative to the
* base position of the fields within the Compressed Filter Tuple
*/
#define FT_VLAN_VLD_S 16
#define FT_VLAN_VLD_V(x) ((x) << FT_VLAN_VLD_S)
#define FT_VLAN_VLD_F FT_VLAN_VLD_V(1U)
#define FT_VNID_ID_VF_S 0
#define FT_VNID_ID_VF_V(x) ((x) << FT_VNID_ID_VF_S)
#define FT_VNID_ID_PF_S 7
#define FT_VNID_ID_PF_V(x) ((x) << FT_VNID_ID_PF_S)
#define FT_VNID_ID_VLD_S 16
#define FT_VNID_ID_VLD_V(x) ((x) << FT_VNID_ID_VLD_S)
#endif /* __T4_VALUES_H__ */
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
View file @ a515abd7
......@@ -380,9 +380,9 @@ static void qenable(struct sge_rspq *rspq)
* enable interrupts.
*/
t4_write_reg(rspq->adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
CIDXINC(0) |
SEINTARM(rspq->intr_params) |
INGRESSQID(rspq->cntxt_id));
CIDXINC_V(0) |
SEINTARM_V(rspq->intr_params) |
INGRESSQID_V(rspq->cntxt_id));
}
/*
......@@ -403,9 +403,9 @@ static void enable_rx(struct adapter *adapter)
*/
if (adapter->flags & USING_MSI)
t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
CIDXINC(0) |
SEINTARM(s->intrq.intr_params) |
INGRESSQID(s->intrq.cntxt_id));
CIDXINC_V(0) |
SEINTARM_V(s->intrq.intr_params) |
INGRESSQID_V(s->intrq.cntxt_id));
}
......@@ -1673,7 +1673,7 @@ static void cxgb4vf_get_regs(struct net_device *dev,
reg_block_dump(adapter, regbuf,
T4VF_PL_BASE_ADDR + T4VF_MOD_MAP_PL_FIRST,
T4VF_PL_BASE_ADDR + (is_t4(adapter->params.chip)
? A_PL_VF_WHOAMI : A_PL_VF_REVISION));
? PL_VF_WHOAMI_A : PL_VF_REVISION_A));
reg_block_dump(adapter, regbuf,
T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_FIRST,
T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_LAST);
......@@ -2294,26 +2294,22 @@ static int adap_init0(struct adapter *adapter)
* threshold values from the SGE parameters.
*/
s->timer_val[0] = core_ticks_to_us(adapter,
TIMERVALUE0_GET(sge_params->sge_timer_value_0_and_1));
TIMERVALUE0_G(sge_params->sge_timer_value_0_and_1));
s->timer_val[1] = core_ticks_to_us(adapter,
TIMERVALUE1_GET(sge_params->sge_timer_value_0_and_1));
TIMERVALUE1_G(sge_params->sge_timer_value_0_and_1));
s->timer_val[2] = core_ticks_to_us(adapter,
TIMERVALUE0_GET(sge_params->sge_timer_value_2_and_3));
TIMERVALUE0_G(sge_params->sge_timer_value_2_and_3));
s->timer_val[3] = core_ticks_to_us(adapter,
TIMERVALUE1_GET(sge_params->sge_timer_value_2_and_3));
TIMERVALUE1_G(sge_params->sge_timer_value_2_and_3));
s->timer_val[4] = core_ticks_to_us(adapter,
TIMERVALUE0_GET(sge_params->sge_timer_value_4_and_5));
TIMERVALUE0_G(sge_params->sge_timer_value_4_and_5));
s->timer_val[5] = core_ticks_to_us(adapter,
TIMERVALUE1_GET(sge_params->sge_timer_value_4_and_5));
s->counter_val[0] =
THRESHOLD_0_GET(sge_params->sge_ingress_rx_threshold);
s->counter_val[1] =
THRESHOLD_1_GET(sge_params->sge_ingress_rx_threshold);
s->counter_val[2] =
THRESHOLD_2_GET(sge_params->sge_ingress_rx_threshold);
s->counter_val[3] =
THRESHOLD_3_GET(sge_params->sge_ingress_rx_threshold);
TIMERVALUE1_G(sge_params->sge_timer_value_4_and_5));
s->counter_val[0] = THRESHOLD_0_G(sge_params->sge_ingress_rx_threshold);
s->counter_val[1] = THRESHOLD_1_G(sge_params->sge_ingress_rx_threshold);
s->counter_val[2] = THRESHOLD_2_G(sge_params->sge_ingress_rx_threshold);
s->counter_val[3] = THRESHOLD_3_G(sge_params->sge_ingress_rx_threshold);
/*
* Grab our Virtual Interface resource allocation, extract the
......
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
View file @ a515abd7
......@@ -47,6 +47,7 @@
#include "t4vf_defs.h"
#include "../cxgb4/t4_regs.h"
#include "../cxgb4/t4_values.h"
#include "../cxgb4/t4fw_api.h"
#include "../cxgb4/t4_msg.h"
......@@ -531,11 +532,11 @@ static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
*/
if (fl->pend_cred >= FL_PER_EQ_UNIT) {
if (is_t4(adapter->params.chip))
val = PIDX(fl->pend_cred / FL_PER_EQ_UNIT);
val = PIDX_V(fl->pend_cred / FL_PER_EQ_UNIT);
else
val = PIDX_T5(fl->pend_cred / FL_PER_EQ_UNIT) |
DBTYPE(1);
val |= DBPRIO(1);
val = PIDX_T5_V(fl->pend_cred / FL_PER_EQ_UNIT) |
DBTYPE_F;
val |= DBPRIO_F;
/* Make sure all memory writes to the Free List queue are
* committed before we tell the hardware about them.
......@@ -549,9 +550,9 @@ static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
if (unlikely(fl->bar2_addr == NULL)) {
t4_write_reg(adapter,
T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
QID(fl->cntxt_id) | val);
QID_V(fl->cntxt_id) | val);
} else {
writel(val | QID(fl->bar2_qid),
writel(val | QID_V(fl->bar2_qid),
fl->bar2_addr + SGE_UDB_KDOORBELL);
/* This Write memory Barrier will force the write to
......@@ -979,12 +980,12 @@ static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
* doorbell mechanism; otherwise use the new BAR2 mechanism.
*/
if (unlikely(tq->bar2_addr == NULL)) {
u32 val = PIDX(n);
u32 val = PIDX_V(n);
t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
QID(tq->cntxt_id) | val);
QID_V(tq->cntxt_id) | val);
} else {
u32 val = PIDX_T5(n);
u32 val = PIDX_T5_V(n);
/* T4 and later chips share the same PIDX field offset within
* the doorbell, but T5 and later shrank the field in order to
......@@ -992,7 +993,7 @@ static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
* large in the first place (14 bits) so we just use the T5
* and later limits and warn if a Queue ID is too large.
*/
WARN_ON(val & DBPRIO(1));
WARN_ON(val & DBPRIO_F);
/* If we're only writing a single Egress Unit and the BAR2
* Queue ID is 0, we can use the Write Combining Doorbell
......@@ -1023,7 +1024,7 @@ static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
count--;
}
} else
writel(val | QID(tq->bar2_qid),
writel(val | QID_V(tq->bar2_qid),
tq->bar2_addr + SGE_UDB_KDOORBELL);
/* This Write Memory Barrier will force the write to the User
......@@ -1875,13 +1876,13 @@ static int napi_rx_handler(struct napi_struct *napi, int budget)
if (unlikely(work_done == 0))
rspq->unhandled_irqs++;
val = CIDXINC(work_done) | SEINTARM(intr_params);
val = CIDXINC_V(work_done) | SEINTARM_V(intr_params);
if (is_t4(rspq->adapter->params.chip)) {
t4_write_reg(rspq->adapter,
T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
val | INGRESSQID((u32)rspq->cntxt_id));
val | INGRESSQID_V((u32)rspq->cntxt_id));
} else {
writel(val | INGRESSQID(rspq->bar2_qid),
writel(val | INGRESSQID_V(rspq->bar2_qid),
rspq->bar2_addr + SGE_UDB_GTS);
wmb();
}
......@@ -1975,12 +1976,12 @@ static unsigned int process_intrq(struct adapter *adapter)
rspq_next(intrq);
}
val = CIDXINC(work_done) | SEINTARM(intrq->intr_params);
val = CIDXINC_V(work_done) | SEINTARM_V(intrq->intr_params);
if (is_t4(adapter->params.chip))
t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
val | INGRESSQID(intrq->cntxt_id));
val | INGRESSQID_V(intrq->cntxt_id));
else {
writel(val | INGRESSQID(intrq->bar2_qid),
writel(val | INGRESSQID_V(intrq->bar2_qid),
intrq->bar2_addr + SGE_UDB_GTS);
wmb();
}
......@@ -2583,7 +2584,7 @@ int t4vf_sge_init(struct adapter *adapter)
fl0, fl1);
return -EINVAL;
}
if ((sge_params->sge_control & RXPKTCPLMODE_MASK) == 0) {
if ((sge_params->sge_control & RXPKTCPLMODE_F) == 0) {
dev_err(adapter->pdev_dev, "bad SGE CPL MODE\n");
return -EINVAL;
}
......@@ -2593,9 +2594,9 @@ int t4vf_sge_init(struct adapter *adapter)
*/
if (fl1)
s->fl_pg_order = ilog2(fl1) - PAGE_SHIFT;
s->stat_len = ((sge_params->sge_control & EGRSTATUSPAGESIZE_MASK)
s->stat_len = ((sge_params->sge_control & EGRSTATUSPAGESIZE_F)
? 128 : 64);
s->pktshift = PKTSHIFT_GET(sge_params->sge_control);
s->pktshift = PKTSHIFT_G(sge_params->sge_control);
/* T4 uses a single control field to specify both the PCIe Padding and
* Packing Boundary. T5 introduced the ability to specify these
......@@ -2607,8 +2608,8 @@ int t4vf_sge_init(struct adapter *adapter)
* end doing this because it would initialize the Padding Boundary and
* leave the Packing Boundary initialized to 0 (16 bytes).)
*/
ingpadboundary = 1 << (INGPADBOUNDARY_GET(sge_params->sge_control) +
X_INGPADBOUNDARY_SHIFT);
ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_params->sge_control) +
INGPADBOUNDARY_SHIFT_X);
if (is_t4(adapter->params.chip)) {
s->fl_align = ingpadboundary;
} else {
......@@ -2633,7 +2634,7 @@ int t4vf_sge_init(struct adapter *adapter)
* Congestion Threshold is in units of 2 Free List pointers.)
*/
s->fl_starve_thres
= EGRTHRESHOLD_GET(sge_params->sge_congestion_control)*2 + 1;
= EGRTHRESHOLD_G(sge_params->sge_congestion_control)*2 + 1;
/*
* Set up tasklet timers.
......
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_defs.h
View file @ a515abd7
......@@ -64,8 +64,8 @@
* Mailbox Data in the fixed CIM PF map and the programmable VF map must
* match. However, it's a useful convention ...
*/
#if T4VF_MBDATA_BASE_ADDR != CIM_PF_MAILBOX_DATA
#error T4VF_MBDATA_BASE_ADDR must match CIM_PF_MAILBOX_DATA!
#if T4VF_MBDATA_BASE_ADDR != CIM_PF_MAILBOX_DATA_A
#error T4VF_MBDATA_BASE_ADDR must match CIM_PF_MAILBOX_DATA_A!
#endif
/*
......
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
View file @ a515abd7
......@@ -39,6 +39,7 @@
#include "t4vf_defs.h"
#include "../cxgb4/t4_regs.h"
#include "../cxgb4/t4_values.h"
#include "../cxgb4/t4fw_api.h"
/*
......@@ -137,9 +138,9 @@ int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
* Loop trying to get ownership of the mailbox. Return an error
* if we can't gain ownership.
*/
v = MBOWNER_GET(t4_read_reg(adapter, mbox_ctl));
v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl));
for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
v = MBOWNER_GET(t4_read_reg(adapter, mbox_ctl));
v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl));
if (v != MBOX_OWNER_DRV)
return v == MBOX_OWNER_FW ? -EBUSY : -ETIMEDOUT;
......@@ -161,7 +162,7 @@ int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
t4_read_reg(adapter, mbox_data); /* flush write */
t4_write_reg(adapter, mbox_ctl,
MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
t4_read_reg(adapter, mbox_ctl); /* flush write */
/*
......@@ -183,14 +184,14 @@ int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
* If we're the owner, see if this is the reply we wanted.
*/
v = t4_read_reg(adapter, mbox_ctl);
if (MBOWNER_GET(v) == MBOX_OWNER_DRV) {
if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
/*
* If the Message Valid bit isn't on, revoke ownership
* of the mailbox and continue waiting for our reply.
*/
if ((v & MBMSGVALID) == 0) {
if ((v & MBMSGVALID_F) == 0) {
t4_write_reg(adapter, mbox_ctl,
MBOWNER(MBOX_OWNER_NONE));
MBOWNER_V(MBOX_OWNER_NONE));
continue;
}
......@@ -216,7 +217,7 @@ int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
& FW_CMD_REQUEST_F) != 0);
}
t4_write_reg(adapter, mbox_ctl,
MBOWNER(MBOX_OWNER_NONE));
MBOWNER_V(MBOX_OWNER_NONE));
return -FW_CMD_RETVAL_G(v);
}
}
......@@ -528,19 +529,19 @@ int t4vf_get_sge_params(struct adapter *adapter)
int v;
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_CONTROL));
FW_PARAMS_PARAM_XYZ_V(SGE_CONTROL_A));
params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_HOST_PAGE_SIZE));
FW_PARAMS_PARAM_XYZ_V(SGE_HOST_PAGE_SIZE_A));
params[2] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE0));
FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE0_A));
params[3] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE1));
FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE1_A));
params[4] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_0_AND_1));
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_0_AND_1_A));
params[5] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_2_AND_3));
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_2_AND_3_A));
params[6] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_4_AND_5));
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_4_AND_5_A));
v = t4vf_query_params(adapter, 7, params, vals);
if (v)
return v;
......@@ -576,9 +577,9 @@ int t4vf_get_sge_params(struct adapter *adapter)
}
params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_INGRESS_RX_THRESHOLD));
FW_PARAMS_PARAM_XYZ_V(SGE_INGRESS_RX_THRESHOLD_A));
params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_CONM_CTRL));
FW_PARAMS_PARAM_XYZ_V(SGE_CONM_CTRL_A));
v = t4vf_query_params(adapter, 2, params, vals);
if (v)
return v;
......@@ -615,8 +616,8 @@ int t4vf_get_sge_params(struct adapter *adapter)
* the driver can just use it.
*/
whoami = t4_read_reg(adapter,
T4VF_PL_BASE_ADDR + A_PL_VF_WHOAMI);
pf = SOURCEPF_GET(whoami);
T4VF_PL_BASE_ADDR + PL_VF_WHOAMI_A);
pf = SOURCEPF_G(whoami);
s_hps = (HOSTPAGESIZEPF0_S +
(HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * pf);
......@@ -628,10 +629,10 @@ int t4vf_get_sge_params(struct adapter *adapter)
(QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * pf);
sge_params->sge_vf_eq_qpp =
((sge_params->sge_egress_queues_per_page >> s_qpp)
& QUEUESPERPAGEPF0_MASK);
& QUEUESPERPAGEPF0_M);
sge_params->sge_vf_iq_qpp =
((sge_params->sge_ingress_queues_per_page >> s_qpp)
& QUEUESPERPAGEPF0_MASK);
& QUEUESPERPAGEPF0_M);
}
return 0;
......@@ -1590,7 +1591,7 @@ int t4vf_prep_adapter(struct adapter *adapter)
break;
case CHELSIO_T5:
chipid = G_REV(t4_read_reg(adapter, A_PL_VF_REV));
chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid);
break;
}
......
drivers/scsi/csiostor/csio_hw.c
View file @ a515abd7
......@@ -188,9 +188,9 @@ void
csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsigned int addr,
unsigned int mask, unsigned int val)
{
csio_wr_reg32(hw, addr, TP_PIO_ADDR);
val |= csio_rd_reg32(hw, TP_PIO_DATA) & ~mask;
csio_wr_reg32(hw, val, TP_PIO_DATA);
csio_wr_reg32(hw, addr, TP_PIO_ADDR_A);
val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask;
csio_wr_reg32(hw, val, TP_PIO_DATA_A);
}
void
......@@ -421,17 +421,15 @@ csio_hw_sf1_read(struct csio_hw *hw, uint32_t byte_cnt, int32_t cont,
if (!byte_cnt || byte_cnt > 4)
return -EINVAL;
if (csio_rd_reg32(hw, SF_OP) & SF_BUSY)
if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
return -EBUSY;
cont = cont ? SF_CONT : 0;
lock = lock ? SF_LOCK : 0;
csio_wr_reg32(hw, lock | cont | BYTECNT(byte_cnt - 1), SF_OP);
ret = csio_hw_wait_op_done_val(hw, SF_OP, SF_BUSY, 0, SF_ATTEMPTS,
10, NULL);
csio_wr_reg32(hw, SF_LOCK_V(lock) | SF_CONT_V(cont) |
BYTECNT_V(byte_cnt - 1), SF_OP_A);
ret = csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS,
10, NULL);
if (!ret)
*valp = csio_rd_reg32(hw, SF_DATA);
*valp = csio_rd_reg32(hw, SF_DATA_A);
return ret;
}
......@@ -453,16 +451,14 @@ csio_hw_sf1_write(struct csio_hw *hw, uint32_t byte_cnt, uint32_t cont,
{
if (!byte_cnt || byte_cnt > 4)
return -EINVAL;
if (csio_rd_reg32(hw, SF_OP) & SF_BUSY)
if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
return -EBUSY;
cont = cont ? SF_CONT : 0;
lock = lock ? SF_LOCK : 0;
csio_wr_reg32(hw, val, SF_DATA);
csio_wr_reg32(hw, cont | BYTECNT(byte_cnt - 1) | OP_WR | lock, SF_OP);
csio_wr_reg32(hw, val, SF_DATA_A);
csio_wr_reg32(hw, SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) |
OP_V(1) | SF_LOCK_V(lock), SF_OP_A);
return csio_hw_wait_op_done_val(hw, SF_OP, SF_BUSY, 0, SF_ATTEMPTS,
return csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS,
10, NULL);
}
......@@ -533,7 +529,7 @@ csio_hw_read_flash(struct csio_hw *hw, uint32_t addr, uint32_t nwords,
for ( ; nwords; nwords--, data++) {
ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data);
if (nwords == 1)
csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */
csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
if (ret)
return ret;
if (byte_oriented)
......@@ -586,7 +582,7 @@ csio_hw_write_flash(struct csio_hw *hw, uint32_t addr,
if (ret)
goto unlock;
csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */
csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
/* Read the page to verify the write succeeded */
ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
......@@ -603,7 +599,7 @@ csio_hw_write_flash(struct csio_hw *hw, uint32_t addr,
return 0;
unlock:
csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */
csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
return ret;
}
......@@ -641,7 +637,7 @@ csio_hw_flash_erase_sectors(struct csio_hw *hw, int32_t start, int32_t end)
if (ret)
csio_err(hw, "erase of flash sector %d failed, error %d\n",
start, ret);
csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */
csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
return 0;
}
......@@ -833,7 +829,7 @@ csio_hw_get_flash_params(struct csio_hw *hw)
ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID);
if (!ret)
ret = csio_hw_sf1_read(hw, 3, 0, 1, &info);
csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */
csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
if (ret != 0)
return ret;
......@@ -861,17 +857,17 @@ csio_hw_dev_ready(struct csio_hw *hw)
uint32_t reg;
int cnt = 6;
while (((reg = csio_rd_reg32(hw, PL_WHOAMI)) == 0xFFFFFFFF) &&
(--cnt != 0))
while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) &&
(--cnt != 0))
mdelay(100);
if ((cnt == 0) && (((int32_t)(SOURCEPF_GET(reg)) < 0) ||
(SOURCEPF_GET(reg) >= CSIO_MAX_PFN))) {
if ((cnt == 0) && (((int32_t)(SOURCEPF_G(reg)) < 0) ||
(SOURCEPF_G(reg) >= CSIO_MAX_PFN))) {
csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt);
return -EIO;
}
hw->pfn = SOURCEPF_GET(reg);
hw->pfn = SOURCEPF_G(reg);
return 0;
}
......@@ -959,8 +955,8 @@ csio_do_hello(struct csio_hw *hw, enum csio_dev_state *state)
* timeout ... and then retry if we haven't exhausted
* our retries ...
*/
pcie_fw = csio_rd_reg32(hw, PCIE_FW);
if (!(pcie_fw & (PCIE_FW_ERR|PCIE_FW_INIT))) {
pcie_fw = csio_rd_reg32(hw, PCIE_FW_A);
if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
if (waiting <= 0) {
if (retries-- > 0)
goto retry;
......@@ -976,10 +972,10 @@ csio_do_hello(struct csio_hw *hw, enum csio_dev_state *state)
* report errors preferentially.
*/
if (state) {
if (pcie_fw & PCIE_FW_ERR) {
if (pcie_fw & PCIE_FW_ERR_F) {
*state = CSIO_DEV_STATE_ERR;
rv = -ETIMEDOUT;
} else if (pcie_fw & PCIE_FW_INIT)
} else if (pcie_fw & PCIE_FW_INIT_F)
*state = CSIO_DEV_STATE_INIT;
}
......@@ -988,9 +984,9 @@ csio_do_hello(struct csio_hw *hw, enum csio_dev_state *state)
* there's not a valid Master PF, grab its identity
* for our caller.
*/
if (mpfn == PCIE_FW_MASTER_MASK &&
(pcie_fw & PCIE_FW_MASTER_VLD))
mpfn = PCIE_FW_MASTER_GET(pcie_fw);
if (mpfn == PCIE_FW_MASTER_M &&
(pcie_fw & PCIE_FW_MASTER_VLD_F))
mpfn = PCIE_FW_MASTER_G(pcie_fw);
break;
}
hw->flags &= ~CSIO_HWF_MASTER;
......@@ -1078,7 +1074,7 @@ csio_do_reset(struct csio_hw *hw, bool fw_rst)
if (!fw_rst) {
/* PIO reset */
csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST);
csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
mdelay(2000);
return 0;
}
......@@ -1090,7 +1086,7 @@ csio_do_reset(struct csio_hw *hw, bool fw_rst)
}
csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
PIORSTMODE | PIORST, 0, NULL);
PIORSTMODE_F | PIORST_F, 0, NULL);
if (csio_mb_issue(hw, mbp)) {
csio_err(hw, "Issue of RESET command failed.n");
......@@ -1156,7 +1152,7 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
* If a legitimate mailbox is provided, issue a RESET command
* with a HALT indication.
*/
if (mbox <= PCIE_FW_MASTER_MASK) {
if (mbox <= PCIE_FW_MASTER_M) {
struct csio_mb *mbp;
mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
......@@ -1166,7 +1162,7 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
}
csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
PIORSTMODE | PIORST, FW_RESET_CMD_HALT_F,
PIORSTMODE_F | PIORST_F, FW_RESET_CMD_HALT_F,
NULL);
if (csio_mb_issue(hw, mbp)) {
......@@ -1193,8 +1189,9 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
* rather than a RESET ... if it's new enough to understand that ...
*/
if (retval == 0 || force) {
csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, UPCRST);
csio_set_reg_field(hw, PCIE_FW, PCIE_FW_HALT, PCIE_FW_HALT);
csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F,
PCIE_FW_HALT_F);
}
/*
......@@ -1234,7 +1231,7 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
* doing it automatically, we need to clear the PCIE_FW.HALT
* bit.
*/
csio_set_reg_field(hw, PCIE_FW, PCIE_FW_HALT, 0);
csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, 0);
/*
* If we've been given a valid mailbox, first try to get the
......@@ -1243,21 +1240,21 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
* valid mailbox or the RESET command failed, fall back to
* hitting the chip with a hammer.
*/
if (mbox <= PCIE_FW_MASTER_MASK) {
csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0);
if (mbox <= PCIE_FW_MASTER_M) {
csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0);
msleep(100);
if (csio_do_reset(hw, true) == 0)
return 0;
}
csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST);
csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
msleep(2000);
} else {
int ms;
csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0);
csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0);
for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
if (!(csio_rd_reg32(hw, PCIE_FW) & PCIE_FW_HALT))
if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F))
return 0;
msleep(100);
ms += 100;
......@@ -2039,7 +2036,7 @@ csio_hw_configure(struct csio_hw *hw)
}
/* HW version */
hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV);
hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV_A);
/* Needed for FW download */
rv = csio_hw_get_flash_params(hw);
......@@ -2217,7 +2214,7 @@ csio_hw_initialize(struct csio_hw *hw)
return;
}
#define PF_INTR_MASK (PFSW | PFCIM)
#define PF_INTR_MASK (PFSW_F | PFCIM_F)
/*
* csio_hw_intr_enable - Enable HW interrupts
......@@ -2229,21 +2226,21 @@ static void
csio_hw_intr_enable(struct csio_hw *hw)
{
uint16_t vec = (uint16_t)csio_get_mb_intr_idx(csio_hw_to_mbm(hw));
uint32_t pf = SOURCEPF_GET(csio_rd_reg32(hw, PL_WHOAMI));
uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE);
uint32_t pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE_A);
/*
* Set aivec for MSI/MSIX. PCIE_PF_CFG.INTXType is set up
* by FW, so do nothing for INTX.
*/
if (hw->intr_mode == CSIO_IM_MSIX)
csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG),
AIVEC(AIVEC_MASK), vec);
csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
AIVEC_V(AIVEC_M), vec);
else if (hw->intr_mode == CSIO_IM_MSI)
csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG),
AIVEC(AIVEC_MASK), 0);
csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
AIVEC_V(AIVEC_M), 0);
csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE));
csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE_A));
/* Turn on MB interrupts - this will internally flush PIO as well */
csio_mb_intr_enable(hw);
......@@ -2253,19 +2250,19 @@ csio_hw_intr_enable(struct csio_hw *hw)
/*
* Disable the Serial FLASH interrupt, if enabled!
*/
pl &= (~SF);
csio_wr_reg32(hw, pl, PL_INT_ENABLE);
pl &= (~SF_F);
csio_wr_reg32(hw, pl, PL_INT_ENABLE_A);
csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE |
EGRESS_SIZE_ERR | ERR_INVALID_CIDX_INC |
ERR_CPL_OPCODE_0 | ERR_DROPPED_DB |
ERR_DATA_CPL_ON_HIGH_QID1 |
ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 |
ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |
ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |
ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR,
SGE_INT_ENABLE3);
csio_set_reg_field(hw, PL_INT_MAP0, 0, 1 << pf);
csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE_F |
EGRESS_SIZE_ERR_F | ERR_INVALID_CIDX_INC_F |
ERR_CPL_OPCODE_0_F | ERR_DROPPED_DB_F |
ERR_DATA_CPL_ON_HIGH_QID1_F |
ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F,
SGE_INT_ENABLE3_A);
csio_set_reg_field(hw, PL_INT_MAP0_A, 0, 1 << pf);
}
hw->flags |= CSIO_HWF_HW_INTR_ENABLED;
......@@ -2281,16 +2278,16 @@ csio_hw_intr_enable(struct csio_hw *hw)
void
csio_hw_intr_disable(struct csio_hw *hw)
{
uint32_t pf = SOURCEPF_GET(csio_rd_reg32(hw, PL_WHOAMI));
uint32_t pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED))
return;
hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED;
csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE));
csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE_A));
if (csio_is_hw_master(hw))
csio_set_reg_field(hw, PL_INT_MAP0, 1 << pf, 0);
csio_set_reg_field(hw, PL_INT_MAP0_A, 1 << pf, 0);
/* Turn off MB interrupts */
csio_mb_intr_disable(hw);
......@@ -2300,7 +2297,7 @@ csio_hw_intr_disable(struct csio_hw *hw)
void
csio_hw_fatal_err(struct csio_hw *hw)
{
csio_set_reg_field(hw, SGE_CONTROL, GLOBALENABLE, 0);
csio_set_reg_field(hw, SGE_CONTROL_A, GLOBALENABLE_F, 0);
csio_hw_intr_disable(hw);
/* Do not reset HW, we may need FW state for debugging */
......@@ -2594,7 +2591,7 @@ csio_hws_removing(struct csio_hw *hw, enum csio_hw_ev evt)
* register directly.
*/
csio_err(hw, "Resetting HW and waiting 2 seconds...\n");
csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST);
csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
mdelay(2000);
break;
......@@ -2682,11 +2679,11 @@ static void csio_tp_intr_handler(struct csio_hw *hw)
{
static struct intr_info tp_intr_info[] = {
{ 0x3fffffff, "TP parity error", -1, 1 },
{ FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
{ FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, TP_INT_CAUSE, tp_intr_info))
if (csio_handle_intr_status(hw, TP_INT_CAUSE_A, tp_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2698,52 +2695,52 @@ static void csio_sge_intr_handler(struct csio_hw *hw)
uint64_t v;
static struct intr_info sge_intr_info[] = {
{ ERR_CPL_EXCEED_IQE_SIZE,
{ ERR_CPL_EXCEED_IQE_SIZE_F,
"SGE received CPL exceeding IQE size", -1, 1 },
{ ERR_INVALID_CIDX_INC,
{ ERR_INVALID_CIDX_INC_F,
"SGE GTS CIDX increment too large", -1, 0 },
{ ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
{ ERR_DROPPED_DB, "SGE doorbell dropped", -1, 0 },
{ ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,
{ ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
{ ERR_DROPPED_DB_F, "SGE doorbell dropped", -1, 0 },
{ ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
"SGE IQID > 1023 received CPL for FL", -1, 0 },
{ ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
{ ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
0 },
{ ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
{ ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
0 },
{ ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
{ ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
0 },
{ ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
{ ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
0 },
{ ERR_ING_CTXT_PRIO,
{ ERR_ING_CTXT_PRIO_F,
"SGE too many priority ingress contexts", -1, 0 },
{ ERR_EGR_CTXT_PRIO,
{ ERR_EGR_CTXT_PRIO_F,
"SGE too many priority egress contexts", -1, 0 },
{ INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
{ EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
{ INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
{ EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
{ 0, NULL, 0, 0 }
};
v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1) |
((uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE2) << 32);
v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1_A) |
((uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE2_A) << 32);
if (v) {
csio_fatal(hw, "SGE parity error (%#llx)\n",
(unsigned long long)v);
csio_wr_reg32(hw, (uint32_t)(v & 0xFFFFFFFF),
SGE_INT_CAUSE1);
csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2);
SGE_INT_CAUSE1_A);
csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2_A);
}
v |= csio_handle_intr_status(hw, SGE_INT_CAUSE3, sge_intr_info);
v |= csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info);
if (csio_handle_intr_status(hw, SGE_INT_CAUSE3, sge_intr_info) ||
if (csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info) ||
v != 0)
csio_hw_fatal_err(hw);
}
#define CIM_OBQ_INTR (OBQULP0PARERR | OBQULP1PARERR | OBQULP2PARERR |\
OBQULP3PARERR | OBQSGEPARERR | OBQNCSIPARERR)
#define CIM_IBQ_INTR (IBQTP0PARERR | IBQTP1PARERR | IBQULPPARERR |\
IBQSGEHIPARERR | IBQSGELOPARERR | IBQNCSIPARERR)
#define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
#define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
/*
* CIM interrupt handler.
......@@ -2751,53 +2748,53 @@ static void csio_sge_intr_handler(struct csio_hw *hw)
static void csio_cim_intr_handler(struct csio_hw *hw)
{
static struct intr_info cim_intr_info[] = {
{ PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
{ PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
{ CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
{ CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
{ MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
{ MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
{ TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
{ TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
{ MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
{ MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
{ TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
{ TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info cim_upintr_info[] = {
{ RSVDSPACEINT, "CIM reserved space access", -1, 1 },
{ ILLTRANSINT, "CIM illegal transaction", -1, 1 },
{ ILLWRINT, "CIM illegal write", -1, 1 },
{ ILLRDINT, "CIM illegal read", -1, 1 },
{ ILLRDBEINT, "CIM illegal read BE", -1, 1 },
{ ILLWRBEINT, "CIM illegal write BE", -1, 1 },
{ SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
{ SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
{ BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
{ SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
{ SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
{ BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
{ SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
{ SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
{ BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
{ BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
{ SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
{ SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
{ BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
{ BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
{ SGLRDPLINT , "CIM single read from PL space", -1, 1 },
{ SGLWRPLINT , "CIM single write to PL space", -1, 1 },
{ BLKRDPLINT , "CIM block read from PL space", -1, 1 },
{ BLKWRPLINT , "CIM block write to PL space", -1, 1 },
{ REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
{ RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
{ TIMEOUTINT , "CIM PIF timeout", -1, 1 },
{ TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
{ RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
{ ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
{ ILLWRINT_F, "CIM illegal write", -1, 1 },
{ ILLRDINT_F, "CIM illegal read", -1, 1 },
{ ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
{ ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
{ SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
{ SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
{ BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
{ SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
{ SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
{ BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
{ SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
{ SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
{ BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
{ BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
{ SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
{ SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
{ BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
{ BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
{ SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
{ SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
{ BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
{ BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
{ REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
{ RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
{ TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
{ TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
{ 0, NULL, 0, 0 }
};
int fat;
fat = csio_handle_intr_status(hw, CIM_HOST_INT_CAUSE,
cim_intr_info) +
csio_handle_intr_status(hw, CIM_HOST_UPACC_INT_CAUSE,
cim_upintr_info);
fat = csio_handle_intr_status(hw, CIM_HOST_INT_CAUSE_A,
cim_intr_info) +
csio_handle_intr_status(hw, CIM_HOST_UPACC_INT_CAUSE_A,
cim_upintr_info);
if (fat)
csio_hw_fatal_err(hw);
}
......@@ -2813,7 +2810,7 @@ static void csio_ulprx_intr_handler(struct csio_hw *hw)
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE, ulprx_intr_info))
if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2823,19 +2820,19 @@ static void csio_ulprx_intr_handler(struct csio_hw *hw)
static void csio_ulptx_intr_handler(struct csio_hw *hw)
{
static struct intr_info ulptx_intr_info[] = {
{ PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
0 },
{ PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
0 },
{ PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
0 },
{ PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
{ PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
0 },
{ 0xfffffff, "ULPTX parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE, ulptx_intr_info))
if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2845,20 +2842,20 @@ static void csio_ulptx_intr_handler(struct csio_hw *hw)
static void csio_pmtx_intr_handler(struct csio_hw *hw)
{
static struct intr_info pmtx_intr_info[] = {
{ PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
{ ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
{ PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
{ PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
{ ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
{ 0xffffff0, "PMTX framing error", -1, 1 },
{ OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1,
{ OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", -1,
1 },
{ ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
{ C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
{ ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
{ PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE, pmtx_intr_info))
if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE_A, pmtx_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2868,17 +2865,17 @@ static void csio_pmtx_intr_handler(struct csio_hw *hw)
static void csio_pmrx_intr_handler(struct csio_hw *hw)
{
static struct intr_info pmrx_intr_info[] = {
{ ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
{ ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
{ 0x3ffff0, "PMRX framing error", -1, 1 },
{ OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1,
{ OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
{ DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", -1,
1 },
{ IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
{ E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
{ IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
{ PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE, pmrx_intr_info))
if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE_A, pmrx_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2888,16 +2885,16 @@ static void csio_pmrx_intr_handler(struct csio_hw *hw)
static void csio_cplsw_intr_handler(struct csio_hw *hw)
{
static struct intr_info cplsw_intr_info[] = {
{ CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
{ CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
{ TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
{ SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
{ CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
{ ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
{ CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
{ CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
{ TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
{ SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
{ CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
{ ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, CPL_INTR_CAUSE, cplsw_intr_info))
if (csio_handle_intr_status(hw, CPL_INTR_CAUSE_A, cplsw_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2907,15 +2904,15 @@ static void csio_cplsw_intr_handler(struct csio_hw *hw)
static void csio_le_intr_handler(struct csio_hw *hw)
{
static struct intr_info le_intr_info[] = {
{ LIPMISS, "LE LIP miss", -1, 0 },
{ LIP0, "LE 0 LIP error", -1, 0 },
{ PARITYERR, "LE parity error", -1, 1 },
{ UNKNOWNCMD, "LE unknown command", -1, 1 },
{ REQQPARERR, "LE request queue parity error", -1, 1 },
{ LIPMISS_F, "LE LIP miss", -1, 0 },
{ LIP0_F, "LE 0 LIP error", -1, 0 },
{ PARITYERR_F, "LE parity error", -1, 1 },
{ UNKNOWNCMD_F, "LE unknown command", -1, 1 },
{ REQQPARERR_F, "LE request queue parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE, le_intr_info))
if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE_A, le_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -2929,19 +2926,22 @@ static void csio_mps_intr_handler(struct csio_hw *hw)
{ 0, NULL, 0, 0 }
};
static struct intr_info mps_tx_intr_info[] = {
{ TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
{ NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
{ TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
{ TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 },
{ BUBBLE, "MPS Tx underflow", -1, 1 },
{ SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
{ FRMERR, "MPS Tx framing error", -1, 1 },
{ TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
{ NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
{ TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
-1, 1 },
{ TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
-1, 1 },
{ BUBBLE_F, "MPS Tx underflow", -1, 1 },
{ SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
{ FRMERR_F, "MPS Tx framing error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info mps_trc_intr_info[] = {
{ FILTMEM, "MPS TRC filter parity error", -1, 1 },
{ PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
{ MISCPERR, "MPS TRC misc parity error", -1, 1 },
{ FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
{ PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
-1, 1 },
{ MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info mps_stat_sram_intr_info[] = {
......@@ -2957,36 +2957,37 @@ static void csio_mps_intr_handler(struct csio_hw *hw)
{ 0, NULL, 0, 0 }
};
static struct intr_info mps_cls_intr_info[] = {
{ MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
{ MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
{ HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
{ MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
{ MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
{ HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
int fat;
fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE,
mps_rx_intr_info) +
csio_handle_intr_status(hw, MPS_TX_INT_CAUSE,
mps_tx_intr_info) +
csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE,
mps_trc_intr_info) +
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM,
mps_stat_sram_intr_info) +
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
mps_stat_tx_intr_info) +
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
mps_stat_rx_intr_info) +
csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE,
mps_cls_intr_info);
csio_wr_reg32(hw, 0, MPS_INT_CAUSE);
csio_rd_reg32(hw, MPS_INT_CAUSE); /* flush */
fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE_A,
mps_rx_intr_info) +
csio_handle_intr_status(hw, MPS_TX_INT_CAUSE_A,
mps_tx_intr_info) +
csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE_A,
mps_trc_intr_info) +
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
mps_stat_sram_intr_info) +
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
mps_stat_tx_intr_info) +
csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
mps_stat_rx_intr_info) +
csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE_A,
mps_cls_intr_info);
csio_wr_reg32(hw, 0, MPS_INT_CAUSE_A);
csio_rd_reg32(hw, MPS_INT_CAUSE_A); /* flush */
if (fat)
csio_hw_fatal_err(hw);
}
#define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE)
#define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
ECC_UE_INT_CAUSE_F)
/*
* EDC/MC interrupt handler.
......@@ -2998,28 +2999,28 @@ static void csio_mem_intr_handler(struct csio_hw *hw, int idx)
unsigned int addr, cnt_addr, v;
if (idx <= MEM_EDC1) {
addr = EDC_REG(EDC_INT_CAUSE, idx);
cnt_addr = EDC_REG(EDC_ECC_STATUS, idx);
addr = EDC_REG(EDC_INT_CAUSE_A, idx);
cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
} else {
addr = MC_INT_CAUSE;
cnt_addr = MC_ECC_STATUS;
addr = MC_INT_CAUSE_A;
cnt_addr = MC_ECC_STATUS_A;
}
v = csio_rd_reg32(hw, addr) & MEM_INT_MASK;
if (v & PERR_INT_CAUSE)
if (v & PERR_INT_CAUSE_F)
csio_fatal(hw, "%s FIFO parity error\n", name[idx]);
if (v & ECC_CE_INT_CAUSE) {
uint32_t cnt = ECC_CECNT_GET(csio_rd_reg32(hw, cnt_addr));
if (v & ECC_CE_INT_CAUSE_F) {
uint32_t cnt = ECC_CECNT_G(csio_rd_reg32(hw, cnt_addr));
csio_wr_reg32(hw, ECC_CECNT_MASK, cnt_addr);
csio_wr_reg32(hw, ECC_CECNT_V(ECC_CECNT_M), cnt_addr);
csio_warn(hw, "%u %s correctable ECC data error%s\n",
cnt, name[idx], cnt > 1 ? "s" : "");
}
if (v & ECC_UE_INT_CAUSE)
if (v & ECC_UE_INT_CAUSE_F)
csio_fatal(hw, "%s uncorrectable ECC data error\n", name[idx]);
csio_wr_reg32(hw, v, addr);
if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE))
if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
csio_hw_fatal_err(hw);
}
......@@ -3028,18 +3029,18 @@ static void csio_mem_intr_handler(struct csio_hw *hw, int idx)
*/
static void csio_ma_intr_handler(struct csio_hw *hw)
{
uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE);
uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE_A);
if (status & MEM_PERR_INT_CAUSE)
if (status & MEM_PERR_INT_CAUSE_F)
csio_fatal(hw, "MA parity error, parity status %#x\n",
csio_rd_reg32(hw, MA_PARITY_ERROR_STATUS));
if (status & MEM_WRAP_INT_CAUSE) {
v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS);
csio_rd_reg32(hw, MA_PARITY_ERROR_STATUS_A));
if (status & MEM_WRAP_INT_CAUSE_F) {
v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS_A);
csio_fatal(hw,
"MA address wrap-around error by client %u to address %#x\n",
MEM_WRAP_CLIENT_NUM_GET(v), MEM_WRAP_ADDRESS_GET(v) << 4);
MEM_WRAP_CLIENT_NUM_G(v), MEM_WRAP_ADDRESS_G(v) << 4);
}
csio_wr_reg32(hw, status, MA_INT_CAUSE);
csio_wr_reg32(hw, status, MA_INT_CAUSE_A);
csio_hw_fatal_err(hw);
}
......@@ -3049,13 +3050,13 @@ static void csio_ma_intr_handler(struct csio_hw *hw)
static void csio_smb_intr_handler(struct csio_hw *hw)
{
static struct intr_info smb_intr_info[] = {
{ MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
{ MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
{ SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
{ MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
{ MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
{ SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, SMB_INT_CAUSE, smb_intr_info))
if (csio_handle_intr_status(hw, SMB_INT_CAUSE_A, smb_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -3065,14 +3066,14 @@ static void csio_smb_intr_handler(struct csio_hw *hw)
static void csio_ncsi_intr_handler(struct csio_hw *hw)
{
static struct intr_info ncsi_intr_info[] = {
{ CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
{ MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
{ TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
{ RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
{ CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
{ MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
{ TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
{ RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, NCSI_INT_CAUSE, ncsi_intr_info))
if (csio_handle_intr_status(hw, NCSI_INT_CAUSE_A, ncsi_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -3083,13 +3084,13 @@ static void csio_xgmac_intr_handler(struct csio_hw *hw, int port)
{
uint32_t v = csio_rd_reg32(hw, CSIO_MAC_INT_CAUSE_REG(hw, port));
v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR;
v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
if (!v)
return;
if (v & TXFIFO_PRTY_ERR)
if (v & TXFIFO_PRTY_ERR_F)
csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port);
if (v & RXFIFO_PRTY_ERR)
if (v & RXFIFO_PRTY_ERR_F)
csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port);
csio_wr_reg32(hw, v, CSIO_MAC_INT_CAUSE_REG(hw, port));
csio_hw_fatal_err(hw);
......@@ -3101,12 +3102,12 @@ static void csio_xgmac_intr_handler(struct csio_hw *hw, int port)
static void csio_pl_intr_handler(struct csio_hw *hw)
{
static struct intr_info pl_intr_info[] = {
{ FATALPERR, "T4 fatal parity error", -1, 1 },
{ PERRVFID, "PL VFID_MAP parity error", -1, 1 },
{ FATALPERR_F, "T4 fatal parity error", -1, 1 },
{ PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE, pl_intr_info))
if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE_A, pl_intr_info))
csio_hw_fatal_err(hw);
}
......@@ -3121,7 +3122,7 @@ static void csio_pl_intr_handler(struct csio_hw *hw)
int
csio_hw_slow_intr_handler(struct csio_hw *hw)
{
uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE);
uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE_A);
if (!(cause & CSIO_GLBL_INTR_MASK)) {
CSIO_INC_STATS(hw, n_plint_unexp);
......@@ -3132,75 +3133,75 @@ csio_hw_slow_intr_handler(struct csio_hw *hw)
CSIO_INC_STATS(hw, n_plint_cnt);
if (cause & CIM)
if (cause & CIM_F)
csio_cim_intr_handler(hw);
if (cause & MPS)
if (cause & MPS_F)
csio_mps_intr_handler(hw);
if (cause & NCSI)
if (cause & NCSI_F)
csio_ncsi_intr_handler(hw);
if (cause & PL)
if (cause & PL_F)
csio_pl_intr_handler(hw);
if (cause & SMB)
if (cause & SMB_F)
csio_smb_intr_handler(hw);
if (cause & XGMAC0)
if (cause & XGMAC0_F)
csio_xgmac_intr_handler(hw, 0);
if (cause & XGMAC1)
if (cause & XGMAC1_F)
csio_xgmac_intr_handler(hw, 1);
if (cause & XGMAC_KR0)
if (cause & XGMAC_KR0_F)
csio_xgmac_intr_handler(hw, 2);
if (cause & XGMAC_KR1)
if (cause & XGMAC_KR1_F)
csio_xgmac_intr_handler(hw, 3);
if (cause & PCIE)
if (cause & PCIE_F)
hw->chip_ops->chip_pcie_intr_handler(hw);
if (cause & MC)
if (cause & MC_F)
csio_mem_intr_handler(hw, MEM_MC);
if (cause & EDC0)
if (cause & EDC0_F)
csio_mem_intr_handler(hw, MEM_EDC0);
if (cause & EDC1)
if (cause & EDC1_F)
csio_mem_intr_handler(hw, MEM_EDC1);
if (cause & LE)
if (cause & LE_F)
csio_le_intr_handler(hw);
if (cause & TP)
if (cause & TP_F)
csio_tp_intr_handler(hw);
if (cause & MA)
if (cause & MA_F)
csio_ma_intr_handler(hw);
if (cause & PM_TX)
if (cause & PM_TX_F)
csio_pmtx_intr_handler(hw);
if (cause & PM_RX)
if (cause & PM_RX_F)
csio_pmrx_intr_handler(hw);
if (cause & ULP_RX)
if (cause & ULP_RX_F)
csio_ulprx_intr_handler(hw);
if (cause & CPL_SWITCH)
if (cause & CPL_SWITCH_F)
csio_cplsw_intr_handler(hw);
if (cause & SGE)
if (cause & SGE_F)
csio_sge_intr_handler(hw);
if (cause & ULP_TX)
if (cause & ULP_TX_F)
csio_ulptx_intr_handler(hw);
/* Clear the interrupts just processed for which we are the master. */
csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE);
csio_rd_reg32(hw, PL_INT_CAUSE); /* flush */
csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE_A);
csio_rd_reg32(hw, PL_INT_CAUSE_A); /* flush */
return 1;
}
......
drivers/scsi/csiostor/csio_hw.h
View file @ a515abd7
......@@ -117,10 +117,10 @@ extern int csio_msi;
#define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
#define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
#define CSIO_GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
EDC1 | LE | TP | MA | PM_TX | PM_RX | \
ULP_RX | CPL_SWITCH | SGE | \
ULP_TX | SF)
#define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \
EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \
PM_TX_F | PM_RX_F | ULP_RX_F | \
CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
/*
* Hard parameters used to initialize the card in the absence of a
......
drivers/scsi/csiostor/csio_hw_chip.h
View file @ a515abd7
......@@ -66,19 +66,19 @@ static inline int csio_is_t5(uint16_t chip)
{ PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
#define CSIO_HW_PIDX(hw, index) \
(csio_is_t4(hw->chip_id) ? (PIDX(index)) : \
(PIDX_T5(index) | DBTYPE(1U)))
(csio_is_t4(hw->chip_id) ? (PIDX_V(index)) : \
(PIDX_T5_G(index) | DBTYPE_F))
#define CSIO_HW_LP_INT_THRESH(hw, val) \
(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH(val)) : \
(V_LP_INT_THRESH_T5(val)))
(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_V(val)) : \
(LP_INT_THRESH_T5_V(val)))
#define CSIO_HW_M_LP_INT_THRESH(hw) \
(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_MASK) : (M_LP_INT_THRESH_T5))
(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (LP_INT_THRESH_T5_M))
#define CSIO_MAC_INT_CAUSE_REG(hw, port) \
(csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \
(T5_PORT_REG(port, MAC_PORT_INT_CAUSE)))
(csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE_A)) : \
(T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)))
#define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0)
#define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0)
......
drivers/scsi/csiostor/csio_hw_t4.c
View file @ a515abd7
......@@ -96,11 +96,11 @@ csio_t4_set_mem_win(struct csio_hw *hw, uint32_t win)
* back MA register to ensure that changes propagate before we attempt
* to use the new values.)
*/
csio_wr_reg32(hw, mem_win_base | BIR(0) |
WINDOW(ilog2(MEMWIN_APERTURE) - 10),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
return 0;
}
......@@ -111,69 +111,69 @@ static void
csio_t4_pcie_intr_handler(struct csio_hw *hw)
{
static struct intr_info sysbus_intr_info[] = {
{ RNPP, "RXNP array parity error", -1, 1 },
{ RPCP, "RXPC array parity error", -1, 1 },
{ RCIP, "RXCIF array parity error", -1, 1 },
{ RCCP, "Rx completions control array parity error", -1, 1 },
{ RFTP, "RXFT array parity error", -1, 1 },
{ RNPP_F, "RXNP array parity error", -1, 1 },
{ RPCP_F, "RXPC array parity error", -1, 1 },
{ RCIP_F, "RXCIF array parity error", -1, 1 },
{ RCCP_F, "Rx completions control array parity error", -1, 1 },
{ RFTP_F, "RXFT array parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info pcie_port_intr_info[] = {
{ TPCP, "TXPC array parity error", -1, 1 },
{ TNPP, "TXNP array parity error", -1, 1 },
{ TFTP, "TXFT array parity error", -1, 1 },
{ TCAP, "TXCA array parity error", -1, 1 },
{ TCIP, "TXCIF array parity error", -1, 1 },
{ RCAP, "RXCA array parity error", -1, 1 },
{ OTDD, "outbound request TLP discarded", -1, 1 },
{ RDPE, "Rx data parity error", -1, 1 },
{ TDUE, "Tx uncorrectable data error", -1, 1 },
{ TPCP_F, "TXPC array parity error", -1, 1 },
{ TNPP_F, "TXNP array parity error", -1, 1 },
{ TFTP_F, "TXFT array parity error", -1, 1 },
{ TCAP_F, "TXCA array parity error", -1, 1 },
{ TCIP_F, "TXCIF array parity error", -1, 1 },
{ RCAP_F, "RXCA array parity error", -1, 1 },
{ OTDD_F, "outbound request TLP discarded", -1, 1 },
{ RDPE_F, "Rx data parity error", -1, 1 },
{ TDUE_F, "Tx uncorrectable data error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info pcie_intr_info[] = {
{ MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
{ MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
{ MSIDATAPERR, "MSI data parity error", -1, 1 },
{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
{ PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
{ PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
{ CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
{ DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
{ HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR, "PCI FID parity error", -1, 1 },
{ INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
{ MATAGPERR, "PCI MA tag parity error", -1, 1 },
{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
{ RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
{ RXWRPERR, "PCI Rx write parity error", -1, 1 },
{ RPLPERR, "PCI replay buffer parity error", -1, 1 },
{ PCIESINT, "PCI core secondary fault", -1, 1 },
{ PCIEPINT, "PCI core primary fault", -1, 1 },
{ UNXSPLCPLERR, "PCI unexpected split completion error", -1,
{ MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
{ MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
{ MSIDATAPERR_F, "MSI data parity error", -1, 1 },
{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
{ PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
{ PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
{ CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
{ DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
{ HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR_F, "PCI FID parity error", -1, 1 },
{ INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
{ MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
{ RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
{ RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
{ RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
{ PCIESINT_F, "PCI core secondary fault", -1, 1 },
{ PCIEPINT_F, "PCI core primary fault", -1, 1 },
{ UNXSPLCPLERR_F, "PCI unexpected split completion error", -1,
0 },
{ 0, NULL, 0, 0 }
};
int fat;
fat = csio_handle_intr_status(hw,
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
sysbus_intr_info) +
csio_handle_intr_status(hw,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
pcie_port_intr_info) +
csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info);
csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
if (fat)
csio_hw_fatal_err(hw);
}
......@@ -209,19 +209,19 @@ csio_t4_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
{
int i;
if (csio_rd_reg32(hw, MC_BIST_CMD) & START_BIST)
if (csio_rd_reg32(hw, MC_BIST_CMD_A) & START_BIST_F)
return -EBUSY;
csio_wr_reg32(hw, addr & ~0x3fU, MC_BIST_CMD_ADDR);
csio_wr_reg32(hw, 64, MC_BIST_CMD_LEN);
csio_wr_reg32(hw, 0xc, MC_BIST_DATA_PATTERN);
csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1),
MC_BIST_CMD);
i = csio_hw_wait_op_done_val(hw, MC_BIST_CMD, START_BIST,
csio_wr_reg32(hw, addr & ~0x3fU, MC_BIST_CMD_ADDR_A);
csio_wr_reg32(hw, 64, MC_BIST_CMD_LEN_A);
csio_wr_reg32(hw, 0xc, MC_BIST_DATA_PATTERN_A);
csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1),
MC_BIST_CMD_A);
i = csio_hw_wait_op_done_val(hw, MC_BIST_CMD_A, START_BIST_F,
0, 10, 1, NULL);
if (i)
return i;
#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i)
#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA_A, i)
for (i = 15; i >= 0; i--)
*data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
......@@ -250,19 +250,19 @@ csio_t4_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
int i;
idx *= EDC_STRIDE;
if (csio_rd_reg32(hw, EDC_BIST_CMD + idx) & START_BIST)
if (csio_rd_reg32(hw, EDC_BIST_CMD_A + idx) & START_BIST_F)
return -EBUSY;
csio_wr_reg32(hw, addr & ~0x3fU, EDC_BIST_CMD_ADDR + idx);
csio_wr_reg32(hw, 64, EDC_BIST_CMD_LEN + idx);
csio_wr_reg32(hw, 0xc, EDC_BIST_DATA_PATTERN + idx);
csio_wr_reg32(hw, BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST,
EDC_BIST_CMD + idx);
i = csio_hw_wait_op_done_val(hw, EDC_BIST_CMD + idx, START_BIST,
csio_wr_reg32(hw, addr & ~0x3fU, EDC_BIST_CMD_ADDR_A + idx);
csio_wr_reg32(hw, 64, EDC_BIST_CMD_LEN_A + idx);
csio_wr_reg32(hw, 0xc, EDC_BIST_DATA_PATTERN_A + idx);
csio_wr_reg32(hw, BIST_OPCODE_V(1) | BIST_CMD_GAP_V(1) | START_BIST_F,
EDC_BIST_CMD_A + idx);
i = csio_hw_wait_op_done_val(hw, EDC_BIST_CMD_A + idx, START_BIST_F,
0, 10, 1, NULL);
if (i)
return i;
#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx)
#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA_A, i) + idx)
for (i = 15; i >= 0; i--)
*data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
......@@ -329,9 +329,9 @@ csio_t4_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
* the address is relative to BAR0.
*/
mem_reg = csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
mem_aperture = 1 << (WINDOW(mem_reg) + 10);
mem_base = GET_PCIEOFST(mem_reg) << 10;
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
mem_base = PCIEOFST_G(mem_reg) << 10;
bar0 = csio_t4_read_pcie_cfg4(hw, PCI_BASE_ADDRESS_0);
bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
......@@ -356,9 +356,9 @@ csio_t4_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
* before we attempt to use the new value.
*/
csio_wr_reg32(hw, pos,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
while (offset < mem_aperture && len > 0) {
if (dir)
......
drivers/scsi/csiostor/csio_hw_t5.c
View file @ a515abd7
......@@ -56,11 +56,11 @@ csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win)
* back MA register to ensure that changes propagate before we attempt
* to use the new values.)
*/
csio_wr_reg32(hw, mem_win_base | BIR(0) |
WINDOW(ilog2(MEMWIN_APERTURE) - 10),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
return 0;
}
......@@ -72,74 +72,74 @@ static void
csio_t5_pcie_intr_handler(struct csio_hw *hw)
{
static struct intr_info sysbus_intr_info[] = {
{ RNPP, "RXNP array parity error", -1, 1 },
{ RPCP, "RXPC array parity error", -1, 1 },
{ RCIP, "RXCIF array parity error", -1, 1 },
{ RCCP, "Rx completions control array parity error", -1, 1 },
{ RFTP, "RXFT array parity error", -1, 1 },
{ RNPP_F, "RXNP array parity error", -1, 1 },
{ RPCP_F, "RXPC array parity error", -1, 1 },
{ RCIP_F, "RXCIF array parity error", -1, 1 },
{ RCCP_F, "Rx completions control array parity error", -1, 1 },
{ RFTP_F, "RXFT array parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info pcie_port_intr_info[] = {
{ TPCP, "TXPC array parity error", -1, 1 },
{ TNPP, "TXNP array parity error", -1, 1 },
{ TFTP, "TXFT array parity error", -1, 1 },
{ TCAP, "TXCA array parity error", -1, 1 },
{ TCIP, "TXCIF array parity error", -1, 1 },
{ RCAP, "RXCA array parity error", -1, 1 },
{ OTDD, "outbound request TLP discarded", -1, 1 },
{ RDPE, "Rx data parity error", -1, 1 },
{ TDUE, "Tx uncorrectable data error", -1, 1 },
{ TPCP_F, "TXPC array parity error", -1, 1 },
{ TNPP_F, "TXNP array parity error", -1, 1 },
{ TFTP_F, "TXFT array parity error", -1, 1 },
{ TCAP_F, "TXCA array parity error", -1, 1 },
{ TCIP_F, "TXCIF array parity error", -1, 1 },
{ RCAP_F, "RXCA array parity error", -1, 1 },
{ OTDD_F, "outbound request TLP discarded", -1, 1 },
{ RDPE_F, "Rx data parity error", -1, 1 },
{ TDUE_F, "Tx uncorrectable data error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info pcie_intr_info[] = {
{ MSTGRPPERR, "Master Response Read Queue parity error",
{ MSTGRPPERR_F, "Master Response Read Queue parity error",
-1, 1 },
{ MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
{ MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
{ PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
{ MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
{ MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
{ PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
-1, 1 },
{ PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
{ PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
-1, 1 },
{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
{ MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
{ DREQWRPERR, "PCI DMA channel write request parity error",
{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
{ MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
{ DREQWRPERR_F, "PCI DMA channel write request parity error",
-1, 1 },
{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
{ HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR, "PCI FID parity error", -1, 1 },
{ VFIDPERR, "PCI INTx clear parity error", -1, 1 },
{ MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
{ IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
{ HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR_F, "PCI FID parity error", -1, 1 },
{ VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
{ MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
{ IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
-1, 1 },
{ IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
{ IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
-1, 1 },
{ RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
{ IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
{ TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
{ READRSPERR, "Outbound read error", -1, 0 },
{ RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
{ IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
{ TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
{ READRSPERR_F, "Outbound read error", -1, 0 },
{ 0, NULL, 0, 0 }
};
int fat;
fat = csio_handle_intr_status(hw,
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
sysbus_intr_info) +
csio_handle_intr_status(hw,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
pcie_port_intr_info) +
csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info);
csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
if (fat)
csio_hw_fatal_err(hw);
}
......@@ -177,25 +177,25 @@ csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
uint32_t mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD, idx);
mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR, idx);
mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN, idx);
mc_bist_status_rdata_reg = MC_REG(MC_P_BIST_STATUS_RDATA, idx);
mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN, idx);
mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD_A, idx);
mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR_A, idx);
mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN_A, idx);
mc_bist_status_rdata_reg = MC_REG(MC_P_BIST_STATUS_RDATA_A, idx);
mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx);
if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST)
if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F)
return -EBUSY;
csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg);
csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg);
csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg);
csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1),
csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1),
mc_bist_cmd_reg);
i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST,
i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST_F,
0, 10, 1, NULL);
if (i)
return i;
#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i)
#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA_A, i)
for (i = 15; i >= 0; i--)
*data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
......@@ -231,27 +231,27 @@ csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD, idx);
edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx);
edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx);
edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx);
edc_bist_status_rdata_reg = EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx);
edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD_A, idx);
edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx);
edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx);
edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx);
edc_bist_status_rdata_reg = EDC_REG_T5(EDC_H_BIST_STATUS_RDATA_A, idx);
#undef EDC_REG_T5
#undef EDC_STRIDE_T5
if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST)
if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F)
return -EBUSY;
csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg);
csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg);
csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern);
csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1),
csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1),
edc_bist_cmd_reg);
i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST,
i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST_F,
0, 10, 1, NULL);
if (i)
return i;
#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx)
#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA_A, i) + idx)
for (i = 15; i >= 0; i--)
*data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
......@@ -320,13 +320,13 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
* the address is relative to BAR0.
*/
mem_reg = csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
mem_aperture = 1 << (WINDOW(mem_reg) + 10);
mem_base = GET_PCIEOFST(mem_reg) << 10;
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
mem_base = PCIEOFST_G(mem_reg) << 10;
start = addr & ~(mem_aperture-1);
offset = addr - start;
win_pf = V_PFNUM(hw->pfn);
win_pf = PFNUM_V(hw->pfn);
csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
mem_reg, mem_aperture);
......@@ -344,9 +344,9 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
* before we attempt to use the new value.
*/
csio_wr_reg32(hw, pos | win_pf,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
while (offset < mem_aperture && len > 0) {
if (dir)
......
drivers/scsi/csiostor/csio_isr.c
View file @ a515abd7
......@@ -317,7 +317,7 @@ csio_fcoe_isr(int irq, void *dev_id)
/* Disable the interrupt for this PCI function. */
if (hw->intr_mode == CSIO_IM_INTX)
csio_wr_reg32(hw, 0, MYPF_REG(PCIE_PF_CLI));
csio_wr_reg32(hw, 0, MYPF_REG(PCIE_PF_CLI_A));
/*
* The read in the following function will flush the
......
drivers/scsi/csiostor/csio_mb.c
View file @ a515abd7
......@@ -1104,8 +1104,8 @@ csio_mb_process_portparams_rsp(struct csio_hw *hw,
void
csio_mb_intr_enable(struct csio_hw *hw)
{
csio_wr_reg32(hw, MBMSGRDYINTEN(1), MYPF_REG(CIM_PF_HOST_INT_ENABLE));
csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE));
csio_wr_reg32(hw, MBMSGRDYINTEN_F, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
}
/*
......@@ -1117,8 +1117,9 @@ csio_mb_intr_enable(struct csio_hw *hw)
void
csio_mb_intr_disable(struct csio_hw *hw)
{
csio_wr_reg32(hw, MBMSGRDYINTEN(0), MYPF_REG(CIM_PF_HOST_INT_ENABLE));
csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE));
csio_wr_reg32(hw, MBMSGRDYINTEN_V(0),
MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
}
static void
......@@ -1153,8 +1154,8 @@ csio_mb_debug_cmd_handler(struct csio_hw *hw)
{
int i;
__be64 cmd[CSIO_MB_MAX_REGS];
uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL);
uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA);
uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A);
uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A);
int size = sizeof(struct fw_debug_cmd);
/* Copy mailbox data */
......@@ -1164,8 +1165,8 @@ csio_mb_debug_cmd_handler(struct csio_hw *hw)
csio_mb_dump_fw_dbg(hw, cmd);
/* Notify FW of mailbox by setting owner as UP */
csio_wr_reg32(hw, MBMSGVALID | MBINTREQ | MBOWNER(CSIO_MBOWNER_FW),
ctl_reg);
csio_wr_reg32(hw, MBMSGVALID_F | MBINTREQ_F |
MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg);
csio_rd_reg32(hw, ctl_reg);
wmb();
......@@ -1187,8 +1188,8 @@ csio_mb_issue(struct csio_hw *hw, struct csio_mb *mbp)
__be64 *cmd = mbp->mb;
__be64 hdr;
struct csio_mbm *mbm = &hw->mbm;
uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL);
uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA);
uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A);
uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A);
int size = mbp->mb_size;
int rv = -EINVAL;
struct fw_cmd_hdr *fw_hdr;
......@@ -1224,12 +1225,12 @@ csio_mb_issue(struct csio_hw *hw, struct csio_mb *mbp)
}
/* Now get ownership of mailbox */
owner = MBOWNER_GET(csio_rd_reg32(hw, ctl_reg));
owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg));
if (!csio_mb_is_host_owner(owner)) {
for (i = 0; (owner == CSIO_MBOWNER_NONE) && (i < 3); i++)
owner = MBOWNER_GET(csio_rd_reg32(hw, ctl_reg));
owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg));
/*
* Mailbox unavailable. In immediate mode, fail the command.
* In other modes, enqueue the request.
......@@ -1271,10 +1272,10 @@ csio_mb_issue(struct csio_hw *hw, struct csio_mb *mbp)
if (mbp->mb_cbfn != NULL) {
mbm->mcurrent = mbp;
mod_timer(&mbm->timer, jiffies + msecs_to_jiffies(mbp->tmo));
csio_wr_reg32(hw, MBMSGVALID | MBINTREQ |
MBOWNER(CSIO_MBOWNER_FW), ctl_reg);
csio_wr_reg32(hw, MBMSGVALID_F | MBINTREQ_F |
MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg);
} else
csio_wr_reg32(hw, MBMSGVALID | MBOWNER(CSIO_MBOWNER_FW),
csio_wr_reg32(hw, MBMSGVALID_F | MBOWNER_V(CSIO_MBOWNER_FW),
ctl_reg);
/* Flush posted writes */
......@@ -1294,9 +1295,9 @@ csio_mb_issue(struct csio_hw *hw, struct csio_mb *mbp)
/* Check for response */
ctl = csio_rd_reg32(hw, ctl_reg);
if (csio_mb_is_host_owner(MBOWNER_GET(ctl))) {
if (csio_mb_is_host_owner(MBOWNER_G(ctl))) {
if (!(ctl & MBMSGVALID)) {
if (!(ctl & MBMSGVALID_F)) {
csio_wr_reg32(hw, 0, ctl_reg);
continue;
}
......@@ -1457,16 +1458,16 @@ csio_mb_isr_handler(struct csio_hw *hw)
__be64 *cmd;
uint32_t ctl, cim_cause, pl_cause;
int i;
uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL);
uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA);
uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A);
uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A);
int size;
__be64 hdr;
struct fw_cmd_hdr *fw_hdr;
pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE));
cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE));
pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE_A));
cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A));
if (!(pl_cause & PFCIM) || !(cim_cause & MBMSGRDYINT)) {
if (!(pl_cause & PFCIM_F) || !(cim_cause & MBMSGRDYINT_F)) {
CSIO_INC_STATS(hw, n_mbint_unexp);
return -EINVAL;
}
......@@ -1477,16 +1478,16 @@ csio_mb_isr_handler(struct csio_hw *hw)
* the upper level cause register. In other words, CIM-cause
* first followed by PL-Cause next.
*/
csio_wr_reg32(hw, MBMSGRDYINT, MYPF_REG(CIM_PF_HOST_INT_CAUSE));
csio_wr_reg32(hw, PFCIM, MYPF_REG(PL_PF_INT_CAUSE));
csio_wr_reg32(hw, MBMSGRDYINT_F, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A));
csio_wr_reg32(hw, PFCIM_F, MYPF_REG(PL_PF_INT_CAUSE_A));
ctl = csio_rd_reg32(hw, ctl_reg);
if (csio_mb_is_host_owner(MBOWNER_GET(ctl))) {
if (csio_mb_is_host_owner(MBOWNER_G(ctl))) {
CSIO_DUMP_MB(hw, hw->pfn, data_reg);
if (!(ctl & MBMSGVALID)) {
if (!(ctl & MBMSGVALID_F)) {
csio_warn(hw,
"Stray mailbox interrupt recvd,"
" mailbox data not valid\n");
......
drivers/scsi/csiostor/csio_wr.c
View file @ a515abd7
......@@ -51,12 +51,12 @@ int csio_intr_coalesce_time = 10; /* value:SGE_TIMER_VALUE_1 */
static int csio_sge_timer_reg = 1;
#define CSIO_SET_FLBUF_SIZE(_hw, _reg, _val) \
csio_wr_reg32((_hw), (_val), SGE_FL_BUFFER_SIZE##_reg)
csio_wr_reg32((_hw), (_val), SGE_FL_BUFFER_SIZE##_reg##_A)
static void
csio_get_flbuf_size(struct csio_hw *hw, struct csio_sge *sge, uint32_t reg)
{
sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0 +
sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0_A +
reg * sizeof(uint32_t));
}
......@@ -71,7 +71,7 @@ csio_wr_fl_bufsz(struct csio_sge *sge, struct csio_dma_buf *buf)
static inline uint32_t
csio_wr_qstat_pgsz(struct csio_hw *hw)
{
return (hw->wrm.sge.sge_control & EGRSTATUSPAGESIZE(1)) ? 128 : 64;
return (hw->wrm.sge.sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64;
}
/* Ring freelist doorbell */
......@@ -84,9 +84,9 @@ csio_wr_ring_fldb(struct csio_hw *hw, struct csio_q *flq)
* 8 freelist buffer pointers (since each pointer is 8 bytes).
*/
if (flq->inc_idx >= 8) {
csio_wr_reg32(hw, DBPRIO(1) | QID(flq->un.fl.flid) |
csio_wr_reg32(hw, DBPRIO_F | QID_V(flq->un.fl.flid) |
CSIO_HW_PIDX(hw, flq->inc_idx / 8),
MYPF_REG(SGE_PF_KDOORBELL));
MYPF_REG(SGE_PF_KDOORBELL_A));
flq->inc_idx &= 7;
}
}
......@@ -95,10 +95,10 @@ csio_wr_ring_fldb(struct csio_hw *hw, struct csio_q *flq)
static void
csio_wr_sge_intr_enable(struct csio_hw *hw, uint16_t iqid)
{
csio_wr_reg32(hw, CIDXINC(0) |
INGRESSQID(iqid) |
TIMERREG(X_TIMERREG_RESTART_COUNTER),
MYPF_REG(SGE_PF_GTS));
csio_wr_reg32(hw, CIDXINC_V(0) |
INGRESSQID_V(iqid) |
TIMERREG_V(X_TIMERREG_RESTART_COUNTER),
MYPF_REG(SGE_PF_GTS_A));
}
/*
......@@ -982,9 +982,9 @@ csio_wr_issue(struct csio_hw *hw, int qidx, bool prio)
wmb();
/* Ring SGE Doorbell writing q->pidx into it */
csio_wr_reg32(hw, DBPRIO(prio) | QID(q->un.eq.physeqid) |
csio_wr_reg32(hw, DBPRIO_V(prio) | QID_V(q->un.eq.physeqid) |
CSIO_HW_PIDX(hw, q->inc_idx),
MYPF_REG(SGE_PF_KDOORBELL));
MYPF_REG(SGE_PF_KDOORBELL_A));
q->inc_idx = 0;
return 0;
......@@ -1242,10 +1242,10 @@ csio_wr_process_iq(struct csio_hw *hw, struct csio_q *q,
restart:
/* Now inform SGE about our incremental index value */
csio_wr_reg32(hw, CIDXINC(q->inc_idx) |
INGRESSQID(q->un.iq.physiqid) |
TIMERREG(csio_sge_timer_reg),
MYPF_REG(SGE_PF_GTS));
csio_wr_reg32(hw, CIDXINC_V(q->inc_idx) |
INGRESSQID_V(q->un.iq.physiqid) |
TIMERREG_V(csio_sge_timer_reg),
MYPF_REG(SGE_PF_GTS_A));
q->stats.n_tot_rsps += q->inc_idx;
q->inc_idx = 0;
......@@ -1310,22 +1310,23 @@ csio_wr_fixup_host_params(struct csio_hw *hw)
uint32_t ingpad = 0;
uint32_t stat_len = clsz > 64 ? 128 : 64;
csio_wr_reg32(hw, HOSTPAGESIZEPF0(s_hps) | HOSTPAGESIZEPF1(s_hps) |
HOSTPAGESIZEPF2(s_hps) | HOSTPAGESIZEPF3(s_hps) |
HOSTPAGESIZEPF4(s_hps) | HOSTPAGESIZEPF5(s_hps) |
HOSTPAGESIZEPF6(s_hps) | HOSTPAGESIZEPF7(s_hps),
SGE_HOST_PAGE_SIZE);
csio_wr_reg32(hw, HOSTPAGESIZEPF0_V(s_hps) | HOSTPAGESIZEPF1_V(s_hps) |
HOSTPAGESIZEPF2_V(s_hps) | HOSTPAGESIZEPF3_V(s_hps) |
HOSTPAGESIZEPF4_V(s_hps) | HOSTPAGESIZEPF5_V(s_hps) |
HOSTPAGESIZEPF6_V(s_hps) | HOSTPAGESIZEPF7_V(s_hps),
SGE_HOST_PAGE_SIZE_A);
sge->csio_fl_align = clsz < 32 ? 32 : clsz;
ingpad = ilog2(sge->csio_fl_align) - 5;
csio_set_reg_field(hw, SGE_CONTROL, INGPADBOUNDARY_MASK |
EGRSTATUSPAGESIZE(1),
INGPADBOUNDARY(ingpad) |
EGRSTATUSPAGESIZE(stat_len != 64));
csio_set_reg_field(hw, SGE_CONTROL_A,
INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
EGRSTATUSPAGESIZE_F,
INGPADBOUNDARY_V(ingpad) |
EGRSTATUSPAGESIZE_V(stat_len != 64));
/* FL BUFFER SIZE#0 is Page size i,e already aligned to cache line */
csio_wr_reg32(hw, PAGE_SIZE, SGE_FL_BUFFER_SIZE0);
csio_wr_reg32(hw, PAGE_SIZE, SGE_FL_BUFFER_SIZE0_A);
/*
* If using hard params, the following will get set correctly
......@@ -1333,23 +1334,24 @@ csio_wr_fixup_host_params(struct csio_hw *hw)
*/
if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS) {
csio_wr_reg32(hw,
(csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2) +
(csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2_A) +
sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
SGE_FL_BUFFER_SIZE2);
SGE_FL_BUFFER_SIZE2_A);
csio_wr_reg32(hw,
(csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3) +
(csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3_A) +
sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
SGE_FL_BUFFER_SIZE3);
SGE_FL_BUFFER_SIZE3_A);
}
csio_wr_reg32(hw, HPZ0(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ);
csio_wr_reg32(hw, HPZ0_V(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ_A);
/* default value of rx_dma_offset of the NIC driver */
csio_set_reg_field(hw, SGE_CONTROL, PKTSHIFT_MASK,
PKTSHIFT(CSIO_SGE_RX_DMA_OFFSET));
csio_set_reg_field(hw, SGE_CONTROL_A,
PKTSHIFT_V(PKTSHIFT_M),
PKTSHIFT_V(CSIO_SGE_RX_DMA_OFFSET));
csio_hw_tp_wr_bits_indirect(hw, TP_INGRESS_CONFIG,
CSUM_HAS_PSEUDO_HDR, 0);
csio_hw_tp_wr_bits_indirect(hw, TP_INGRESS_CONFIG_A,
CSUM_HAS_PSEUDO_HDR_F, 0);
}
static void
......@@ -1384,9 +1386,9 @@ csio_wr_get_sge(struct csio_hw *hw)
u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5;
u32 ingress_rx_threshold;
sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL);
sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A);
ingpad = INGPADBOUNDARY_GET(sge->sge_control);
ingpad = INGPADBOUNDARY_G(sge->sge_control);
switch (ingpad) {
case X_INGPCIEBOUNDARY_32B:
......@@ -1410,28 +1412,28 @@ csio_wr_get_sge(struct csio_hw *hw)
for (i = 0; i < CSIO_SGE_FL_SIZE_REGS; i++)
csio_get_flbuf_size(hw, sge, i);
timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1);
timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3);
timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5);
timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1_A);
timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3_A);
timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5_A);
sge->timer_val[0] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE0_GET(timer_value_0_and_1));
TIMERVALUE0_G(timer_value_0_and_1));
sge->timer_val[1] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE1_GET(timer_value_0_and_1));
TIMERVALUE1_G(timer_value_0_and_1));
sge->timer_val[2] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE2_GET(timer_value_2_and_3));
TIMERVALUE2_G(timer_value_2_and_3));
sge->timer_val[3] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE3_GET(timer_value_2_and_3));
TIMERVALUE3_G(timer_value_2_and_3));
sge->timer_val[4] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE4_GET(timer_value_4_and_5));
TIMERVALUE4_G(timer_value_4_and_5));
sge->timer_val[5] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE5_GET(timer_value_4_and_5));
TIMERVALUE5_G(timer_value_4_and_5));
ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD);
sge->counter_val[0] = THRESHOLD_0_GET(ingress_rx_threshold);
sge->counter_val[1] = THRESHOLD_1_GET(ingress_rx_threshold);
sge->counter_val[2] = THRESHOLD_2_GET(ingress_rx_threshold);
sge->counter_val[3] = THRESHOLD_3_GET(ingress_rx_threshold);
ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD_A);
sge->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
sge->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold);
sge->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold);
sge->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold);
csio_init_intr_coalesce_parms(hw);
}
......@@ -1454,9 +1456,9 @@ csio_wr_set_sge(struct csio_hw *hw)
* Set up our basic SGE mode to deliver CPL messages to our Ingress
* Queue and Packet Date to the Free List.
*/
csio_set_reg_field(hw, SGE_CONTROL, RXPKTCPLMODE(1), RXPKTCPLMODE(1));
csio_set_reg_field(hw, SGE_CONTROL_A, RXPKTCPLMODE_F, RXPKTCPLMODE_F);
sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL);
sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A);
/* sge->csio_fl_align is set up by csio_wr_fixup_host_params(). */
......@@ -1464,22 +1466,24 @@ csio_wr_set_sge(struct csio_hw *hw)
* Set up to drop DOORBELL writes when the DOORBELL FIFO overflows
* and generate an interrupt when this occurs so we can recover.
*/
csio_set_reg_field(hw, SGE_DBFIFO_STATUS,
HP_INT_THRESH(HP_INT_THRESH_MASK) |
CSIO_HW_LP_INT_THRESH(hw, CSIO_HW_M_LP_INT_THRESH(hw)),
HP_INT_THRESH(CSIO_SGE_DBFIFO_INT_THRESH) |
CSIO_HW_LP_INT_THRESH(hw, CSIO_SGE_DBFIFO_INT_THRESH));
csio_set_reg_field(hw, SGE_DBFIFO_STATUS_A,
HP_INT_THRESH_V(HP_INT_THRESH_M) |
CSIO_HW_LP_INT_THRESH(hw,
CSIO_HW_M_LP_INT_THRESH(hw)),
HP_INT_THRESH_V(CSIO_SGE_DBFIFO_INT_THRESH) |
CSIO_HW_LP_INT_THRESH(hw,
CSIO_SGE_DBFIFO_INT_THRESH));
csio_set_reg_field(hw, SGE_DOORBELL_CONTROL, ENABLE_DROP,
ENABLE_DROP);
csio_set_reg_field(hw, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F,
ENABLE_DROP_F);
/* SGE_FL_BUFFER_SIZE0 is set up by csio_wr_fixup_host_params(). */
CSIO_SET_FLBUF_SIZE(hw, 1, CSIO_SGE_FLBUF_SIZE1);
csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE2 + sge->csio_fl_align - 1)
& ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE2);
& ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE2_A);
csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE3 + sge->csio_fl_align - 1)
& ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE3);
& ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE3_A);
CSIO_SET_FLBUF_SIZE(hw, 4, CSIO_SGE_FLBUF_SIZE4);
CSIO_SET_FLBUF_SIZE(hw, 5, CSIO_SGE_FLBUF_SIZE5);
CSIO_SET_FLBUF_SIZE(hw, 6, CSIO_SGE_FLBUF_SIZE6);
......@@ -1502,26 +1506,26 @@ csio_wr_set_sge(struct csio_hw *hw)
sge->counter_val[2] = CSIO_SGE_INT_CNT_VAL_2;
sge->counter_val[3] = CSIO_SGE_INT_CNT_VAL_3;
csio_wr_reg32(hw, THRESHOLD_0(sge->counter_val[0]) |
THRESHOLD_1(sge->counter_val[1]) |
THRESHOLD_2(sge->counter_val[2]) |
THRESHOLD_3(sge->counter_val[3]),
SGE_INGRESS_RX_THRESHOLD);
csio_wr_reg32(hw, THRESHOLD_0_V(sge->counter_val[0]) |
THRESHOLD_1_V(sge->counter_val[1]) |
THRESHOLD_2_V(sge->counter_val[2]) |
THRESHOLD_3_V(sge->counter_val[3]),
SGE_INGRESS_RX_THRESHOLD_A);
csio_wr_reg32(hw,
TIMERVALUE0(csio_us_to_core_ticks(hw, sge->timer_val[0])) |
TIMERVALUE1(csio_us_to_core_ticks(hw, sge->timer_val[1])),
SGE_TIMER_VALUE_0_AND_1);
TIMERVALUE0_V(csio_us_to_core_ticks(hw, sge->timer_val[0])) |
TIMERVALUE1_V(csio_us_to_core_ticks(hw, sge->timer_val[1])),
SGE_TIMER_VALUE_0_AND_1_A);
csio_wr_reg32(hw,
TIMERVALUE2(csio_us_to_core_ticks(hw, sge->timer_val[2])) |
TIMERVALUE3(csio_us_to_core_ticks(hw, sge->timer_val[3])),
SGE_TIMER_VALUE_2_AND_3);
TIMERVALUE2_V(csio_us_to_core_ticks(hw, sge->timer_val[2])) |
TIMERVALUE3_V(csio_us_to_core_ticks(hw, sge->timer_val[3])),
SGE_TIMER_VALUE_2_AND_3_A);
csio_wr_reg32(hw,
TIMERVALUE4(csio_us_to_core_ticks(hw, sge->timer_val[4])) |
TIMERVALUE5(csio_us_to_core_ticks(hw, sge->timer_val[5])),
SGE_TIMER_VALUE_4_AND_5);
TIMERVALUE4_V(csio_us_to_core_ticks(hw, sge->timer_val[4])) |
TIMERVALUE5_V(csio_us_to_core_ticks(hw, sge->timer_val[5])),
SGE_TIMER_VALUE_4_AND_5_A);
csio_init_intr_coalesce_parms(hw);
}
......
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