Commit a5562257 authored by Rahul Sharma's avatar Rahul Sharma Committed by Inki Dae

drm/exynos: add support for hdmiphy power control for exynos5

This patch adds support for controlling power of hdmi phy for
exynos5 soc. A special bit is provided in exynos5 for directly
switching of PHY while in exynos4, phy power needs to be controlled
through i2c settings. I2C configuration may affect the suspend to
resume and wake-up time requirements hence not added.
Signed-off-by: default avatarRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: default avatarInki Dae <inki.dae@samsung.com>
parent 000f1308
...@@ -2003,6 +2003,24 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata) ...@@ -2003,6 +2003,24 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
mdelay(10); mdelay(10);
} }
static void hdmiphy_poweron(struct hdmi_context *hdata)
{
DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
if (hdata->type == HDMI_TYPE14)
hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0,
HDMI_PHY_POWER_OFF_EN);
}
static void hdmiphy_poweroff(struct hdmi_context *hdata)
{
DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
if (hdata->type == HDMI_TYPE14)
hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0,
HDMI_PHY_POWER_OFF_EN);
}
static void hdmiphy_conf_apply(struct hdmi_context *hdata) static void hdmiphy_conf_apply(struct hdmi_context *hdata)
{ {
const u8 *hdmiphy_data; const u8 *hdmiphy_data;
...@@ -2175,6 +2193,8 @@ static void hdmi_poweron(struct hdmi_context *hdata) ...@@ -2175,6 +2193,8 @@ static void hdmi_poweron(struct hdmi_context *hdata)
clk_enable(res->hdmiphy); clk_enable(res->hdmiphy);
clk_enable(res->hdmi); clk_enable(res->hdmi);
clk_enable(res->sclk_hdmi); clk_enable(res->sclk_hdmi);
hdmiphy_poweron(hdata);
} }
static void hdmi_poweroff(struct hdmi_context *hdata) static void hdmi_poweroff(struct hdmi_context *hdata)
...@@ -2193,6 +2213,7 @@ static void hdmi_poweroff(struct hdmi_context *hdata) ...@@ -2193,6 +2213,7 @@ static void hdmi_poweroff(struct hdmi_context *hdata)
* its reset state seems to meet the condition. * its reset state seems to meet the condition.
*/ */
hdmiphy_conf_reset(hdata); hdmiphy_conf_reset(hdata);
hdmiphy_poweroff(hdata);
clk_disable(res->sclk_hdmi); clk_disable(res->sclk_hdmi);
clk_disable(res->hdmi); clk_disable(res->hdmi);
......
...@@ -176,6 +176,11 @@ ...@@ -176,6 +176,11 @@
#define HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C) #define HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C)
#define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080) #define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080)
/* PHY Control bit definition */
/* HDMI_PHY_CON_0 */
#define HDMI_PHY_POWER_OFF_EN (1 << 0)
/* Video related registers */ /* Video related registers */
#define HDMI_YMAX HDMI_CORE_BASE(0x0060) #define HDMI_YMAX HDMI_CORE_BASE(0x0060)
#define HDMI_YMIN HDMI_CORE_BASE(0x0064) #define HDMI_YMIN HDMI_CORE_BASE(0x0064)
......
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