Commit a5890c12 authored by Naga Sureshkumar Relli's avatar Naga Sureshkumar Relli Committed by Mark Brown

spi: dt-binding: document microchip coreQSPI

Add microchip coreQSPI compatible string and update the title/description
to reflect this addition.
Signed-off-by: default avatarNaga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220808064603.1174906-2-nagasuresh.relli@microchip.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 75c971dd
...@@ -4,7 +4,11 @@ ...@@ -4,7 +4,11 @@
$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings title: Microchip FPGA {Q,}SPI Controllers
description:
SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
fabric IP cores they are based on
maintainers: maintainers:
- Conor Dooley <conor.dooley@microchip.com> - Conor Dooley <conor.dooley@microchip.com>
...@@ -17,6 +21,7 @@ properties: ...@@ -17,6 +21,7 @@ properties:
enum: enum:
- microchip,mpfs-spi - microchip,mpfs-spi
- microchip,mpfs-qspi - microchip,mpfs-qspi
- microchip,coreqspi-rtl-v2 # FPGA QSPI
reg: reg:
maxItems: 1 maxItems: 1
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment