Commit a5ffbfa0 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amd/pm: enable deep sleep features control for SMU 13.0.0

Fulfill the interface for deep sleep features control.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarLikun Gao <Likun.Gao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9f3f1b03
...@@ -275,5 +275,8 @@ int smu_v13_0_init_pptable_microcode(struct smu_context *smu); ...@@ -275,5 +275,8 @@ int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
int smu_v13_0_run_btc(struct smu_context *smu); int smu_v13_0_run_btc(struct smu_context *smu);
int smu_v13_0_deep_sleep_control(struct smu_context *smu,
bool enablement);
#endif #endif
#endif #endif
...@@ -2111,3 +2111,76 @@ int smu_v13_0_run_btc(struct smu_context *smu) ...@@ -2111,3 +2111,76 @@ int smu_v13_0_run_btc(struct smu_context *smu)
return res; return res;
} }
int smu_v13_0_deep_sleep_control(struct smu_context *smu,
bool enablement)
{
struct amdgpu_device *adev = smu->adev;
int ret = 0;
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
if (ret) {
dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
return ret;
}
}
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
if (ret) {
dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
return ret;
}
}
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
if (ret) {
dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
return ret;
}
}
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
if (ret) {
dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
return ret;
}
}
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
if (ret) {
dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
return ret;
}
}
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
if (ret) {
dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
return ret;
}
}
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
if (ret) {
dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
return ret;
}
}
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
if (ret) {
dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
return ret;
}
}
return ret;
}
...@@ -141,6 +141,14 @@ static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = ...@@ -141,6 +141,14 @@ static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] =
[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
[SMU_FEATURE_FAN_CONTROL_BIT] = {1, FEATURE_FAN_CONTROL_BIT}, [SMU_FEATURE_FAN_CONTROL_BIT] = {1, FEATURE_FAN_CONTROL_BIT},
[SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT}, [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
[SMU_FEATURE_DS_GFXCLK_BIT] = {1, FEATURE_DS_GFXCLK_BIT},
[SMU_FEATURE_DS_SOCCLK_BIT] = {1, FEATURE_DS_SOCCLK_BIT},
[SMU_FEATURE_DS_UCLK_BIT] = {1, FEATURE_DS_UCLK_BIT},
[SMU_FEATURE_DS_FCLK_BIT] = {1, FEATURE_DS_FCLK_BIT},
[SMU_FEATURE_DS_LCLK_BIT] = {1, FEATURE_DS_LCLK_BIT},
[SMU_FEATURE_DS_VCN_BIT] = {1, FEATURE_DS_VCN_BIT},
[SMU_FEATURE_DS_MP0CLK_BIT] = {1, FEATURE_SOC_MPCLK_DS_BIT},
[SMU_FEATURE_DS_MP1CLK_BIT] = {1, FEATURE_BACO_MPCLK_DS_BIT},
}; };
static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = { static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
...@@ -1571,6 +1579,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { ...@@ -1571,6 +1579,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask, .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.set_tool_table_location = smu_v13_0_set_tool_table_location, .set_tool_table_location = smu_v13_0_set_tool_table_location,
.deep_sleep_control = smu_v13_0_deep_sleep_control,
}; };
void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
......
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