Skip to content

L
linux
Commit a6546460 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files
Options

arm64: dts: qcom: sc8180x: switch PCIe QMP PHY to new style of bindings 

Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes). While we are at it, rename PHY
nodes to `phy@`.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230820142035.89903-13-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 4a8fbb7c
Hide whitespace changes
Inline Side-by-side
Showing with 55 additions and 93 deletions
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View file @ a6546460
......@@ -1749,23 +1749,28 @@ pcie0: pci@1c00000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
phys = <&pcie0_lane>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
status = "disabled";
};
pcie0_phy: phy-wrapper@1c06000 {
pcie0_phy: phy@1c06000 {
compatible = "qcom,sc8180x-qmp-pcie-phy";
reg = <0 0x1c06000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01c06000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
#clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
......@@ -1774,21 +1779,6 @@ pcie0_phy: phy-wrapper@1c06000 {
assigned-clock-rates = <100000000>;
status = "disabled";
pcie0_lane: phy@1c06200 {
reg = <0 0x1c06200 0 0x170>, /* tx0 */
<0 0x1c06400 0 0x200>, /* rx0 */
<0 0x1c06a00 0 0x1f0>, /* pcs */
<0 0x1c06600 0 0x170>, /* tx1 */
<0 0x1c06800 0 0x200>, /* rx1 */
<0 0x1c06e00 0 0xf4>; /* pcs_com */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
#clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
#phy-cells = <0>;
};
};
pcie3: pci@1c08000 {
......@@ -1856,23 +1846,29 @@ pcie3: pci@1c08000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
phys = <&pcie3_lane>;
phys = <&pcie3_phy>;
phy-names = "pciephy";
status = "disabled";
};
pcie3_phy: phy-wrapper@1c0c000 {
pcie3_phy: phy@1c0c000 {
compatible = "qcom,sc8180x-qmp-pcie-phy";
reg = <0 0x1c0c000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01c0c000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
<&gcc GCC_PCIE_3_CLKREF_CLK>,
<&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
<&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_3_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
#clock-cells = <0>;
clock-output-names = "pcie_3_pipe_clk";
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_3_PHY_BCR>;
reset-names = "phy";
......@@ -1881,21 +1877,6 @@ pcie3_phy: phy-wrapper@1c0c000 {
assigned-clock-rates = <100000000>;
status = "disabled";
pcie3_lane: phy@1c0c200 {
reg = <0 0x1c0c200 0 0x170>, /* tx0 */
<0 0x1c0c400 0 0x200>, /* rx0 */
<0 0x1c0ca00 0 0x1f0>, /* pcs */
<0 0x1c0c600 0 0x170>, /* tx1 */
<0 0x1c0c800 0 0x200>, /* rx1 */
<0 0x1c0ce00 0 0xf4>; /* pcs_com */
clocks = <&gcc GCC_PCIE_3_PIPE_CLK>;
clock-names = "pipe0";
#clock-cells = <0>;
clock-output-names = "pcie_3_pipe_clk";
#phy-cells = <0>;
};
};
pcie1: pci@1c10000 {
......@@ -1963,23 +1944,29 @@ pcie1: pci@1c10000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
phys = <&pcie1_lane>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
status = "disabled";
};
pcie1_phy: phy-wrapper@1c16000 {
pcie1_phy: phy@1c16000 {
compatible = "qcom,sc8180x-qmp-pcie-phy";
reg = <0 0x1c16000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01c16000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_CLKREF_CLK>,
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
......@@ -1988,21 +1975,6 @@ pcie1_phy: phy-wrapper@1c16000 {
assigned-clock-rates = <100000000>;
status = "disabled";
pcie1_lane: phy@1c0e200 {
reg = <0 0x1c16200 0 0x170>, /* tx0 */
<0 0x1c16400 0 0x200>, /* rx0 */
<0 0x1c16a00 0 0x1f0>, /* pcs */
<0 0x1c16600 0 0x170>, /* tx1 */
<0 0x1c16800 0 0x200>, /* rx1 */
<0 0x1c16e00 0 0xf4>; /* pcs_com */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe0";
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
#phy-cells = <0>;
};
};
pcie2: pci@1c18000 {
......@@ -2070,23 +2042,29 @@ pcie2: pci@1c18000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
phys = <&pcie2_lane>;
phys = <&pcie2_phy>;
phy-names = "pciephy";
status = "disabled";
};
pcie2_phy: phy-wrapper@1c1c000 {
pcie2_phy: phy@1c1c000 {
compatible = "qcom,sc8180x-qmp-pcie-phy";
reg = <0 0x1c1c000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0 0x01c1c000 0 0x1000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2_CLKREF_CLK>,
<&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "refgen";
<&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"refgen",
"pipe";
#clock-cells = <0>;
clock-output-names = "pcie_3_pipe_clk";
#phy-cells = <0>;
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "phy";
......@@ -2095,22 +2073,6 @@ pcie2_phy: phy-wrapper@1c1c000 {
assigned-clock-rates = <100000000>;
status = "disabled";
pcie2_lane: phy@1c0e200 {
reg = <0 0x1c1c200 0 0x170>, /* tx0 */
<0 0x1c1c400 0 0x200>, /* rx0 */
<0 0x1c1ca00 0 0x1f0>, /* pcs */
<0 0x1c1c600 0 0x170>, /* tx1 */
<0 0x1c1c800 0 0x200>, /* rx1 */
<0 0x1c1ce00 0 0xf4>; /* pcs_com */
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "pipe0";
#clock-cells = <0>;
clock-output-names = "pcie_2_pipe_clk";
#phy-cells = <0>;
};
};
ufs_mem_hc: ufshc@1d84000 {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7