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Commit a69c5ed2 authored by Rob Clark's avatar Rob Clark
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drm/msm: update generated headers 

Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent a2c3c0a5
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Showing with 1149 additions and 342 deletions
drivers/gpu/drm/msm/adreno/a2xx.xml.h
View file @ a69c5ed2
......@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
Copyright (C) 2013-2018 by the following authors:
......
drivers/gpu/drm/msm/adreno/a3xx.xml.h
View file @ a69c5ed2
......@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
Copyright (C) 2013-2018 by the following authors:
......
drivers/gpu/drm/msm/adreno/a4xx.xml.h
View file @ a69c5ed2
......@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
Copyright (C) 2013-2018 by the following authors:
......
drivers/gpu/drm/msm/adreno/a5xx.xml.h
View file @ a69c5ed2
......@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
Copyright (C) 2013-2018 by the following authors:
......
drivers/gpu/drm/msm/adreno/a6xx.xml.h
View file @ a69c5ed2
......@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
Copyright (C) 2013-2018 by the following authors:
......@@ -268,8 +268,687 @@ enum a6xx_depth_format {
DEPTH6_32 = 4,
};
enum a6xx_shader_id {
A6XX_TP0_TMO_DATA = 9,
A6XX_TP0_SMO_DATA = 10,
A6XX_TP0_MIPMAP_BASE_DATA = 11,
A6XX_TP1_TMO_DATA = 25,
A6XX_TP1_SMO_DATA = 26,
A6XX_TP1_MIPMAP_BASE_DATA = 27,
A6XX_SP_INST_DATA = 41,
A6XX_SP_LB_0_DATA = 42,
A6XX_SP_LB_1_DATA = 43,
A6XX_SP_LB_2_DATA = 44,
A6XX_SP_LB_3_DATA = 45,
A6XX_SP_LB_4_DATA = 46,
A6XX_SP_LB_5_DATA = 47,
A6XX_SP_CB_BINDLESS_DATA = 48,
A6XX_SP_CB_LEGACY_DATA = 49,
A6XX_SP_UAV_DATA = 50,
A6XX_SP_INST_TAG = 51,
A6XX_SP_CB_BINDLESS_TAG = 52,
A6XX_SP_TMO_UMO_TAG = 53,
A6XX_SP_SMO_TAG = 54,
A6XX_SP_STATE_DATA = 55,
A6XX_HLSQ_CHUNK_CVS_RAM = 73,
A6XX_HLSQ_CHUNK_CPS_RAM = 74,
A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
A6XX_HLSQ_CVS_MISC_RAM = 80,
A6XX_HLSQ_CPS_MISC_RAM = 81,
A6XX_HLSQ_INST_RAM = 82,
A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
A6XX_HLSQ_INST_RAM_TAG = 87,
A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
A6XX_HLSQ_PWR_REST_RAM = 90,
A6XX_HLSQ_PWR_REST_TAG = 91,
A6XX_HLSQ_DATAPATH_META = 96,
A6XX_HLSQ_FRONTEND_META = 97,
A6XX_HLSQ_INDIRECT_META = 98,
A6XX_HLSQ_BACKEND_META = 99,
};
enum a6xx_debugbus_id {
A6XX_DBGBUS_CP = 1,
A6XX_DBGBUS_RBBM = 2,
A6XX_DBGBUS_VBIF = 3,
A6XX_DBGBUS_HLSQ = 4,
A6XX_DBGBUS_UCHE = 5,
A6XX_DBGBUS_DPM = 6,
A6XX_DBGBUS_TESS = 7,
A6XX_DBGBUS_PC = 8,
A6XX_DBGBUS_VFDP = 9,
A6XX_DBGBUS_VPC = 10,
A6XX_DBGBUS_TSE = 11,
A6XX_DBGBUS_RAS = 12,
A6XX_DBGBUS_VSC = 13,
A6XX_DBGBUS_COM = 14,
A6XX_DBGBUS_LRZ = 16,
A6XX_DBGBUS_A2D = 17,
A6XX_DBGBUS_CCUFCHE = 18,
A6XX_DBGBUS_GMU_CX = 19,
A6XX_DBGBUS_RBP = 20,
A6XX_DBGBUS_DCS = 21,
A6XX_DBGBUS_DBGC = 22,
A6XX_DBGBUS_CX = 23,
A6XX_DBGBUS_GMU_GX = 24,
A6XX_DBGBUS_TPFCHE = 25,
A6XX_DBGBUS_GBIF_GX = 26,
A6XX_DBGBUS_GPC = 29,
A6XX_DBGBUS_LARC = 30,
A6XX_DBGBUS_HLSQ_SPTP = 31,
A6XX_DBGBUS_RB_0 = 32,
A6XX_DBGBUS_RB_1 = 33,
A6XX_DBGBUS_UCHE_WRAPPER = 36,
A6XX_DBGBUS_CCU_0 = 40,
A6XX_DBGBUS_CCU_1 = 41,
A6XX_DBGBUS_VFD_0 = 56,
A6XX_DBGBUS_VFD_1 = 57,
A6XX_DBGBUS_VFD_2 = 58,
A6XX_DBGBUS_VFD_3 = 59,
A6XX_DBGBUS_SP_0 = 64,
A6XX_DBGBUS_SP_1 = 65,
A6XX_DBGBUS_TPL1_0 = 72,
A6XX_DBGBUS_TPL1_1 = 73,
A6XX_DBGBUS_TPL1_2 = 74,
A6XX_DBGBUS_TPL1_3 = 75,
};
enum a6xx_cp_perfcounter_select {
PERF_CP_ALWAYS_COUNT = 0,
PERF_CP_BUSY_GFX_CORE_IDLE = 1,
PERF_CP_BUSY_CYCLES = 2,
PERF_CP_NUM_PREEMPTIONS = 3,
PERF_CP_PREEMPTION_REACTION_DELAY = 4,
PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
PERF_CP_PREDICATED_DRAWS_KILLED = 8,
PERF_CP_MODE_SWITCH = 9,
PERF_CP_ZPASS_DONE = 10,
PERF_CP_CONTEXT_DONE = 11,
PERF_CP_CACHE_FLUSH = 12,
PERF_CP_LONG_PREEMPTIONS = 13,
PERF_CP_SQE_I_CACHE_STARVE = 14,
PERF_CP_SQE_IDLE = 15,
PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
PERF_CP_SQE_PM4_STARVE_SDS = 17,
PERF_CP_SQE_MRB_STARVE = 18,
PERF_CP_SQE_RRB_STARVE = 19,
PERF_CP_SQE_VSD_STARVE = 20,
PERF_CP_VSD_DECODE_STARVE = 21,
PERF_CP_SQE_PIPE_OUT_STALL = 22,
PERF_CP_SQE_SYNC_STALL = 23,
PERF_CP_SQE_PM4_WFI_STALL = 24,
PERF_CP_SQE_SYS_WFI_STALL = 25,
PERF_CP_SQE_T4_EXEC = 26,
PERF_CP_SQE_LOAD_STATE_EXEC = 27,
PERF_CP_SQE_SAVE_SDS_STATE = 28,
PERF_CP_SQE_DRAW_EXEC = 29,
PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
PERF_CP_SQE_EXEC_PROFILED = 31,
PERF_CP_MEMORY_POOL_EMPTY = 32,
PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
PERF_CP_AHB_STALL_SQE_GMU = 36,
PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
PERF_CP_CLUSTER0_EMPTY = 39,
PERF_CP_CLUSTER1_EMPTY = 40,
PERF_CP_CLUSTER2_EMPTY = 41,
PERF_CP_CLUSTER3_EMPTY = 42,
PERF_CP_CLUSTER4_EMPTY = 43,
PERF_CP_CLUSTER5_EMPTY = 44,
PERF_CP_PM4_DATA = 45,
PERF_CP_PM4_HEADERS = 46,
PERF_CP_VBIF_READ_BEATS = 47,
PERF_CP_VBIF_WRITE_BEATS = 48,
PERF_CP_SQE_INSTR_COUNTER = 49,
};
enum a6xx_rbbm_perfcounter_select {
PERF_RBBM_ALWAYS_COUNT = 0,
PERF_RBBM_ALWAYS_ON = 1,
PERF_RBBM_TSE_BUSY = 2,
PERF_RBBM_RAS_BUSY = 3,
PERF_RBBM_PC_DCALL_BUSY = 4,
PERF_RBBM_PC_VSD_BUSY = 5,
PERF_RBBM_STATUS_MASKED = 6,
PERF_RBBM_COM_BUSY = 7,
PERF_RBBM_DCOM_BUSY = 8,
PERF_RBBM_VBIF_BUSY = 9,
PERF_RBBM_VSC_BUSY = 10,
PERF_RBBM_TESS_BUSY = 11,
PERF_RBBM_UCHE_BUSY = 12,
PERF_RBBM_HLSQ_BUSY = 13,
};
enum a6xx_pc_perfcounter_select {
PERF_PC_BUSY_CYCLES = 0,
PERF_PC_WORKING_CYCLES = 1,
PERF_PC_STALL_CYCLES_VFD = 2,
PERF_PC_STALL_CYCLES_TSE = 3,
PERF_PC_STALL_CYCLES_VPC = 4,
PERF_PC_STALL_CYCLES_UCHE = 5,
PERF_PC_STALL_CYCLES_TESS = 6,
PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
PERF_PC_PASS1_TF_STALL_CYCLES = 9,
PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
PERF_PC_STARVE_CYCLES_DI = 14,
PERF_PC_VIS_STREAMS_LOADED = 15,
PERF_PC_INSTANCES = 16,
PERF_PC_VPC_PRIMITIVES = 17,
PERF_PC_DEAD_PRIM = 18,
PERF_PC_LIVE_PRIM = 19,
PERF_PC_VERTEX_HITS = 20,
PERF_PC_IA_VERTICES = 21,
PERF_PC_IA_PRIMITIVES = 22,
PERF_PC_GS_PRIMITIVES = 23,
PERF_PC_HS_INVOCATIONS = 24,
PERF_PC_DS_INVOCATIONS = 25,
PERF_PC_VS_INVOCATIONS = 26,
PERF_PC_GS_INVOCATIONS = 27,
PERF_PC_DS_PRIMITIVES = 28,
PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
PERF_PC_3D_DRAWCALLS = 30,
PERF_PC_2D_DRAWCALLS = 31,
PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
PERF_TESS_BUSY_CYCLES = 33,
PERF_TESS_WORKING_CYCLES = 34,
PERF_TESS_STALL_CYCLES_PC = 35,
PERF_TESS_STARVE_CYCLES_PC = 36,
PERF_PC_TSE_TRANSACTION = 37,
PERF_PC_TSE_VERTEX = 38,
PERF_PC_TESS_PC_UV_TRANS = 39,
PERF_PC_TESS_PC_UV_PATCHES = 40,
PERF_PC_TESS_FACTOR_TRANS = 41,
};
enum a6xx_vfd_perfcounter_select {
PERF_VFD_BUSY_CYCLES = 0,
PERF_VFD_STALL_CYCLES_UCHE = 1,
PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
PERF_VFD_STALL_CYCLES_SP_INFO = 3,
PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
PERF_VFD_STARVE_CYCLES_UCHE = 5,
PERF_VFD_RBUFFER_FULL = 6,
PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
PERF_VFD_NUM_ATTRIBUTES = 9,
PERF_VFD_UPPER_SHADER_FIBERS = 10,
PERF_VFD_LOWER_SHADER_FIBERS = 11,
PERF_VFD_MODE_0_FIBERS = 12,
PERF_VFD_MODE_1_FIBERS = 13,
PERF_VFD_MODE_2_FIBERS = 14,
PERF_VFD_MODE_3_FIBERS = 15,
PERF_VFD_MODE_4_FIBERS = 16,
PERF_VFD_TOTAL_VERTICES = 17,
PERF_VFDP_STALL_CYCLES_VFD = 18,
PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
PERF_VFDP_STARVE_CYCLES_PC = 21,
PERF_VFDP_VS_STAGE_WAVES = 22,
};
enum a6xx_hslq_perfcounter_select {
PERF_HLSQ_BUSY_CYCLES = 0,
PERF_HLSQ_STALL_CYCLES_UCHE = 1,
PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
PERF_HLSQ_QUADS = 8,
PERF_HLSQ_CS_INVOCATIONS = 9,
PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
PERF_HLSQ_STALL_CYCLES_VPC = 18,
PERF_HLSQ_PIXELS = 19,
PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
};
enum a6xx_vpc_perfcounter_select {
PERF_VPC_BUSY_CYCLES = 0,
PERF_VPC_WORKING_CYCLES = 1,
PERF_VPC_STALL_CYCLES_UCHE = 2,
PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
PERF_VPC_STALL_CYCLES_PC = 5,
PERF_VPC_STALL_CYCLES_SP_LM = 6,
PERF_VPC_STARVE_CYCLES_SP = 7,
PERF_VPC_STARVE_CYCLES_LRZ = 8,
PERF_VPC_PC_PRIMITIVES = 9,
PERF_VPC_SP_COMPONENTS = 10,
PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
PERF_VPC_LM_TRANSACTION = 14,
PERF_VPC_STREAMOUT_TRANSACTION = 15,
PERF_VPC_VS_BUSY_CYCLES = 16,
PERF_VPC_PS_BUSY_CYCLES = 17,
PERF_VPC_VS_WORKING_CYCLES = 18,
PERF_VPC_PS_WORKING_CYCLES = 19,
PERF_VPC_STARVE_CYCLES_RB = 20,
PERF_VPC_NUM_VPCRAM_READ_POS = 21,
PERF_VPC_WIT_FULL_CYCLES = 22,
PERF_VPC_VPCRAM_FULL_CYCLES = 23,
PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
PERF_VPC_NUM_VPCRAM_WRITE = 25,
PERF_VPC_NUM_VPCRAM_READ_SO = 26,
PERF_VPC_NUM_ATTR_REQ_LM = 27,
};
enum a6xx_tse_perfcounter_select {
PERF_TSE_BUSY_CYCLES = 0,
PERF_TSE_CLIPPING_CYCLES = 1,
PERF_TSE_STALL_CYCLES_RAS = 2,
PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
PERF_TSE_STARVE_CYCLES_PC = 5,
PERF_TSE_INPUT_PRIM = 6,
PERF_TSE_INPUT_NULL_PRIM = 7,
PERF_TSE_TRIVAL_REJ_PRIM = 8,
PERF_TSE_CLIPPED_PRIM = 9,
PERF_TSE_ZERO_AREA_PRIM = 10,
PERF_TSE_FACENESS_CULLED_PRIM = 11,
PERF_TSE_ZERO_PIXEL_PRIM = 12,
PERF_TSE_OUTPUT_NULL_PRIM = 13,
PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
PERF_TSE_CINVOCATION = 15,
PERF_TSE_CPRIMITIVES = 16,
PERF_TSE_2D_INPUT_PRIM = 17,
PERF_TSE_2D_ALIVE_CYCLES = 18,
PERF_TSE_CLIP_PLANES = 19,
};
enum a6xx_ras_perfcounter_select {
PERF_RAS_BUSY_CYCLES = 0,
PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
PERF_RAS_STALL_CYCLES_LRZ = 2,
PERF_RAS_STARVE_CYCLES_TSE = 3,
PERF_RAS_SUPER_TILES = 4,
PERF_RAS_8X4_TILES = 5,
PERF_RAS_MASKGEN_ACTIVE = 6,
PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
PERF_RAS_PRIM_KILLED_INVISILBE = 9,
PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
PERF_RAS_BLOCKS = 12,
};
enum a6xx_uche_perfcounter_select {
PERF_UCHE_BUSY_CYCLES = 0,
PERF_UCHE_STALL_CYCLES_ARBITER = 1,
PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
PERF_UCHE_VBIF_READ_BEATS_TP = 4,
PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
PERF_UCHE_VBIF_READ_BEATS_SP = 8,
PERF_UCHE_READ_REQUESTS_TP = 9,
PERF_UCHE_READ_REQUESTS_VFD = 10,
PERF_UCHE_READ_REQUESTS_HLSQ = 11,
PERF_UCHE_READ_REQUESTS_LRZ = 12,
PERF_UCHE_READ_REQUESTS_SP = 13,
PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
PERF_UCHE_WRITE_REQUESTS_SP = 15,
PERF_UCHE_WRITE_REQUESTS_VPC = 16,
PERF_UCHE_WRITE_REQUESTS_VSC = 17,
PERF_UCHE_EVICTS = 18,
PERF_UCHE_BANK_REQ0 = 19,
PERF_UCHE_BANK_REQ1 = 20,
PERF_UCHE_BANK_REQ2 = 21,
PERF_UCHE_BANK_REQ3 = 22,
PERF_UCHE_BANK_REQ4 = 23,
PERF_UCHE_BANK_REQ5 = 24,
PERF_UCHE_BANK_REQ6 = 25,
PERF_UCHE_BANK_REQ7 = 26,
PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
PERF_UCHE_GMEM_READ_BEATS = 29,
PERF_UCHE_TPH_REF_FULL = 30,
PERF_UCHE_TPH_VICTIM_FULL = 31,
PERF_UCHE_TPH_EXT_FULL = 32,
PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
PERF_UCHE_VBIF_READ_BEATS_PC = 36,
PERF_UCHE_READ_REQUESTS_PC = 37,
PERF_UCHE_RAM_READ_REQ = 38,
PERF_UCHE_RAM_WRITE_REQ = 39,
};
enum a6xx_tp_perfcounter_select {
PERF_TP_BUSY_CYCLES = 0,
PERF_TP_STALL_CYCLES_UCHE = 1,
PERF_TP_LATENCY_CYCLES = 2,
PERF_TP_LATENCY_TRANS = 3,
PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
PERF_TP_L1_CACHELINE_REQUESTS = 6,
PERF_TP_L1_CACHELINE_MISSES = 7,
PERF_TP_SP_TP_TRANS = 8,
PERF_TP_TP_SP_TRANS = 9,
PERF_TP_OUTPUT_PIXELS = 10,
PERF_TP_FILTER_WORKLOAD_16BIT = 11,
PERF_TP_FILTER_WORKLOAD_32BIT = 12,
PERF_TP_QUADS_RECEIVED = 13,
PERF_TP_QUADS_OFFSET = 14,
PERF_TP_QUADS_SHADOW = 15,
PERF_TP_QUADS_ARRAY = 16,
PERF_TP_QUADS_GRADIENT = 17,
PERF_TP_QUADS_1D = 18,
PERF_TP_QUADS_2D = 19,
PERF_TP_QUADS_BUFFER = 20,
PERF_TP_QUADS_3D = 21,
PERF_TP_QUADS_CUBE = 22,
PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
PERF_TP_OUTPUT_PIXELS_POINT = 25,
PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
PERF_TP_OUTPUT_PIXELS_MIP = 27,
PERF_TP_OUTPUT_PIXELS_ANISO = 28,
PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
PERF_TP_FLAG_CACHE_REQUESTS = 30,
PERF_TP_FLAG_CACHE_MISSES = 31,
PERF_TP_L1_5_L2_REQUESTS = 32,
PERF_TP_2D_OUTPUT_PIXELS = 33,
PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
PERF_TP_TPA2TPC_TRANS = 38,
PERF_TP_L1_MISSES_ASTC_1TILE = 39,
PERF_TP_L1_MISSES_ASTC_2TILE = 40,
PERF_TP_L1_MISSES_ASTC_4TILE = 41,
PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
PERF_TP_L1_BANK_CONFLICT = 44,
PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
PERF_TP_FRONTEND_WORKING_CYCLES = 48,
PERF_TP_L1_TAG_WORKING_CYCLES = 49,
PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
PERF_TP_BACKEND_WORKING_CYCLES = 52,
PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
PERF_TP_STARVE_CYCLES_SP = 55,
PERF_TP_STARVE_CYCLES_UCHE = 56,
};
enum a6xx_sp_perfcounter_select {
PERF_SP_BUSY_CYCLES = 0,
PERF_SP_ALU_WORKING_CYCLES = 1,
PERF_SP_EFU_WORKING_CYCLES = 2,
PERF_SP_STALL_CYCLES_VPC = 3,
PERF_SP_STALL_CYCLES_TP = 4,
PERF_SP_STALL_CYCLES_UCHE = 5,
PERF_SP_STALL_CYCLES_RB = 6,
PERF_SP_NON_EXECUTION_CYCLES = 7,
PERF_SP_WAVE_CONTEXTS = 8,
PERF_SP_WAVE_CONTEXT_CYCLES = 9,
PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
PERF_SP_WAVE_CTRL_CYCLES = 16,
PERF_SP_WAVE_LOAD_CYCLES = 17,
PERF_SP_WAVE_EMIT_CYCLES = 18,
PERF_SP_WAVE_NOP_CYCLES = 19,
PERF_SP_WAVE_WAIT_CYCLES = 20,
PERF_SP_WAVE_FETCH_CYCLES = 21,
PERF_SP_WAVE_IDLE_CYCLES = 22,
PERF_SP_WAVE_END_CYCLES = 23,
PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
PERF_SP_WAVE_JOIN_CYCLES = 26,
PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
PERF_SP_LM_STORE_INSTRUCTIONS = 28,
PERF_SP_LM_ATOMICS = 29,
PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
PERF_SP_GM_STORE_INSTRUCTIONS = 31,
PERF_SP_GM_ATOMICS = 32,
PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
PERF_SP_VS_INSTRUCTIONS = 43,
PERF_SP_FS_INSTRUCTIONS = 44,
PERF_SP_ADDR_LOCK_COUNT = 45,
PERF_SP_UCHE_READ_TRANS = 46,
PERF_SP_UCHE_WRITE_TRANS = 47,
PERF_SP_EXPORT_VPC_TRANS = 48,
PERF_SP_EXPORT_RB_TRANS = 49,
PERF_SP_PIXELS_KILLED = 50,
PERF_SP_ICL1_REQUESTS = 51,
PERF_SP_ICL1_MISSES = 52,
PERF_SP_HS_INSTRUCTIONS = 53,
PERF_SP_DS_INSTRUCTIONS = 54,
PERF_SP_GS_INSTRUCTIONS = 55,
PERF_SP_CS_INSTRUCTIONS = 56,
PERF_SP_GPR_READ = 57,
PERF_SP_GPR_WRITE = 58,
PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
PERF_SP_LM_BANK_CONFLICTS = 61,
PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
PERF_SP_LM_WORKING_CYCLES = 65,
PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
PERF_SP_STARVE_CYCLES_HLSQ = 69,
PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
PERF_SP_WORKING_EU = 71,
PERF_SP_ANY_EU_WORKING = 72,
PERF_SP_WORKING_EU_FS_STAGE = 73,
PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
PERF_SP_WORKING_EU_VS_STAGE = 75,
PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
PERF_SP_WORKING_EU_CS_STAGE = 77,
PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
PERF_SP_GPR_READ_PREFETCH = 79,
PERF_SP_GPR_READ_CONFLICT = 80,
PERF_SP_GPR_WRITE_CONFLICT = 81,
PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
PERF_SP_EXECUTABLE_WAVES = 84,
};
enum a6xx_rb_perfcounter_select {
PERF_RB_BUSY_CYCLES = 0,
PERF_RB_STALL_CYCLES_HLSQ = 1,
PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
PERF_RB_STARVE_CYCLES_SP = 5,
PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
PERF_RB_STARVE_CYCLES_CCU = 7,
PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
PERF_RB_Z_WORKLOAD = 10,
PERF_RB_HLSQ_ACTIVE = 11,
PERF_RB_Z_READ = 12,
PERF_RB_Z_WRITE = 13,
PERF_RB_C_READ = 14,
PERF_RB_C_WRITE = 15,
PERF_RB_TOTAL_PASS = 16,
PERF_RB_Z_PASS = 17,
PERF_RB_Z_FAIL = 18,
PERF_RB_S_FAIL = 19,
PERF_RB_BLENDED_FXP_COMPONENTS = 20,
PERF_RB_BLENDED_FP16_COMPONENTS = 21,
PERF_RB_PS_INVOCATIONS = 22,
PERF_RB_2D_ALIVE_CYCLES = 23,
PERF_RB_2D_STALL_CYCLES_A2D = 24,
PERF_RB_2D_STARVE_CYCLES_SRC = 25,
PERF_RB_2D_STARVE_CYCLES_SP = 26,
PERF_RB_2D_STARVE_CYCLES_DST = 27,
PERF_RB_2D_VALID_PIXELS = 28,
PERF_RB_3D_PIXELS = 29,
PERF_RB_BLENDER_WORKING_CYCLES = 30,
PERF_RB_ZPROC_WORKING_CYCLES = 31,
PERF_RB_CPROC_WORKING_CYCLES = 32,
PERF_RB_SAMPLER_WORKING_CYCLES = 33,
PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
PERF_RB_STALL_CYCLES_VPC = 38,
PERF_RB_2D_INPUT_TRANS = 39,
PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
PERF_RB_BLENDED_FP32_COMPONENTS = 42,
PERF_RB_COLOR_PIX_TILES = 43,
PERF_RB_STALL_CYCLES_CCU = 44,
PERF_RB_EARLY_Z_ARB3_GRANT = 45,
PERF_RB_LATE_Z_ARB3_GRANT = 46,
PERF_RB_EARLY_Z_SKIP_GRANT = 47,
};
enum a6xx_vsc_perfcounter_select {
PERF_VSC_BUSY_CYCLES = 0,
PERF_VSC_WORKING_CYCLES = 1,
PERF_VSC_STALL_CYCLES_UCHE = 2,
PERF_VSC_EOT_NUM = 3,
PERF_VSC_INPUT_TILES = 4,
};
enum a6xx_ccu_perfcounter_select {
PERF_CCU_BUSY_CYCLES = 0,
PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
PERF_CCU_DEPTH_BLOCKS = 4,
PERF_CCU_COLOR_BLOCKS = 5,
PERF_CCU_DEPTH_BLOCK_HIT = 6,
PERF_CCU_COLOR_BLOCK_HIT = 7,
PERF_CCU_PARTIAL_BLOCK_READ = 8,
PERF_CCU_GMEM_READ = 9,
PERF_CCU_GMEM_WRITE = 10,
PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
PERF_CCU_2D_RD_REQ = 27,
PERF_CCU_2D_WR_REQ = 28,
};
enum a6xx_lrz_perfcounter_select {
PERF_LRZ_BUSY_CYCLES = 0,
PERF_LRZ_STARVE_CYCLES_RAS = 1,
PERF_LRZ_STALL_CYCLES_RB = 2,
PERF_LRZ_STALL_CYCLES_VSC = 3,
PERF_LRZ_STALL_CYCLES_VPC = 4,
PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
PERF_LRZ_STALL_CYCLES_UCHE = 6,
PERF_LRZ_LRZ_READ = 7,
PERF_LRZ_LRZ_WRITE = 8,
PERF_LRZ_READ_LATENCY = 9,
PERF_LRZ_MERGE_CACHE_UPDATING = 10,
PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
PERF_LRZ_FULL_8X8_TILES = 14,
PERF_LRZ_PARTIAL_8X8_TILES = 15,
PERF_LRZ_TILE_KILLED = 16,
PERF_LRZ_TOTAL_PIXEL = 17,
PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
PERF_LRZ_FULLY_COVERED_TILES = 19,
PERF_LRZ_PARTIAL_COVERED_TILES = 20,
PERF_LRZ_FEEDBACK_ACCEPT = 21,
PERF_LRZ_FEEDBACK_DISCARD = 22,
PERF_LRZ_FEEDBACK_STALL = 23,
PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
PERF_LRZ_STALL_CYCLES_VC = 26,
PERF_LRZ_RAS_MASK_TRANS = 27,
};
enum a6xx_cmp_perfcounter_select {
PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
PERF_CMPDECMP_VBIF_READ_DATA = 7,
PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
PERF_CMPDECMP_2D_RD_DATA = 28,
PERF_CMPDECMP_2D_WR_DATA = 29,
PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
PERF_CMPDECMP_2D_PIXELS = 39,
};
enum a6xx_tex_filter {
......@@ -1765,12 +2444,39 @@ static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
#define REG_A6XX_VBIF_VERSION 0x00003000
#define REG_A6XX_VBIF_CLKON 0x00003001
#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
#define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
#define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080
#define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081
#define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
#define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085
#define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086
#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f
#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0
static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
{
return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
}
#define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087
#define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088
#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff
#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0
static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
{
return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
}
#define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c
#define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0
#define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1
......@@ -1813,313 +2519,79 @@ static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00018400
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00018401
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00018402
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00018403
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
}
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00018404
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
}
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00018405
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
}
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00018408
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00018409
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0001840a
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0001840b
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0001840c
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0001840d
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0001840e
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0001840f
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00018410
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
}
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00018411
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
}
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0001842f
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00018430
#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
#define REG_A6XX_X1_WINDOW_OFFSET 0x000088d4
#define A6XX_X1_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
#define A6XX_X1_WINDOW_OFFSET_X__MASK 0x00007fff
#define A6XX_X1_WINDOW_OFFSET_X__SHIFT 0
static inline uint32_t A6XX_X1_WINDOW_OFFSET_X(uint32_t val)
{
return ((val) << A6XX_X1_WINDOW_OFFSET_X__SHIFT) & A6XX_X1_WINDOW_OFFSET_X__MASK;
}
#define A6XX_X1_WINDOW_OFFSET_Y__MASK 0x7fff0000
#define A6XX_X1_WINDOW_OFFSET_Y__SHIFT 16
static inline uint32_t A6XX_X1_WINDOW_OFFSET_Y(uint32_t val)
{
return ((val) << A6XX_X1_WINDOW_OFFSET_Y__SHIFT) & A6XX_X1_WINDOW_OFFSET_Y__MASK;
}
#define REG_A6XX_X2_WINDOW_OFFSET 0x0000b4d1
#define A6XX_X2_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
#define A6XX_X2_WINDOW_OFFSET_X__MASK 0x00007fff
#define A6XX_X2_WINDOW_OFFSET_X__SHIFT 0
static inline uint32_t A6XX_X2_WINDOW_OFFSET_X(uint32_t val)
#define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
#define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE 0x80000000
#define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00007fff
#define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0
static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
{
return ((val) << A6XX_X2_WINDOW_OFFSET_X__SHIFT) & A6XX_X2_WINDOW_OFFSET_X__MASK;
return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
}
#define A6XX_X2_WINDOW_OFFSET_Y__MASK 0x7fff0000
#define A6XX_X2_WINDOW_OFFSET_Y__SHIFT 16
static inline uint32_t A6XX_X2_WINDOW_OFFSET_Y(uint32_t val)
#define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x7fff0000
#define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16
static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
{
return ((val) << A6XX_X2_WINDOW_OFFSET_Y__SHIFT) & A6XX_X2_WINDOW_OFFSET_Y__MASK;
return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
}
#define REG_A6XX_X3_WINDOW_OFFSET 0x0000b307
#define A6XX_X3_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
#define A6XX_X3_WINDOW_OFFSET_X__MASK 0x00007fff
#define A6XX_X3_WINDOW_OFFSET_X__SHIFT 0
static inline uint32_t A6XX_X3_WINDOW_OFFSET_X(uint32_t val)
#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
#define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff
#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
{
return ((val) << A6XX_X3_WINDOW_OFFSET_X__SHIFT) & A6XX_X3_WINDOW_OFFSET_X__MASK;
return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
}
#define A6XX_X3_WINDOW_OFFSET_Y__MASK 0x7fff0000
#define A6XX_X3_WINDOW_OFFSET_Y__SHIFT 16
static inline uint32_t A6XX_X3_WINDOW_OFFSET_Y(uint32_t val)
#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000
#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
{
return ((val) << A6XX_X3_WINDOW_OFFSET_Y__SHIFT) & A6XX_X3_WINDOW_OFFSET_Y__MASK;
return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
}
#define REG_A6XX_X1_BIN_SIZE 0x000080a1
#define A6XX_X1_BIN_SIZE_WIDTH__MASK 0x000000ff
#define A6XX_X1_BIN_SIZE_WIDTH__SHIFT 0
static inline uint32_t A6XX_X1_BIN_SIZE_WIDTH(uint32_t val)
#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
#define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff
#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
{
return ((val >> 5) << A6XX_X1_BIN_SIZE_WIDTH__SHIFT) & A6XX_X1_BIN_SIZE_WIDTH__MASK;
return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
}
#define A6XX_X1_BIN_SIZE_HEIGHT__MASK 0x0001ff00
#define A6XX_X1_BIN_SIZE_HEIGHT__SHIFT 8
static inline uint32_t A6XX_X1_BIN_SIZE_HEIGHT(uint32_t val)
#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000
#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
{
return ((val >> 4) << A6XX_X1_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X1_BIN_SIZE_HEIGHT__MASK;
return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
}
#define REG_A6XX_X2_BIN_SIZE 0x00008800
#define A6XX_X2_BIN_SIZE_WIDTH__MASK 0x000000ff
#define A6XX_X2_BIN_SIZE_WIDTH__SHIFT 0
static inline uint32_t A6XX_X2_BIN_SIZE_WIDTH(uint32_t val)
#define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1
#define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x000000ff
#define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0
static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
{
return ((val >> 5) << A6XX_X2_BIN_SIZE_WIDTH__SHIFT) & A6XX_X2_BIN_SIZE_WIDTH__MASK;
return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
}
#define A6XX_X2_BIN_SIZE_HEIGHT__MASK 0x0001ff00
#define A6XX_X2_BIN_SIZE_HEIGHT__SHIFT 8
static inline uint32_t A6XX_X2_BIN_SIZE_HEIGHT(uint32_t val)
#define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x0001ff00
#define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8
static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
{
return ((val >> 4) << A6XX_X2_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X2_BIN_SIZE_HEIGHT__MASK;
return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
}
#define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000
#define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000
#define REG_A6XX_X3_BIN_SIZE 0x000088d3
#define A6XX_X3_BIN_SIZE_WIDTH__MASK 0x000000ff
#define A6XX_X3_BIN_SIZE_WIDTH__SHIFT 0
static inline uint32_t A6XX_X3_BIN_SIZE_WIDTH(uint32_t val)
#define REG_A6XX_RB_BIN_CONTROL2 0x000088d3
#define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x000000ff
#define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0
static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
{
return ((val >> 5) << A6XX_X3_BIN_SIZE_WIDTH__SHIFT) & A6XX_X3_BIN_SIZE_WIDTH__MASK;
return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
}
#define A6XX_X3_BIN_SIZE_HEIGHT__MASK 0x0001ff00
#define A6XX_X3_BIN_SIZE_HEIGHT__SHIFT 8
static inline uint32_t A6XX_X3_BIN_SIZE_HEIGHT(uint32_t val)
#define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x0001ff00
#define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8
static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
{
return ((val >> 4) << A6XX_X3_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X3_BIN_SIZE_HEIGHT__MASK;
return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
}
#define REG_A6XX_VSC_BIN_SIZE 0x00000c02
......@@ -2182,11 +2654,19 @@ static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
}
#define REG_A6XX_VSC_XXX_ADDRESS_LO 0x00000c30
#define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO 0x00000c30
#define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_HI 0x00000c31
#define REG_A6XX_VSC_XXX_ADDRESS_HI 0x00000c31
#define REG_A6XX_VSC_PIPE_DATA2_PITCH 0x00000c32
#define REG_A6XX_VSC_XXX_PITCH 0x00000c32
#define REG_A6XX_VSC_PIPE_DATA2_ARRAY_PITCH 0x00000c33
#define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK 0xffffffff
#define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT 0
static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val)
{
return ((val >> 4) << A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK;
}
#define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO 0x00000c34
......@@ -2194,18 +2674,29 @@ static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
#define REG_A6XX_VSC_PIPE_DATA_PITCH 0x00000c36
#define REG_A6XX_VSC_PIPE_DATA_ARRAY_PITCH 0x00000c37
#define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK 0xffffffff
#define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT 0
static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val)
{
return ((val >> 4) << A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK;
}
static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
#define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
#define REG_A6XX_GRAS_UNKNOWN_8000 0x00008000
#define REG_A6XX_GRAS_UNKNOWN_8001 0x00008001
#define REG_A6XX_GRAS_UNKNOWN_8004 0x00008004
#define REG_A6XX_GRAS_CNTL 0x00008005
#define A6XX_GRAS_CNTL_VARYING 0x00000001
#define A6XX_GRAS_CNTL_UNK3 0x00000008
#define A6XX_GRAS_CNTL_XCOORD 0x00000040
#define A6XX_GRAS_CNTL_YCOORD 0x00000080
#define A6XX_GRAS_CNTL_ZCOORD 0x00000100
......@@ -2308,6 +2799,9 @@ static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
}
#define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094
#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
#define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
......@@ -2344,6 +2838,8 @@ static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_dep
#define REG_A6XX_GRAS_UNKNOWN_809B 0x0000809b
#define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0
#define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
......@@ -2464,6 +2960,8 @@ static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
#define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
......@@ -2494,6 +2992,10 @@ static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
#define REG_A6XX_GRAS_UNKNOWN_8109 0x00008109
#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
......@@ -2590,6 +3092,33 @@ static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val)
#define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600
#define REG_A6XX_RB_BIN_CONTROL 0x00008800
#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x000000ff
#define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
{
return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
}
#define A6XX_RB_BIN_CONTROL_BINH__MASK 0x0001ff00
#define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8
static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
{
return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
}
#define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000
#define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000
#define REG_A6XX_RB_RENDER_CNTL 0x00008801
#define A6XX_RB_RENDER_CNTL_UNK4 0x00000010
#define A6XX_RB_RENDER_CNTL_BINNING 0x00000080
#define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
}
#define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
......@@ -2615,6 +3144,7 @@ static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
#define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
#define A6XX_RB_RENDER_CONTROL0_VARYING 0x00000001
#define A6XX_RB_RENDER_CONTROL0_UNK3 0x00000008
#define A6XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
#define A6XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
#define A6XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
......@@ -2747,6 +3277,10 @@ static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dithe
#define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
#define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
#define REG_A6XX_RB_UNKNOWN_8810 0x00008810
#define REG_A6XX_RB_UNKNOWN_8811 0x00008811
#define REG_A6XX_RB_UNKNOWN_8818 0x00008818
#define REG_A6XX_RB_UNKNOWN_8819 0x00008819
......@@ -2837,7 +3371,6 @@ static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
{
return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
}
#define A6XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
#define A6XX_RB_MRT_PITCH__MASK 0xffffffff
......@@ -2923,6 +3456,9 @@ static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
}
#define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870
#define A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
#define REG_A6XX_RB_DEPTH_CNTL 0x00008871
#define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
#define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
......@@ -3053,6 +3589,12 @@ static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
{
return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
}
#define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00
#define A6XX_RB_STENCILREF_BFREF__SHIFT 8
static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
{
return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
}
#define REG_A6XX_RB_STENCILMASK 0x00008888
#define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff
......@@ -3061,6 +3603,12 @@ static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
{
return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
}
#define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00
#define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8
static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
{
return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
}
#define REG_A6XX_RB_STENCILWRMASK 0x00008889
#define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff
......@@ -3069,6 +3617,12 @@ static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
{
return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
}
#define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00
#define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8
static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
{
return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
}
#define REG_A6XX_RB_WINDOW_OFFSET 0x00008890
#define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
......@@ -3177,14 +3731,14 @@ static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
#define REG_A6XX_RB_BLIT_INFO 0x000088e3
#define A6XX_RB_BLIT_INFO_UNK0 0x00000001
#define A6XX_RB_BLIT_INFO_FAST_CLEAR 0x00000002
#define A6XX_RB_BLIT_INFO_GMEM 0x00000002
#define A6XX_RB_BLIT_INFO_INTEGER 0x00000004
#define A6XX_RB_BLIT_INFO_UNK3 0x00000008
#define A6XX_RB_BLIT_INFO_MASK__MASK 0x000000f0
#define A6XX_RB_BLIT_INFO_MASK__SHIFT 4
static inline uint32_t A6XX_RB_BLIT_INFO_MASK(uint32_t val)
#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
{
return ((val) << A6XX_RB_BLIT_INFO_MASK__SHIFT) & A6XX_RB_BLIT_INFO_MASK__MASK;
return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
}
#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
......@@ -3274,12 +3828,16 @@ static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
#define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01
#define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04
#define REG_A6XX_RB_CCU_CNTL 0x00008e07
#define REG_A6XX_VPC_UNKNOWN_9101 0x00009101
#define REG_A6XX_VPC_GS_SIV_CNTL 0x00009104
#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
#define REG_A6XX_VPC_UNKNOWN_9108 0x00009108
static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
......@@ -3385,6 +3943,9 @@ static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
#define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
#define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
#define REG_A6XX_VPC_SO_OVERRIDE 0x00009306
#define A6XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
#define REG_A6XX_VPC_UNKNOWN_9600 0x00009600
#define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
......@@ -3397,8 +3958,14 @@ static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
#define REG_A6XX_PC_UNKNOWN_9805 0x00009805
#define REG_A6XX_PC_UNKNOWN_9806 0x00009806
#define REG_A6XX_PC_UNKNOWN_9980 0x00009980
#define REG_A6XX_PC_UNKNOWN_9981 0x00009981
#define REG_A6XX_PC_UNKNOWN_9990 0x00009990
#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
#define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
......@@ -3410,6 +3977,7 @@ static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val)
{
return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK;
}
#define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE 0x00000100
#define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06
......@@ -3488,6 +4056,8 @@ static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
#define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008
#define REG_A6XX_VFD_UNKNOWN_A009 0x0000a009
#define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
#define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
......@@ -3640,6 +4210,8 @@ static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
#define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b
#define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c
#define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d
......@@ -3884,6 +4456,8 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
#define REG_A6XX_SP_UNKNOWN_A982 0x0000a982
#define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983
#define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984
......@@ -3979,7 +4553,8 @@ static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val)
}
#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
#define A6XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
#define REG_A6XX_SP_UNKNOWN_A99E 0x0000a99e
#define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
......@@ -4066,14 +4641,20 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
#define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
#define REG_A6XX_SP_UNKNOWN_AB20 0x0000ab20
#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
#define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04
#define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f
#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
......@@ -4097,6 +4678,8 @@ static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples
#define REG_A6XX_SP_TP_UNKNOWN_B304 0x0000b304
#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
......@@ -4162,6 +4745,8 @@ static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
}
#define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980
#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
#define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
......@@ -4537,11 +5122,11 @@ static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
}
#define REG_A6XX_TEX_CONST_8 0x00000008
#define A6XX_TEX_CONST_8_BASE_HI__MASK 0x0001ffff
#define A6XX_TEX_CONST_8_BASE_HI__SHIFT 0
static inline uint32_t A6XX_TEX_CONST_8_BASE_HI(uint32_t val)
#define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff
#define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0
static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
{
return ((val) << A6XX_TEX_CONST_8_BASE_HI__SHIFT) & A6XX_TEX_CONST_8_BASE_HI__MASK;
return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
}
#define REG_A6XX_TEX_CONST_9 0x00000009
......@@ -4558,5 +5143,227 @@ static inline uint32_t A6XX_TEX_CONST_8_BASE_HI(uint32_t val)
#define REG_A6XX_TEX_CONST_15 0x0000000f
#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00
#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
}
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
}
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
}
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
}
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
}
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
{
return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
}
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
#endif /* A6XX_XML */
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
View file @ a69c5ed2
......@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
Copyright (C) 2013-2018 by the following authors:
......@@ -167,8 +167,8 @@ static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_
#define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000004
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000008
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040
......
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
View file @ a69c5ed2
......@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
Copyright (C) 2013-2018 by the following authors:
......
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
View file @ a69c5ed2
......@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
Copyright (C) 2013-2018 by the following authors:
......@@ -237,7 +237,7 @@ enum adreno_pm4_type3_packets {
CP_UNK_A6XX_14 = 20,
CP_UNK_A6XX_36 = 54,
CP_UNK_A6XX_55 = 85,
UNK_A6XX_6D = 109,
CP_REG_WRITE = 109,
};
enum adreno_state_block {
......@@ -968,19 +968,19 @@ static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
}
#define REG_CP_SET_BIN_DATA5_5 0x00000005
#define CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__MASK 0xffffffff
#define CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__SHIFT 0
static inline uint32_t CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO(uint32_t val)
#define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK 0xffffffff
#define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT 0
static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val)
{
return ((val) << CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__MASK;
return ((val) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK;
}
#define REG_CP_SET_BIN_DATA5_6 0x00000006
#define CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__MASK 0xffffffff
#define CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__SHIFT 0
static inline uint32_t CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI(uint32_t val)
#define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK 0xffffffff
#define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT 0
static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val)
{
return ((val) << CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__MASK;
return ((val) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK;
}
#define REG_CP_REG_TO_MEM_0 0x00000000
......
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