Commit a6e25b39 authored by Bhupesh Sharma's avatar Bhupesh Sharma Committed by Bjorn Helgaas

dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC

Document the PCIe DT bindings for SM8150 SoC. The PCIe IP is similar to
the one used on SM8250.

Link: https://lore.kernel.org/r/20220326060810.1797516-2-bhupesh.sharma@linaro.orgSigned-off-by: default avatarBhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
parent 31231092
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
- "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-qcs404" for qcs404
- "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sc8180x" for sc8180x
- "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sdm845" for sdm845
- "qcom,pcie-sm8150" for sm8150
- "qcom,pcie-sm8250" for sm8250 - "qcom,pcie-sm8250" for sm8250
- "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450
- "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450
...@@ -159,7 +160,7 @@ ...@@ -159,7 +160,7 @@
- "pipe" PIPE clock - "pipe" PIPE clock
- clock-names: - clock-names:
Usage: required for sc8180x and sm8250 Usage: required for sc8180x, sm8150 and sm8250
Value type: <stringlist> Value type: <stringlist>
Definition: Should contain the following entries Definition: Should contain the following entries
- "aux" Auxiliary clock - "aux" Auxiliary clock
...@@ -266,7 +267,7 @@ ...@@ -266,7 +267,7 @@
- "ahb" AHB reset - "ahb" AHB reset
- reset-names: - reset-names:
Usage: required for sc8180x, sdm845, sm8250 and sm8450 Usage: required for sc8180x, sdm845, sm8150, sm8250 and sm8450
Value type: <stringlist> Value type: <stringlist>
Definition: Should contain the following entries Definition: Should contain the following entries
- "pci" PCIe core reset - "pci" PCIe core reset
......
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