Commit a74801c5 authored by Yuval Mintz's avatar Yuval Mintz Committed by David S. Miller

bnx2x: Clear dirty status when booting after UNDI

Self-tests following boot from SAN have failed as the
UNDI driver might leave some NIG interrupt indications.

This patch does the clean-up, clearing those indications
and allowing the test to pass.
Signed-off-by: default avatarYuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: default avatarAriel Elior <ariele@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4b87f922
...@@ -9854,6 +9854,8 @@ static int bnx2x_prev_unload_common(struct bnx2x *bp) ...@@ -9854,6 +9854,8 @@ static int bnx2x_prev_unload_common(struct bnx2x *bp)
prev_undi = true; prev_undi = true;
/* clear the UNDI indication */ /* clear the UNDI indication */
REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
/* clear possible idle check errors */
REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
} }
} }
/* wait until BRB is empty */ /* wait until BRB is empty */
......
...@@ -2154,6 +2154,8 @@ ...@@ -2154,6 +2154,8 @@
/* [R 32] Interrupt register #0 read */ /* [R 32] Interrupt register #0 read */
#define NIG_REG_NIG_INT_STS_0 0x103b0 #define NIG_REG_NIG_INT_STS_0 0x103b0
#define NIG_REG_NIG_INT_STS_1 0x103c0 #define NIG_REG_NIG_INT_STS_1 0x103c0
/* [RC 32] Interrupt register #0 read clear */
#define NIG_REG_NIG_INT_STS_CLR_0 0x103b4
/* [R 32] Legacy E1 and E1H location for parity error mask register. */ /* [R 32] Legacy E1 and E1H location for parity error mask register. */
#define NIG_REG_NIG_PRTY_MASK 0x103dc #define NIG_REG_NIG_PRTY_MASK 0x103dc
/* [RW 32] Parity mask register #0 read/write */ /* [RW 32] Parity mask register #0 read/write */
......
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