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Commit a7705e54 authored by Jonathan Bergh's avatar Jonathan Bergh Committed by Greg Kroah-Hartman
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staging: vme_user: Fix various comment formatting issues including comment content 

Fixed various issues relating to comments including:
    * Lines with '*' in block comments which should be aligned and
      were not
    * Corrected comments where closing multiline comment identifier
      ran over into second newline spuriously
    * Corrected comment content to correctly reflect hexadecimal for
      the offsets rather than integers
Signed-off-by: default avatarJonathan Bergh <bergh.jonathan@gmail.com>
Link: https://lore.kernel.org/r/20230914200732.47659-1-bergh.jonathan@gmail.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c887e083
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Showing with 77 additions and 79 deletions
drivers/staging/vme_user/vme_tsi148.h
View file @ a7705e54
...@@ -206,7 +206,7 @@ static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1, ...@@ -206,7 +206,7 @@ static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1,
/* /*
* VMEbus interrupt ack * VMEbus interrupt ack
* offset 200 * offset 0x200
*/ */
#define TSI148_LCSR_VIACK1 0x204 #define TSI148_LCSR_VIACK1 0x204
#define TSI148_LCSR_VIACK2 0x208 #define TSI148_LCSR_VIACK2 0x208
...@@ -223,7 +223,7 @@ static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1, ...@@ -223,7 +223,7 @@ static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
/* /*
* RMW * RMW
* offset 220 * offset 0x220
*/ */
#define TSI148_LCSR_RMWAU 0x220 #define TSI148_LCSR_RMWAU 0x220
#define TSI148_LCSR_RMWAL 0x224 #define TSI148_LCSR_RMWAL 0x224
...@@ -233,7 +233,7 @@ static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1, ...@@ -233,7 +233,7 @@ static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
/* /*
* VMEbus control * VMEbus control
* offset 234 * offset 0x234
*/ */
#define TSI148_LCSR_VMCTRL 0x234 #define TSI148_LCSR_VMCTRL 0x234
#define TSI148_LCSR_VCTRL 0x238 #define TSI148_LCSR_VCTRL 0x238
...@@ -241,38 +241,38 @@ static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1, ...@@ -241,38 +241,38 @@ static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
/* /*
* PCI status * PCI status
* offset 240 * offset 0x240
*/ */
#define TSI148_LCSR_PSTAT 0x240 #define TSI148_LCSR_PSTAT 0x240
/* /*
* VME filter. * VME filter.
* offset 250 * offset 0x250
*/ */
#define TSI148_LCSR_VMEFL 0x250 #define TSI148_LCSR_VMEFL 0x250
/* /*
* VME exception. * VME exception.
* offset 260 * offset 0x260
*/ */
#define TSI148_LCSR_VEAU 0x260 #define TSI148_LCSR_VEAU 0x260
#define TSI148_LCSR_VEAL 0x264 #define TSI148_LCSR_VEAL 0x264
#define TSI148_LCSR_VEAT 0x268 #define TSI148_LCSR_VEAT 0x268
/* /*
* PCI error * PCI error
* offset 270 * offset 0x270
*/ */
#define TSI148_LCSR_EDPAU 0x270 #define TSI148_LCSR_EDPAU 0x270
#define TSI148_LCSR_EDPAL 0x274 #define TSI148_LCSR_EDPAL 0x274
#define TSI148_LCSR_EDPXA 0x278 #define TSI148_LCSR_EDPXA 0x278
#define TSI148_LCSR_EDPXS 0x27C #define TSI148_LCSR_EDPXS 0x27C
#define TSI148_LCSR_EDPAT 0x280 #define TSI148_LCSR_EDPAT 0x280
/* /*
* Inbound Translations * Inbound Translations
* offset 300 * offset 0x300
*/ */
#define TSI148_LCSR_IT0_ITSAU 0x300 #define TSI148_LCSR_IT0_ITSAU 0x300
#define TSI148_LCSR_IT0_ITSAL 0x304 #define TSI148_LCSR_IT0_ITSAL 0x304
#define TSI148_LCSR_IT0_ITEAU 0x308 #define TSI148_LCSR_IT0_ITEAU 0x308
...@@ -359,53 +359,53 @@ static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1, ...@@ -359,53 +359,53 @@ static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
#define TSI148_LCSR_OFFSET_ITOFL 0x14 #define TSI148_LCSR_OFFSET_ITOFL 0x14
#define TSI148_LCSR_OFFSET_ITAT 0x18 #define TSI148_LCSR_OFFSET_ITAT 0x18
/* /*
* Inbound Translation GCSR * Inbound Translation GCSR
* offset 400 * offset 0x400
*/ */
#define TSI148_LCSR_GBAU 0x400 #define TSI148_LCSR_GBAU 0x400
#define TSI148_LCSR_GBAL 0x404 #define TSI148_LCSR_GBAL 0x404
#define TSI148_LCSR_GCSRAT 0x408 #define TSI148_LCSR_GCSRAT 0x408
/* /*
* Inbound Translation CRG * Inbound Translation CRG
* offset 40C * offset 0x40C
*/ */
#define TSI148_LCSR_CBAU 0x40C #define TSI148_LCSR_CBAU 0x40C
#define TSI148_LCSR_CBAL 0x410 #define TSI148_LCSR_CBAL 0x410
#define TSI148_LCSR_CSRAT 0x414 #define TSI148_LCSR_CSRAT 0x414
/* /*
* Inbound Translation CR/CSR * Inbound Translation CR/CSR
* CRG * CRG
* offset 418 * offset 0x418
*/ */
#define TSI148_LCSR_CROU 0x418 #define TSI148_LCSR_CROU 0x418
#define TSI148_LCSR_CROL 0x41C #define TSI148_LCSR_CROL 0x41C
#define TSI148_LCSR_CRAT 0x420 #define TSI148_LCSR_CRAT 0x420
/* /*
* Inbound Translation Location Monitor * Inbound Translation Location Monitor
* offset 424 * offset 0x424
*/ */
#define TSI148_LCSR_LMBAU 0x424 #define TSI148_LCSR_LMBAU 0x424
#define TSI148_LCSR_LMBAL 0x428 #define TSI148_LCSR_LMBAL 0x428
#define TSI148_LCSR_LMAT 0x42C #define TSI148_LCSR_LMAT 0x42C
/* /*
* VMEbus Interrupt Control. * VMEbus Interrupt Control.
* offset 430 * offset 0x430
*/ */
#define TSI148_LCSR_BCU 0x430 #define TSI148_LCSR_BCU 0x430
#define TSI148_LCSR_BCL 0x434 #define TSI148_LCSR_BCL 0x434
#define TSI148_LCSR_BPGTR 0x438 #define TSI148_LCSR_BPGTR 0x438
#define TSI148_LCSR_BPCTR 0x43C #define TSI148_LCSR_BPCTR 0x43C
#define TSI148_LCSR_VICR 0x440 #define TSI148_LCSR_VICR 0x440
/* /*
* Local Bus Interrupt Control. * Local Bus Interrupt Control.
* offset 448 * offset 0x448
*/ */
#define TSI148_LCSR_INTEN 0x448 #define TSI148_LCSR_INTEN 0x448
#define TSI148_LCSR_INTEO 0x44C #define TSI148_LCSR_INTEO 0x44C
#define TSI148_LCSR_INTS 0x450 #define TSI148_LCSR_INTS 0x450
...@@ -413,10 +413,10 @@ static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1, ...@@ -413,10 +413,10 @@ static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
#define TSI148_LCSR_INTM1 0x458 #define TSI148_LCSR_INTM1 0x458
#define TSI148_LCSR_INTM2 0x45C #define TSI148_LCSR_INTM2 0x45C
/* /*
* DMA Controllers * DMA Controllers
* offset 500 * offset 0x500
*/ */
#define TSI148_LCSR_DCTL0 0x500 #define TSI148_LCSR_DCTL0 0x500
#define TSI148_LCSR_DSTA0 0x504 #define TSI148_LCSR_DSTA0 0x504
#define TSI148_LCSR_DCSAU0 0x508 #define TSI148_LCSR_DCSAU0 0x508
...@@ -480,27 +480,27 @@ static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0, ...@@ -480,27 +480,27 @@ static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0,
#define TSI148_LCSR_OFFSET_DCNT 0x40 #define TSI148_LCSR_OFFSET_DCNT 0x40
#define TSI148_LCSR_OFFSET_DDBS 0x44 #define TSI148_LCSR_OFFSET_DDBS 0x44
/* /*
* GCSR Register Group * GCSR Register Group
*/ */
/* /*
* GCSR CRG * GCSR CRG
* offset 00 600 - DEVI/VENI * offset 0x00 0x600 - DEVI/VENI
* offset 04 604 - CTRL/GA/REVID * offset 0x04 0x604 - CTRL/GA/REVID
* offset 08 608 - Semaphore3/2/1/0 * offset 0x08 0x608 - Semaphore3/2/1/0
* offset 0C 60C - Seamphore7/6/5/4 * offset 0x0C 0x60C - Seamphore7/6/5/4
*/ */
#define TSI148_GCSR_ID 0x600 #define TSI148_GCSR_ID 0x600
#define TSI148_GCSR_CSR 0x604 #define TSI148_GCSR_CSR 0x604
#define TSI148_GCSR_SEMA0 0x608 #define TSI148_GCSR_SEMA0 0x608
#define TSI148_GCSR_SEMA1 0x60C #define TSI148_GCSR_SEMA1 0x60C
/* /*
* Mail Box * Mail Box
* GCSR CRG * GCSR CRG
* offset 10 610 - Mailbox0 * offset 0x10 0x610 - Mailbox0
*/ */
#define TSI148_GCSR_MBOX0 0x610 #define TSI148_GCSR_MBOX0 0x610
#define TSI148_GCSR_MBOX1 0x614 #define TSI148_GCSR_MBOX1 0x614
#define TSI148_GCSR_MBOX2 0x618 #define TSI148_GCSR_MBOX2 0x618
...@@ -511,27 +511,27 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0, ...@@ -511,27 +511,27 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
TSI148_GCSR_MBOX2, TSI148_GCSR_MBOX2,
TSI148_GCSR_MBOX3 }; TSI148_GCSR_MBOX3 };
/* /*
* CR/CSR * CR/CSR
*/ */
/* /*
* CR/CSR CRG * CR/CSR CRG
* offset 7FFF4 FF4 - CSRBCR * offset 0x7FFF4 0xFF4 - CSRBCR
* offset 7FFF8 FF8 - CSRBSR * offset 0x7FFF8 0xFF8 - CSRBSR
* offset 7FFFC FFC - CBAR * offset 0x7FFFC 0xFFC - CBAR
*/ */
#define TSI148_CSRBCR 0xFF4 #define TSI148_CSRBCR 0xFF4
#define TSI148_CSRBSR 0xFF8 #define TSI148_CSRBSR 0xFF8
#define TSI148_CBAR 0xFFC #define TSI148_CBAR 0xFFC
/* /*
* TSI148 Register Bit Definitions * TSI148 Register Bit Definitions
*/ */
/* /*
* PFCS Register Set * PFCS Register Set
*/ */
#define TSI148_PCFS_CMMD_SERR BIT(8) /* SERR_L out pin ssys err */ #define TSI148_PCFS_CMMD_SERR BIT(8) /* SERR_L out pin ssys err */
#define TSI148_PCFS_CMMD_PERR BIT(6) /* PERR_L out pin parity */ #define TSI148_PCFS_CMMD_PERR BIT(6) /* PERR_L out pin parity */
#define TSI148_PCFS_CMMD_MSTR BIT(2) /* PCI bus master */ #define TSI148_PCFS_CMMD_MSTR BIT(2) /* PCI bus master */
...@@ -603,8 +603,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0, ...@@ -603,8 +603,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
*/ */
#define TSI148_PCFS_PCIXSTAT_RSCEM BIT(29) /* Received Split Comp Error */ #define TSI148_PCFS_PCIXSTAT_RSCEM BIT(29) /* Received Split Comp Error */
#define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */ #define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */
#define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans #define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans */
*/
#define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */ #define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */
#define TSI148_PCFS_PCIXSTAT_DC BIT(20) /* Device Complexity */ #define TSI148_PCFS_PCIXSTAT_DC BIT(20) /* Device Complexity */
#define TSI148_PCFS_PCIXSTAT_USC BIT(19) /* Unexpected Split comp */ #define TSI148_PCFS_PCIXSTAT_USC BIT(19) /* Unexpected Split comp */
...@@ -766,8 +765,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0, ...@@ -766,8 +765,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
#define TSI148_LCSR_VCTRL_ATOEN BIT(7) /* Arbiter Time-out Enable */ #define TSI148_LCSR_VCTRL_ATOEN BIT(7) /* Arbiter Time-out Enable */
#define TSI148_LCSR_VCTRL_ROBIN BIT(6) /* VMEbus Round Robin */ #define TSI148_LCSR_VCTRL_ROBIN BIT(6) /* VMEbus Round Robin */
#define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask #define TSI148_LCSR_VCTRL_GTO_M (7<<0) /* VMEbus Global Time-out Mask*/
*/
#define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */ #define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */
#define TSI148_LCSR_VCTRL_GTO_16 BIT(0) /* 16 us */ #define TSI148_LCSR_VCTRL_GTO_16 BIT(0) /* 16 us */
#define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */ #define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */
......
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