Commit a8209dd4 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Vinod Koul

soundwire: sdw.h: fix PRBS/Static_1 swapped definitions

Table 110 "Port Data Modes" of the SoundWire 1.2 specification lists
PRBS as b01 and Static_1 as b11. The existing headers swapped the two
values, fix.
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarGuennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@linux.intel.com>
Signed-off-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20200714213744.24674-2-yung-chuan.liao@linux.intel.comSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 9cb834b1
...@@ -152,19 +152,19 @@ enum sdw_data_direction { ...@@ -152,19 +152,19 @@ enum sdw_data_direction {
* *
* @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
* and transmitted. * and transmitted.
* @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
* a pseudo random data pattern that is transferred
* @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
* logic 0. The encoding will result in no signal transitions
* @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of
* logic 1. The encoding will result in signal transitions at every bitslot * logic 1. The encoding will result in signal transitions at every bitslot
* owned by this Port * owned by this Port
* @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
* logic 0. The encoding will result in no signal transitions
* @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
* a pseudo random data pattern that is transferred
*/ */
enum sdw_port_data_mode { enum sdw_port_data_mode {
SDW_PORT_DATA_MODE_NORMAL = 0, SDW_PORT_DATA_MODE_NORMAL = 0,
SDW_PORT_DATA_MODE_STATIC_1 = 1, SDW_PORT_DATA_MODE_PRBS = 1,
SDW_PORT_DATA_MODE_STATIC_0 = 2, SDW_PORT_DATA_MODE_STATIC_0 = 2,
SDW_PORT_DATA_MODE_PRBS = 3, SDW_PORT_DATA_MODE_STATIC_1 = 3,
}; };
/* /*
......
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