Commit a89534ed authored by Woody Hung's avatar Woody Hung Committed by John W. Linville

rt2x00 : RT3290 chip support v4

This patch support the new chipset rt3290 wifi implementation in rt2x00.
It initailize the related mac, bbp and rf register in startup phase.
And this patch modify the efuse read/write method for the different efuse data offset of rt3290.
Signed-off-by: default avatarWoody Hung <Woody.Hung@mediatek.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 324640e3
......@@ -99,6 +99,14 @@ config RT2800PCI_RT53XX
rt2800pci driver.
Supported chips: RT5390
config RT2800PCI_RT3290
bool "rt2800pci - Include support for rt3290 devices (EXPERIMENTAL)"
depends on EXPERIMENTAL
default y
---help---
This adds support for rt3290 wireless chipset family to the
rt2800pci driver.
Supported chips: RT3290
endif
config RT2500USB
......
......@@ -68,6 +68,7 @@
#define RF3320 0x000b
#define RF3322 0x000c
#define RF3053 0x000d
#define RF3290 0x3290
#define RF5360 0x5360
#define RF5370 0x5370
#define RF5372 0x5372
......@@ -117,6 +118,12 @@
* Registers.
*/
/*
* MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
*/
#define MAC_CSR0_3290 0x0000
/*
* E2PROM_CSR: PCI EEPROM control register.
* RELOAD: Write 1 to reload eeprom content.
......@@ -132,6 +139,150 @@
#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
/*
* CMB_CTRL_CFG
*/
#define CMB_CTRL 0x0020
#define AUX_OPT_BIT0 FIELD32(0x00000001)
#define AUX_OPT_BIT1 FIELD32(0x00000002)
#define AUX_OPT_BIT2 FIELD32(0x00000004)
#define AUX_OPT_BIT3 FIELD32(0x00000008)
#define AUX_OPT_BIT4 FIELD32(0x00000010)
#define AUX_OPT_BIT5 FIELD32(0x00000020)
#define AUX_OPT_BIT6 FIELD32(0x00000040)
#define AUX_OPT_BIT7 FIELD32(0x00000080)
#define AUX_OPT_BIT8 FIELD32(0x00000100)
#define AUX_OPT_BIT9 FIELD32(0x00000200)
#define AUX_OPT_BIT10 FIELD32(0x00000400)
#define AUX_OPT_BIT11 FIELD32(0x00000800)
#define AUX_OPT_BIT12 FIELD32(0x00001000)
#define AUX_OPT_BIT13 FIELD32(0x00002000)
#define AUX_OPT_BIT14 FIELD32(0x00004000)
#define AUX_OPT_BIT15 FIELD32(0x00008000)
#define LDO25_LEVEL FIELD32(0x00030000)
#define LDO25_LARGEA FIELD32(0x00040000)
#define LDO25_FRC_ON FIELD32(0x00080000)
#define CMB_RSV FIELD32(0x00300000)
#define XTAL_RDY FIELD32(0x00400000)
#define PLL_LD FIELD32(0x00800000)
#define LDO_CORE_LEVEL FIELD32(0x0F000000)
#define LDO_BGSEL FIELD32(0x30000000)
#define LDO3_EN FIELD32(0x40000000)
#define LDO0_EN FIELD32(0x80000000)
/*
* EFUSE_CSR_3290: RT3290 EEPROM
*/
#define EFUSE_CTRL_3290 0x0024
/*
* EFUSE_DATA3 of 3290
*/
#define EFUSE_DATA3_3290 0x0028
/*
* EFUSE_DATA2 of 3290
*/
#define EFUSE_DATA2_3290 0x002c
/*
* EFUSE_DATA1 of 3290
*/
#define EFUSE_DATA1_3290 0x0030
/*
* EFUSE_DATA0 of 3290
*/
#define EFUSE_DATA0_3290 0x0034
/*
* OSC_CTRL_CFG
* Ring oscillator configuration
*/
#define OSC_CTRL 0x0038
#define OSC_REF_CYCLE FIELD32(0x00001fff)
#define OSC_RSV FIELD32(0x0000e000)
#define OSC_CAL_CNT FIELD32(0x0fff0000)
#define OSC_CAL_ACK FIELD32(0x10000000)
#define OSC_CLK_32K_VLD FIELD32(0x20000000)
#define OSC_CAL_REQ FIELD32(0x40000000)
#define OSC_ROSC_EN FIELD32(0x80000000)
/*
* COEX_CFG_0
*/
#define COEX_CFG0 0x0040
#define COEX_CFG_ANT FIELD32(0xff000000)
/*
* COEX_CFG_1
*/
#define COEX_CFG1 0x0044
/*
* COEX_CFG_2
*/
#define COEX_CFG2 0x0048
#define BT_COEX_CFG1 FIELD32(0xff000000)
#define BT_COEX_CFG0 FIELD32(0x00ff0000)
#define WL_COEX_CFG1 FIELD32(0x0000ff00)
#define WL_COEX_CFG0 FIELD32(0x000000ff)
/*
* PLL_CTRL_CFG
* PLL configuration register
*/
#define PLL_CTRL 0x0050
#define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
#define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
#define PLL_CONTROL FIELD32(0x00070000)
#define PLL_LPF_R1 FIELD32(0x00080000)
#define PLL_LPF_C1_CTRL FIELD32(0x00300000)
#define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
#define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
#define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
#define PLL_LOCK_CTRL FIELD32(0x70000000)
#define PLL_VBGBK_EN FIELD32(0x80000000)
/*
* WLAN_CTRL_CFG
* RT3290 wlan configuration
*/
#define WLAN_FUN_CTRL 0x0080
#define WLAN_EN FIELD32(0x00000001)
#define WLAN_CLK_EN FIELD32(0x00000002)
#define WLAN_RSV1 FIELD32(0x00000004)
#define WLAN_RESET FIELD32(0x00000008)
#define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
#define FRC_WL_ANT_SET FIELD32(0x00000020)
#define INV_TR_SW0 FIELD32(0x00000040)
#define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
#define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
#define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
#define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
#define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
#define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
#define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
#define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
#define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
#define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
#define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
#define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
#define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
#define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
#define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
#define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
#define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
#define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
#define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
#define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
#define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
#define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
#define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
#define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
#define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
#define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
#define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
/*
* AUX_CTRL: Aux/PCI-E related configuration
*/
......@@ -1766,6 +1917,8 @@ struct mac_iveiv_entry {
#define BBP3_RX_ADC FIELD8(0x03)
#define BBP3_RX_ANTENNA FIELD8(0x18)
#define BBP3_HT40_MINUS FIELD8(0x20)
#define BBP3_ADC_MODE_SWITCH FIELD8(0x40)
#define BBP3_ADC_INIT_MODE FIELD8(0x80)
/*
* BBP 4: Bandwidth
......@@ -1774,6 +1927,14 @@ struct mac_iveiv_entry {
#define BBP4_BANDWIDTH FIELD8(0x18)
#define BBP4_MAC_IF_CTRL FIELD8(0x40)
/*
* BBP 47: Bandwidth
*/
#define BBP47_TSSI_REPORT_SEL FIELD8(0x03)
#define BBP47_TSSI_UPDATE_REQ FIELD8(0x04)
#define BBP47_TSSI_TSSI_MODE FIELD8(0x18)
#define BBP47_TSSI_ADC6 FIELD8(0x80)
/*
* BBP 109
*/
......@@ -1916,6 +2077,16 @@ struct mac_iveiv_entry {
#define RFCSR27_R3 FIELD8(0x30)
#define RFCSR27_R4 FIELD8(0x40)
/*
* RFCSR 29:
*/
#define RFCSR29_ADC6_TEST FIELD8(0x01)
#define RFCSR29_ADC6_INT_TEST FIELD8(0x02)
#define RFCSR29_RSSI_RESET FIELD8(0x04)
#define RFCSR29_RSSI_ON FIELD8(0x08)
#define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30)
#define RFCSR29_RSSI_GAIN FIELD8(0xc0)
/*
* RFCSR 30:
*/
......
This diff is collapsed.
......@@ -280,6 +280,12 @@ static void rt2800pci_stop_queue(struct data_queue *queue)
*/
static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
{
/*
* Chip rt3290 use specific 4KB firmware named rt3290.bin.
*/
if (rt2x00_rt(rt2x00dev, RT3290))
return FIRMWARE_RT3290;
else
return FIRMWARE_RT2860;
}
......@@ -974,6 +980,66 @@ static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
return rt2800_validate_eeprom(rt2x00dev);
}
static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
int i, count;
rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
if ((rt2x00_get_field32(reg, WLAN_EN) == 1))
return 0;
rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
rt2x00_set_field32(&reg, WLAN_EN, 1);
rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
udelay(REGISTER_BUSY_DELAY);
count = 0;
do {
/*
* Check PLL_LD & XTAL_RDY.
*/
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
if ((rt2x00_get_field32(reg, PLL_LD) == 1) &&
(rt2x00_get_field32(reg, XTAL_RDY) == 1))
break;
udelay(REGISTER_BUSY_DELAY);
}
if (i >= REGISTER_BUSY_COUNT) {
if (count >= 10)
return -EIO;
rt2800_register_write(rt2x00dev, 0x58, 0x018);
udelay(REGISTER_BUSY_DELAY);
rt2800_register_write(rt2x00dev, 0x58, 0x418);
udelay(REGISTER_BUSY_DELAY);
rt2800_register_write(rt2x00dev, 0x58, 0x618);
udelay(REGISTER_BUSY_DELAY);
count++;
} else {
count = 0;
}
rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
rt2x00_set_field32(&reg, WLAN_RESET, 1);
rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
udelay(10);
rt2x00_set_field32(&reg, WLAN_RESET, 0);
rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
udelay(10);
rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
} while (count != 0);
return 0;
}
static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
{
int retval;
......@@ -996,6 +1062,17 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
if (retval)
return retval;
/*
* In probe phase call rt2800_enable_wlan_rt3290 to enable wlan
* clk for rt3290. That avoid the MCU fail in start phase.
*/
if (rt2x00_rt(rt2x00dev, RT3290)) {
retval = rt2800_enable_wlan_rt3290(rt2x00dev);
if (retval)
return retval;
}
/*
* This device has multiple filters for control frames
* and has a separate filter for PS Poll frames.
......@@ -1175,6 +1252,9 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
{ PCI_DEVICE(0x1432, 0x7768) },
{ PCI_DEVICE(0x1462, 0x891a) },
{ PCI_DEVICE(0x1a3b, 0x1059) },
#ifdef CONFIG_RT2800PCI_RT3290
{ PCI_DEVICE(0x1814, 0x3290) },
#endif
#ifdef CONFIG_RT2800PCI_RT33XX
{ PCI_DEVICE(0x1814, 0x3390) },
#endif
......
......@@ -47,6 +47,7 @@
* 8051 firmware image.
*/
#define FIRMWARE_RT2860 "rt2860.bin"
#define FIRMWARE_RT3290 "rt3290.bin"
#define FIRMWARE_IMAGE_BASE 0x2000
/*
......
......@@ -187,6 +187,7 @@ struct rt2x00_chip {
#define RT3070 0x3070
#define RT3071 0x3071
#define RT3090 0x3090 /* 2.4GHz PCIe */
#define RT3290 0x3290
#define RT3390 0x3390
#define RT3572 0x3572
#define RT3593 0x3593
......
......@@ -256,6 +256,7 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct rt2x00_ops *ops)
struct ieee80211_hw *hw;
struct rt2x00_dev *rt2x00dev;
int retval;
u16 chip;
retval = pci_enable_device(pci_dev);
if (retval) {
......@@ -305,6 +306,14 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct rt2x00_ops *ops)
if (retval)
goto exit_free_device;
/*
* Because rt3290 chip use different efuse offset to read efuse data.
* So before read efuse it need to indicate it is the
* rt3290 or not.
*/
pci_read_config_word(pci_dev, PCI_DEVICE_ID, &chip);
rt2x00dev->chip.rt = chip;
retval = rt2x00lib_probe_dev(rt2x00dev);
if (retval)
goto exit_free_reg;
......
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