Commit a8e2e0d7 authored by José Roberto de Souza's avatar José Roberto de Souza Committed by Rodrigo Vivi

drm/xe: Remove devcoredump readout of IPEIR

This register don't exist in gfx12+, so here dropping the readout
and print in devcoredump.
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent d32c49e3
...@@ -31,12 +31,10 @@ ...@@ -31,12 +31,10 @@
#define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c) #define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c)
#define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60) #define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60)
#define RING_IPEIR(base) XE_REG((base) + 0x64)
#define RING_IPEHR(base) XE_REG((base) + 0x68) #define RING_IPEHR(base) XE_REG((base) + 0x68)
#define RING_ACTHD(base) XE_REG((base) + 0x74) #define RING_ACTHD(base) XE_REG((base) + 0x74)
#define RING_DMA_FADD(base) XE_REG((base) + 0x78) #define RING_DMA_FADD(base) XE_REG((base) + 0x78)
#define RING_HWS_PGA(base) XE_REG((base) + 0x80) #define RING_HWS_PGA(base) XE_REG((base) + 0x80)
#define IPEIR(base) XE_REG((base) + 0x88)
#define RING_HWSTAM(base) XE_REG((base) + 0x98) #define RING_HWSTAM(base) XE_REG((base) + 0x98)
#define RING_MI_MODE(base) XE_REG((base) + 0x9c) #define RING_MI_MODE(base) XE_REG((base) + 0x9c)
#define RING_NOPID(base) XE_REG((base) + 0x94) #define RING_NOPID(base) XE_REG((base) + 0x94)
......
...@@ -727,7 +727,6 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe) ...@@ -727,7 +727,6 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe)
hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)); hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0));
snapshot->reg.ring_dma_fadd = snapshot->reg.ring_dma_fadd =
hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)); hw_engine_mmio_read32(hwe, RING_DMA_FADD(0));
snapshot->reg.ipeir = hw_engine_mmio_read32(hwe, IPEIR(0));
snapshot->reg.ipehr = hw_engine_mmio_read32(hwe, RING_IPEHR(0)); snapshot->reg.ipehr = hw_engine_mmio_read32(hwe, RING_IPEHR(0));
if (snapshot->class == XE_ENGINE_CLASS_COMPUTE) if (snapshot->class == XE_ENGINE_CLASS_COMPUTE)
...@@ -784,7 +783,6 @@ void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot, ...@@ -784,7 +783,6 @@ void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot,
drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n", drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
snapshot->reg.ring_dma_fadd_udw, snapshot->reg.ring_dma_fadd_udw,
snapshot->reg.ring_dma_fadd); snapshot->reg.ring_dma_fadd);
drm_printf(p, "\tIPEIR: 0x%08x\n", snapshot->reg.ipeir);
drm_printf(p, "\tIPEHR: 0x%08x\n\n", snapshot->reg.ipehr); drm_printf(p, "\tIPEHR: 0x%08x\n\n", snapshot->reg.ipehr);
if (snapshot->class == XE_ENGINE_CLASS_COMPUTE) if (snapshot->class == XE_ENGINE_CLASS_COMPUTE)
drm_printf(p, "\tRCU_MODE: 0x%08x\n", drm_printf(p, "\tRCU_MODE: 0x%08x\n",
......
...@@ -217,8 +217,6 @@ struct xe_hw_engine_snapshot { ...@@ -217,8 +217,6 @@ struct xe_hw_engine_snapshot {
u32 ring_dma_fadd_udw; u32 ring_dma_fadd_udw;
/** @ring_dma_fadd: RING_DMA_FADD */ /** @ring_dma_fadd: RING_DMA_FADD */
u32 ring_dma_fadd; u32 ring_dma_fadd;
/** @ipeir: IPEIR */
u32 ipeir;
/** @ipehr: IPEHR */ /** @ipehr: IPEHR */
u32 ipehr; u32 ipehr;
/** @rcu_mode: RCU_MODE */ /** @rcu_mode: RCU_MODE */
......
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