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Commit a8f8b489 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nv50/disp: preparation for storing static class data 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 70a3e647
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Showing with 181 additions and 121 deletions
drivers/gpu/drm/nouveau/core/engine/device/nv04.c
View file @ a8f8b489
...@@ -60,7 +60,7 @@ nv04_identify(struct nouveau_device *device) ...@@ -60,7 +60,7 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x05: case 0x05:
device->cname = "NV05"; device->cname = "NV05";
...@@ -78,7 +78,7 @@ nv04_identify(struct nouveau_device *device) ...@@ -78,7 +78,7 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
default: default:
nv_fatal(device, "unknown RIVA chipset\n"); nv_fatal(device, "unknown RIVA chipset\n");
......
drivers/gpu/drm/nouveau/core/engine/device/nv10.c
View file @ a8f8b489
...@@ -60,7 +60,7 @@ nv10_identify(struct nouveau_device *device) ...@@ -60,7 +60,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x15: case 0x15:
device->cname = "NV15"; device->cname = "NV15";
...@@ -79,7 +79,7 @@ nv10_identify(struct nouveau_device *device) ...@@ -79,7 +79,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x16: case 0x16:
device->cname = "NV16"; device->cname = "NV16";
...@@ -98,7 +98,7 @@ nv10_identify(struct nouveau_device *device) ...@@ -98,7 +98,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x1a: case 0x1a:
device->cname = "nForce"; device->cname = "nForce";
...@@ -117,7 +117,7 @@ nv10_identify(struct nouveau_device *device) ...@@ -117,7 +117,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x11: case 0x11:
device->cname = "NV11"; device->cname = "NV11";
...@@ -136,7 +136,7 @@ nv10_identify(struct nouveau_device *device) ...@@ -136,7 +136,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x17: case 0x17:
device->cname = "NV17"; device->cname = "NV17";
...@@ -155,7 +155,7 @@ nv10_identify(struct nouveau_device *device) ...@@ -155,7 +155,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x1f: case 0x1f:
device->cname = "nForce2"; device->cname = "nForce2";
...@@ -174,7 +174,7 @@ nv10_identify(struct nouveau_device *device) ...@@ -174,7 +174,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x18: case 0x18:
device->cname = "NV18"; device->cname = "NV18";
...@@ -193,7 +193,7 @@ nv10_identify(struct nouveau_device *device) ...@@ -193,7 +193,7 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
default: default:
nv_fatal(device, "unknown Celsius chipset\n"); nv_fatal(device, "unknown Celsius chipset\n");
......
drivers/gpu/drm/nouveau/core/engine/device/nv20.c
View file @ a8f8b489
...@@ -63,7 +63,7 @@ nv20_identify(struct nouveau_device *device) ...@@ -63,7 +63,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x25: case 0x25:
device->cname = "NV25"; device->cname = "NV25";
...@@ -82,7 +82,7 @@ nv20_identify(struct nouveau_device *device) ...@@ -82,7 +82,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x28: case 0x28:
device->cname = "NV28"; device->cname = "NV28";
...@@ -101,7 +101,7 @@ nv20_identify(struct nouveau_device *device) ...@@ -101,7 +101,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x2a: case 0x2a:
device->cname = "NV2A"; device->cname = "NV2A";
...@@ -120,7 +120,7 @@ nv20_identify(struct nouveau_device *device) ...@@ -120,7 +120,7 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
default: default:
nv_fatal(device, "unknown Kelvin chipset\n"); nv_fatal(device, "unknown Kelvin chipset\n");
......
drivers/gpu/drm/nouveau/core/engine/device/nv30.c
View file @ a8f8b489
...@@ -63,7 +63,7 @@ nv30_identify(struct nouveau_device *device) ...@@ -63,7 +63,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x35: case 0x35:
device->cname = "NV35"; device->cname = "NV35";
...@@ -82,7 +82,7 @@ nv30_identify(struct nouveau_device *device) ...@@ -82,7 +82,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x31: case 0x31:
device->cname = "NV31"; device->cname = "NV31";
...@@ -102,7 +102,7 @@ nv30_identify(struct nouveau_device *device) ...@@ -102,7 +102,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x36: case 0x36:
device->cname = "NV36"; device->cname = "NV36";
...@@ -122,7 +122,7 @@ nv30_identify(struct nouveau_device *device) ...@@ -122,7 +122,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
case 0x34: case 0x34:
device->cname = "NV34"; device->cname = "NV34";
...@@ -142,7 +142,7 @@ nv30_identify(struct nouveau_device *device) ...@@ -142,7 +142,7 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break; break;
default: default:
nv_fatal(device, "unknown Rankine chipset\n"); nv_fatal(device, "unknown Rankine chipset\n");
......
drivers/gpu/drm/nouveau/core/engine/device/nv40.c
View file @ a8f8b489
...@@ -70,7 +70,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -70,7 +70,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x41: case 0x41:
...@@ -93,7 +93,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -93,7 +93,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x42: case 0x42:
...@@ -116,7 +116,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -116,7 +116,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x43: case 0x43:
...@@ -139,7 +139,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -139,7 +139,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x45: case 0x45:
...@@ -162,7 +162,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -162,7 +162,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x47: case 0x47:
...@@ -185,7 +185,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -185,7 +185,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x49: case 0x49:
...@@ -208,7 +208,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -208,7 +208,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x4b: case 0x4b:
...@@ -231,7 +231,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -231,7 +231,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x44: case 0x44:
...@@ -254,7 +254,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -254,7 +254,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x46: case 0x46:
...@@ -277,7 +277,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -277,7 +277,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x4a: case 0x4a:
...@@ -300,7 +300,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -300,7 +300,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x4c: case 0x4c:
...@@ -323,7 +323,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -323,7 +323,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x4e: case 0x4e:
...@@ -346,7 +346,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -346,7 +346,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x63: case 0x63:
...@@ -369,7 +369,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -369,7 +369,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x67: case 0x67:
...@@ -392,7 +392,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -392,7 +392,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
case 0x68: case 0x68:
...@@ -415,7 +415,7 @@ nv40_identify(struct nouveau_device *device) ...@@ -415,7 +415,7 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break; break;
default: default:
......
drivers/gpu/drm/nouveau/core/engine/device/nv50.c
View file @ a8f8b489
...@@ -79,7 +79,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -79,7 +79,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass;
break; break;
case 0x84: case 0x84:
...@@ -107,7 +107,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -107,7 +107,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break; break;
case 0x86: case 0x86:
...@@ -135,7 +135,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -135,7 +135,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break; break;
case 0x92: case 0x92:
...@@ -163,7 +163,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -163,7 +163,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break; break;
case 0x94: case 0x94:
...@@ -191,7 +191,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -191,7 +191,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break; break;
case 0x96: case 0x96:
...@@ -219,7 +219,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -219,7 +219,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break; break;
case 0x98: case 0x98:
...@@ -247,7 +247,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -247,7 +247,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break; break;
case 0xa0: case 0xa0:
...@@ -275,7 +275,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -275,7 +275,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva0_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break; break;
case 0xaa: case 0xaa:
...@@ -303,7 +303,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -303,7 +303,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break; break;
case 0xac: case 0xac:
...@@ -331,7 +331,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -331,7 +331,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break; break;
case 0xa3: case 0xa3:
...@@ -361,7 +361,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -361,7 +361,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break; break;
case 0xa5: case 0xa5:
...@@ -390,7 +390,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -390,7 +390,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break; break;
case 0xa8: case 0xa8:
...@@ -419,7 +419,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -419,7 +419,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break; break;
case 0xaf: case 0xaf:
...@@ -448,7 +448,7 @@ nv50_identify(struct nouveau_device *device) ...@@ -448,7 +448,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break; break;
default: default:
......
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
View file @ a8f8b489
...@@ -86,7 +86,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -86,7 +86,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break; break;
case 0xc4: case 0xc4:
...@@ -118,7 +118,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -118,7 +118,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break; break;
case 0xc3: case 0xc3:
...@@ -149,7 +149,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -149,7 +149,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break; break;
case 0xce: case 0xce:
...@@ -181,7 +181,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -181,7 +181,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break; break;
case 0xcf: case 0xcf:
...@@ -213,7 +213,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -213,7 +213,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break; break;
case 0xc1: case 0xc1:
...@@ -244,7 +244,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -244,7 +244,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break; break;
case 0xc8: case 0xc8:
...@@ -276,7 +276,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -276,7 +276,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break; break;
case 0xd9: case 0xd9:
...@@ -307,7 +307,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -307,7 +307,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break; break;
case 0xd7: case 0xd7:
...@@ -336,7 +336,7 @@ nvc0_identify(struct nouveau_device *device) ...@@ -336,7 +336,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break; break;
default: default:
......
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
View file @ a8f8b489
...@@ -81,7 +81,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -81,7 +81,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
...@@ -114,7 +114,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -114,7 +114,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
...@@ -147,7 +147,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -147,7 +147,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
...@@ -180,7 +180,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -180,7 +180,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
...@@ -215,7 +215,7 @@ nve0_identify(struct nouveau_device *device) ...@@ -215,7 +215,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
......
drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
View file @ a8f8b489
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include <engine/disp.h> #include "priv.h"
#include <core/event.h> #include <core/event.h>
#include <core/class.h> #include <core/class.h>
...@@ -138,13 +138,13 @@ nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -138,13 +138,13 @@ nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nouveau_oclass *
nv04_disp_oclass = { nv04_disp_oclass = &(struct nouveau_disp_impl) {
.handle = NV_ENGINE(DISP, 0x04), .base.handle = NV_ENGINE(DISP, 0x04),
.ofuncs = &(struct nouveau_ofuncs) { .base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_disp_ctor, .ctor = nv04_disp_ctor,
.dtor = _nouveau_disp_dtor, .dtor = _nouveau_disp_dtor,
.init = _nouveau_disp_init, .init = _nouveau_disp_init,
.fini = _nouveau_disp_fini, .fini = _nouveau_disp_fini,
}, },
}; }.base;
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
View file @ a8f8b489
...@@ -27,8 +27,6 @@ ...@@ -27,8 +27,6 @@
#include <core/handle.h> #include <core/handle.h>
#include <core/class.h> #include <core/class.h>
#include <engine/disp.h>
#include <subdev/bios.h> #include <subdev/bios.h>
#include <subdev/bios/dcb.h> #include <subdev/bios/dcb.h>
#include <subdev/bios/disp.h> #include <subdev/bios/disp.h>
...@@ -1346,13 +1344,13 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -1346,13 +1344,13 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nouveau_oclass *
nv50_disp_oclass = { nv50_disp_oclass = &(struct nv50_disp_impl) {
.handle = NV_ENGINE(DISP, 0x50), .base.base.handle = NV_ENGINE(DISP, 0x50),
.ofuncs = &(struct nouveau_ofuncs) { .base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_disp_ctor, .ctor = nv50_disp_ctor,
.dtor = _nouveau_disp_dtor, .dtor = _nouveau_disp_dtor,
.init = _nouveau_disp_init, .init = _nouveau_disp_init,
.fini = _nouveau_disp_fini, .fini = _nouveau_disp_fini,
}, },
}; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
View file @ a8f8b489
...@@ -8,9 +8,13 @@ ...@@ -8,9 +8,13 @@
#include <core/event.h> #include <core/event.h>
#include <engine/dmaobj.h> #include <engine/dmaobj.h>
#include <engine/disp.h>
#include "dport.h" #include "dport.h"
#include "priv.h"
struct nv50_disp_impl {
struct nouveau_disp_impl base;
};
struct nv50_disp_priv { struct nv50_disp_priv {
struct nouveau_disp base; struct nouveau_disp base;
......
drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
View file @ a8f8b489
...@@ -29,6 +29,10 @@ ...@@ -29,6 +29,10 @@
#include "nv50.h" #include "nv50.h"
/*******************************************************************************
* Base display object
******************************************************************************/
static struct nouveau_oclass static struct nouveau_oclass
nv84_disp_sclass[] = { nv84_disp_sclass[] = {
{ NV84_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, { NV84_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
...@@ -59,6 +63,10 @@ nv84_disp_base_oclass[] = { ...@@ -59,6 +63,10 @@ nv84_disp_base_oclass[] = {
{} {}
}; };
/*******************************************************************************
* Display engine implementation
******************************************************************************/
static int static int
nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
...@@ -91,13 +99,13 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -91,13 +99,13 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nouveau_oclass *
nv84_disp_oclass = { nv84_disp_oclass = &(struct nv50_disp_impl) {
.handle = NV_ENGINE(DISP, 0x82), .base.base.handle = NV_ENGINE(DISP, 0x82),
.ofuncs = &(struct nouveau_ofuncs) { .base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv84_disp_ctor, .ctor = nv84_disp_ctor,
.dtor = _nouveau_disp_dtor, .dtor = _nouveau_disp_dtor,
.init = _nouveau_disp_init, .init = _nouveau_disp_init,
.fini = _nouveau_disp_fini, .fini = _nouveau_disp_fini,
}, },
}; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
View file @ a8f8b489
...@@ -29,6 +29,10 @@ ...@@ -29,6 +29,10 @@
#include "nv50.h" #include "nv50.h"
/*******************************************************************************
* Base display object
******************************************************************************/
static struct nouveau_oclass static struct nouveau_oclass
nv94_disp_sclass[] = { nv94_disp_sclass[] = {
{ NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, { NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
...@@ -59,6 +63,10 @@ nv94_disp_base_oclass[] = { ...@@ -59,6 +63,10 @@ nv94_disp_base_oclass[] = {
{} {}
}; };
/*******************************************************************************
* Display engine implementation
******************************************************************************/
static int static int
nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
...@@ -92,13 +100,13 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -92,13 +100,13 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nouveau_oclass *
nv94_disp_oclass = { nv94_disp_oclass = &(struct nv50_disp_impl) {
.handle = NV_ENGINE(DISP, 0x88), .base.base.handle = NV_ENGINE(DISP, 0x88),
.ofuncs = &(struct nouveau_ofuncs) { .base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv94_disp_ctor, .ctor = nv94_disp_ctor,
.dtor = _nouveau_disp_dtor, .dtor = _nouveau_disp_dtor,
.init = _nouveau_disp_init, .init = _nouveau_disp_init,
.fini = _nouveau_disp_fini, .fini = _nouveau_disp_fini,
}, },
}; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
View file @ a8f8b489
...@@ -29,6 +29,10 @@ ...@@ -29,6 +29,10 @@
#include "nv50.h" #include "nv50.h"
/*******************************************************************************
* Base display object
******************************************************************************/
static struct nouveau_oclass static struct nouveau_oclass
nva0_disp_sclass[] = { nva0_disp_sclass[] = {
{ NVA0_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, { NVA0_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
...@@ -45,6 +49,10 @@ nva0_disp_base_oclass[] = { ...@@ -45,6 +49,10 @@ nva0_disp_base_oclass[] = {
{} {}
}; };
/*******************************************************************************
* Display engine implementation
******************************************************************************/
static int static int
nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
...@@ -77,13 +85,13 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -77,13 +85,13 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nouveau_oclass *
nva0_disp_oclass = { nva0_disp_oclass = &(struct nv50_disp_impl) {
.handle = NV_ENGINE(DISP, 0x83), .base.base.handle = NV_ENGINE(DISP, 0x83),
.ofuncs = &(struct nouveau_ofuncs) { .base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nva0_disp_ctor, .ctor = nva0_disp_ctor,
.dtor = _nouveau_disp_dtor, .dtor = _nouveau_disp_dtor,
.init = _nouveau_disp_init, .init = _nouveau_disp_init,
.fini = _nouveau_disp_fini, .fini = _nouveau_disp_fini,
}, },
}; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
View file @ a8f8b489
...@@ -29,6 +29,10 @@ ...@@ -29,6 +29,10 @@
#include "nv50.h" #include "nv50.h"
/*******************************************************************************
* Base display object
******************************************************************************/
static struct nouveau_oclass static struct nouveau_oclass
nva3_disp_sclass[] = { nva3_disp_sclass[] = {
{ NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
...@@ -60,6 +64,10 @@ nva3_disp_base_oclass[] = { ...@@ -60,6 +64,10 @@ nva3_disp_base_oclass[] = {
{} {}
}; };
/*******************************************************************************
* Display engine implementation
******************************************************************************/
static int static int
nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
...@@ -94,13 +102,13 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -94,13 +102,13 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nouveau_oclass *
nva3_disp_oclass = { nva3_disp_oclass = &(struct nv50_disp_impl) {
.handle = NV_ENGINE(DISP, 0x85), .base.base.handle = NV_ENGINE(DISP, 0x85),
.ofuncs = &(struct nouveau_ofuncs) { .base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nva3_disp_ctor, .ctor = nva3_disp_ctor,
.dtor = _nouveau_disp_dtor, .dtor = _nouveau_disp_dtor,
.init = _nouveau_disp_init, .init = _nouveau_disp_init,
.fini = _nouveau_disp_fini, .fini = _nouveau_disp_fini,
}, },
}; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
View file @ a8f8b489
...@@ -1035,13 +1035,13 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -1035,13 +1035,13 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nouveau_oclass *
nvd0_disp_oclass = { nvd0_disp_oclass = &(struct nv50_disp_impl) {
.handle = NV_ENGINE(DISP, 0x90), .base.base.handle = NV_ENGINE(DISP, 0x90),
.ofuncs = &(struct nouveau_ofuncs) { .base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvd0_disp_ctor, .ctor = nvd0_disp_ctor,
.dtor = _nouveau_disp_dtor, .dtor = _nouveau_disp_dtor,
.init = _nouveau_disp_init, .init = _nouveau_disp_init,
.fini = _nouveau_disp_fini, .fini = _nouveau_disp_fini,
}, },
}; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
View file @ a8f8b489
...@@ -29,6 +29,10 @@ ...@@ -29,6 +29,10 @@
#include "nv50.h" #include "nv50.h"
/*******************************************************************************
* Base display object
******************************************************************************/
static struct nouveau_oclass static struct nouveau_oclass
nve0_disp_sclass[] = { nve0_disp_sclass[] = {
{ NVE0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs }, { NVE0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
...@@ -45,6 +49,10 @@ nve0_disp_base_oclass[] = { ...@@ -45,6 +49,10 @@ nve0_disp_base_oclass[] = {
{} {}
}; };
/*******************************************************************************
* Display engine implementation
******************************************************************************/
static int static int
nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
...@@ -77,13 +85,13 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -77,13 +85,13 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nouveau_oclass *
nve0_disp_oclass = { nve0_disp_oclass = &(struct nv50_disp_impl) {
.handle = NV_ENGINE(DISP, 0x91), .base.base.handle = NV_ENGINE(DISP, 0x91),
.ofuncs = &(struct nouveau_ofuncs) { .base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_disp_ctor, .ctor = nve0_disp_ctor,
.dtor = _nouveau_disp_dtor, .dtor = _nouveau_disp_dtor,
.init = _nouveau_disp_init, .init = _nouveau_disp_init,
.fini = _nouveau_disp_fini, .fini = _nouveau_disp_fini,
}, },
}; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
View file @ a8f8b489
...@@ -29,6 +29,10 @@ ...@@ -29,6 +29,10 @@
#include "nv50.h" #include "nv50.h"
/*******************************************************************************
* Base display object
******************************************************************************/
static struct nouveau_oclass static struct nouveau_oclass
nvf0_disp_sclass[] = { nvf0_disp_sclass[] = {
{ NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs }, { NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
...@@ -45,6 +49,10 @@ nvf0_disp_base_oclass[] = { ...@@ -45,6 +49,10 @@ nvf0_disp_base_oclass[] = {
{} {}
}; };
/*******************************************************************************
* Display engine implementation
******************************************************************************/
static int static int
nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
...@@ -77,13 +85,13 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -77,13 +85,13 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0; return 0;
} }
struct nouveau_oclass struct nouveau_oclass *
nvf0_disp_oclass = { nvf0_disp_oclass = &(struct nv50_disp_impl) {
.handle = NV_ENGINE(DISP, 0x92), .base.base.handle = NV_ENGINE(DISP, 0x92),
.ofuncs = &(struct nouveau_ofuncs) { .base.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvf0_disp_ctor, .ctor = nvf0_disp_ctor,
.dtor = _nouveau_disp_dtor, .dtor = _nouveau_disp_dtor,
.init = _nouveau_disp_init, .init = _nouveau_disp_init,
.fini = _nouveau_disp_fini, .fini = _nouveau_disp_fini,
}, },
}; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/priv.h 0 → 100644
View file @ a8f8b489
#ifndef __NVKM_DISP_PRIV_H__
#define __NVKM_DISP_PRIV_H__
#include <engine/disp.h>
struct nouveau_disp_impl {
struct nouveau_oclass base;
};
#endif
drivers/gpu/drm/nouveau/core/include/engine/disp.h
View file @ a8f8b489
...@@ -36,14 +36,14 @@ void _nouveau_disp_dtor(struct nouveau_object *); ...@@ -36,14 +36,14 @@ void _nouveau_disp_dtor(struct nouveau_object *);
#define _nouveau_disp_init _nouveau_engine_init #define _nouveau_disp_init _nouveau_engine_init
#define _nouveau_disp_fini _nouveau_engine_fini #define _nouveau_disp_fini _nouveau_engine_fini
extern struct nouveau_oclass nv04_disp_oclass; extern struct nouveau_oclass *nv04_disp_oclass;
extern struct nouveau_oclass nv50_disp_oclass; extern struct nouveau_oclass *nv50_disp_oclass;
extern struct nouveau_oclass nv84_disp_oclass; extern struct nouveau_oclass *nv84_disp_oclass;
extern struct nouveau_oclass nva0_disp_oclass; extern struct nouveau_oclass *nva0_disp_oclass;
extern struct nouveau_oclass nv94_disp_oclass; extern struct nouveau_oclass *nv94_disp_oclass;
extern struct nouveau_oclass nva3_disp_oclass; extern struct nouveau_oclass *nva3_disp_oclass;
extern struct nouveau_oclass nvd0_disp_oclass; extern struct nouveau_oclass *nvd0_disp_oclass;
extern struct nouveau_oclass nve0_disp_oclass; extern struct nouveau_oclass *nve0_disp_oclass;
extern struct nouveau_oclass nvf0_disp_oclass; extern struct nouveau_oclass *nvf0_disp_oclass;
#endif #endif
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