Commit a914fc52 authored by Dave Jiang's avatar Dave Jiang Committed by Jon Mason

ntb: intel: add GNR support for Intel PCIe gen5 NTB

Add Intel Granite Rapids NTB PCI device ID and related enabling.
Expectation is same hardware interface as Saphire Rapids Xeon platforms.
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Acked-by: default avatarAllen Hubbe <allenbh@gmail.com>
Signed-off-by: default avatarJon Mason <jdmason@kudzu.us>
parent 45e1058b
...@@ -763,7 +763,7 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf, ...@@ -763,7 +763,7 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf,
return ndev_ntb_debugfs_read(filp, ubuf, count, offp); return ndev_ntb_debugfs_read(filp, ubuf, count, offp);
else if (pdev_is_gen3(ndev->ntb.pdev)) else if (pdev_is_gen3(ndev->ntb.pdev))
return ndev_ntb3_debugfs_read(filp, ubuf, count, offp); return ndev_ntb3_debugfs_read(filp, ubuf, count, offp);
else if (pdev_is_gen4(ndev->ntb.pdev)) else if (pdev_is_gen4(ndev->ntb.pdev) || pdev_is_gen5(ndev->ntb.pdev))
return ndev_ntb4_debugfs_read(filp, ubuf, count, offp); return ndev_ntb4_debugfs_read(filp, ubuf, count, offp);
return -ENXIO; return -ENXIO;
...@@ -1874,7 +1874,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, ...@@ -1874,7 +1874,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
rc = gen3_init_dev(ndev); rc = gen3_init_dev(ndev);
if (rc) if (rc)
goto err_init_dev; goto err_init_dev;
} else if (pdev_is_gen4(pdev)) { } else if (pdev_is_gen4(pdev) || pdev_is_gen5(pdev)) {
ndev->ntb.ops = &intel_ntb4_ops; ndev->ntb.ops = &intel_ntb4_ops;
rc = intel_ntb_init_pci(ndev, pdev); rc = intel_ntb_init_pci(ndev, pdev);
if (rc) if (rc)
...@@ -1904,7 +1904,8 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev, ...@@ -1904,7 +1904,8 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
err_register: err_register:
ndev_deinit_debugfs(ndev); ndev_deinit_debugfs(ndev);
if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev)) if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) ||
pdev_is_gen4(pdev) || pdev_is_gen5(pdev))
xeon_deinit_dev(ndev); xeon_deinit_dev(ndev);
err_init_dev: err_init_dev:
intel_ntb_deinit_pci(ndev); intel_ntb_deinit_pci(ndev);
...@@ -1920,7 +1921,8 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev) ...@@ -1920,7 +1921,8 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev)
ntb_unregister_device(&ndev->ntb); ntb_unregister_device(&ndev->ntb);
ndev_deinit_debugfs(ndev); ndev_deinit_debugfs(ndev);
if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev)) if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) ||
pdev_is_gen4(pdev) || pdev_is_gen5(pdev))
xeon_deinit_dev(ndev); xeon_deinit_dev(ndev);
intel_ntb_deinit_pci(ndev); intel_ntb_deinit_pci(ndev);
kfree(ndev); kfree(ndev);
...@@ -2047,6 +2049,8 @@ static const struct pci_device_id intel_ntb_pci_tbl[] = { ...@@ -2047,6 +2049,8 @@ static const struct pci_device_id intel_ntb_pci_tbl[] = {
/* GEN4 */ /* GEN4 */
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)}, {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)},
/* GEN5 PCIe */
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_GNR)},
{0} {0}
}; };
MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl); MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl);
......
...@@ -197,7 +197,7 @@ int gen4_init_dev(struct intel_ntb_dev *ndev) ...@@ -197,7 +197,7 @@ int gen4_init_dev(struct intel_ntb_dev *ndev)
ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET); ppd1 = ioread32(ndev->self_mmio + GEN4_PPD1_OFFSET);
if (pdev_is_ICX(pdev)) if (pdev_is_ICX(pdev))
ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1); ndev->ntb.topo = gen4_ppd_topo(ndev, ppd1);
else if (pdev_is_SPR(pdev)) else if (pdev_is_SPR(pdev) || pdev_is_gen5(pdev))
ndev->ntb.topo = spr_ppd_topo(ndev, ppd1); ndev->ntb.topo = spr_ppd_topo(ndev, ppd1);
dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1, dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd1,
ntb_topo_string(ndev->ntb.topo)); ntb_topo_string(ndev->ntb.topo));
......
...@@ -70,6 +70,7 @@ ...@@ -70,6 +70,7 @@
#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
#define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e #define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
#define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR 0x0db4
/* Ntb control and link status */ /* Ntb control and link status */
#define NTB_CTL_CFG_LOCK BIT(0) #define NTB_CTL_CFG_LOCK BIT(0)
...@@ -228,4 +229,10 @@ static inline int pdev_is_gen4(struct pci_dev *pdev) ...@@ -228,4 +229,10 @@ static inline int pdev_is_gen4(struct pci_dev *pdev)
return 0; return 0;
} }
static inline int pdev_is_gen5(struct pci_dev *pdev)
{
return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR;
}
#endif #endif
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