Commit a97fa68e authored by Borislav Petkov's avatar Borislav Petkov

amd64_edac: Cleanup NBCFG handling

The fact whether we are chipkill capable or not does not have any
bearing when computing the channel index on a ganged DCT configuration
so remove that. Also, simplify debug statements. Finally, remove old
error injection leftovers, while at it.
Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
parent c9f4f26e
...@@ -1011,7 +1011,7 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, ...@@ -1011,7 +1011,7 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
syndrome = extract_syndrome(err_info); syndrome = extract_syndrome(err_info);
/* CHIPKILL enabled */ /* CHIPKILL enabled */
if (err_info->nbcfg & K8_NBCFG_CHIPKILL) { if (err_info->nbcfg & NBCFG_CHIPKILL) {
channel = get_channel_from_ecc_syndrome(mci, syndrome); channel = get_channel_from_ecc_syndrome(mci, syndrome);
if (channel < 0) { if (channel < 0) {
/* /*
...@@ -1461,7 +1461,7 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci, ...@@ -1461,7 +1461,7 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
* ganged. Otherwise @chan should already contain the channel at * ganged. Otherwise @chan should already contain the channel at
* this point. * this point.
*/ */
if (dct_ganging_enabled(pvt) && (pvt->nbcfg & K8_NBCFG_CHIPKILL)) if (dct_ganging_enabled(pvt))
chan = get_channel_from_ecc_syndrome(mci, syndrome); chan = get_channel_from_ecc_syndrome(mci, syndrome);
if (chan >= 0) if (chan >= 0)
...@@ -2050,14 +2050,13 @@ static int init_csrows(struct mem_ctl_info *mci) ...@@ -2050,14 +2050,13 @@ static int init_csrows(struct mem_ctl_info *mci)
u32 val; u32 val;
int i, empty = 1; int i, empty = 1;
amd64_read_pci_cfg(pvt->F3, K8_NBCFG, &val); amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
pvt->nbcfg = val; pvt->nbcfg = val;
pvt->ctl_error_info.nbcfg = val;
debugf0("node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n", debugf0("node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
pvt->mc_node_id, val, pvt->mc_node_id, val,
!!(val & K8_NBCFG_CHIPKILL), !!(val & K8_NBCFG_ECC_ENABLE)); !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
for_each_chip_select(i, 0, pvt) { for_each_chip_select(i, 0, pvt) {
csrow = &mci->csrows[i]; csrow = &mci->csrows[i];
...@@ -2099,9 +2098,9 @@ static int init_csrows(struct mem_ctl_info *mci) ...@@ -2099,9 +2098,9 @@ static int init_csrows(struct mem_ctl_info *mci)
/* /*
* determine whether CHIPKILL or JUST ECC or NO ECC is operating * determine whether CHIPKILL or JUST ECC or NO ECC is operating
*/ */
if (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) if (pvt->nbcfg & NBCFG_ECC_ENABLE)
csrow->edac_mode = csrow->edac_mode =
(pvt->nbcfg & K8_NBCFG_CHIPKILL) ? (pvt->nbcfg & NBCFG_CHIPKILL) ?
EDAC_S4ECD4ED : EDAC_SECDED; EDAC_S4ECD4ED : EDAC_SECDED;
else else
csrow->edac_mode = EDAC_NONE; csrow->edac_mode = EDAC_NONE;
...@@ -2211,24 +2210,23 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid, ...@@ -2211,24 +2210,23 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
value |= mask; value |= mask;
amd64_write_pci_cfg(F3, NBCTL, value); amd64_write_pci_cfg(F3, NBCTL, value);
amd64_read_pci_cfg(F3, K8_NBCFG, &value); amd64_read_pci_cfg(F3, NBCFG, &value);
debugf0("1: node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n", debugf0("1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
nid, value, nid, value, !!(value & NBCFG_ECC_ENABLE));
!!(value & K8_NBCFG_CHIPKILL), !!(value & K8_NBCFG_ECC_ENABLE));
if (!(value & K8_NBCFG_ECC_ENABLE)) { if (!(value & NBCFG_ECC_ENABLE)) {
amd64_warn("DRAM ECC disabled on this node, enabling...\n"); amd64_warn("DRAM ECC disabled on this node, enabling...\n");
s->flags.nb_ecc_prev = 0; s->flags.nb_ecc_prev = 0;
/* Attempt to turn on DRAM ECC Enable */ /* Attempt to turn on DRAM ECC Enable */
value |= K8_NBCFG_ECC_ENABLE; value |= NBCFG_ECC_ENABLE;
amd64_write_pci_cfg(F3, K8_NBCFG, value); amd64_write_pci_cfg(F3, NBCFG, value);
amd64_read_pci_cfg(F3, K8_NBCFG, &value); amd64_read_pci_cfg(F3, NBCFG, &value);
if (!(value & K8_NBCFG_ECC_ENABLE)) { if (!(value & NBCFG_ECC_ENABLE)) {
amd64_warn("Hardware rejected DRAM ECC enable," amd64_warn("Hardware rejected DRAM ECC enable,"
"check memory DIMM configuration.\n"); "check memory DIMM configuration.\n");
ret = false; ret = false;
...@@ -2239,9 +2237,8 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid, ...@@ -2239,9 +2237,8 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
s->flags.nb_ecc_prev = 1; s->flags.nb_ecc_prev = 1;
} }
debugf0("2: node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n", debugf0("2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
nid, value, nid, value, !!(value & NBCFG_ECC_ENABLE));
!!(value & K8_NBCFG_CHIPKILL), !!(value & K8_NBCFG_ECC_ENABLE));
return ret; return ret;
} }
...@@ -2263,9 +2260,9 @@ static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid, ...@@ -2263,9 +2260,9 @@ static void restore_ecc_error_reporting(struct ecc_settings *s, u8 nid,
/* restore previous BIOS DRAM ECC "off" setting we force-enabled */ /* restore previous BIOS DRAM ECC "off" setting we force-enabled */
if (!s->flags.nb_ecc_prev) { if (!s->flags.nb_ecc_prev) {
amd64_read_pci_cfg(F3, K8_NBCFG, &value); amd64_read_pci_cfg(F3, NBCFG, &value);
value &= ~K8_NBCFG_ECC_ENABLE; value &= ~NBCFG_ECC_ENABLE;
amd64_write_pci_cfg(F3, K8_NBCFG, value); amd64_write_pci_cfg(F3, NBCFG, value);
} }
/* restore the NB Enable MCGCTL bit */ /* restore the NB Enable MCGCTL bit */
...@@ -2291,9 +2288,9 @@ static bool ecc_enabled(struct pci_dev *F3, u8 nid) ...@@ -2291,9 +2288,9 @@ static bool ecc_enabled(struct pci_dev *F3, u8 nid)
u8 ecc_en = 0; u8 ecc_en = 0;
bool nb_mce_en = false; bool nb_mce_en = false;
amd64_read_pci_cfg(F3, K8_NBCFG, &value); amd64_read_pci_cfg(F3, NBCFG, &value);
ecc_en = !!(value & K8_NBCFG_ECC_ENABLE); ecc_en = !!(value & NBCFG_ECC_ENABLE);
amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled")); amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled"));
nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid); nb_mce_en = amd64_nb_mce_bank_enabled_on_node(nid);
......
...@@ -246,9 +246,9 @@ ...@@ -246,9 +246,9 @@
*/ */
#define NBCTL 0x40 #define NBCTL 0x40
#define K8_NBCFG 0x44 #define NBCFG 0x44
#define K8_NBCFG_CHIPKILL BIT(23) #define NBCFG_CHIPKILL BIT(23)
#define K8_NBCFG_ECC_ENABLE BIT(22) #define NBCFG_ECC_ENABLE BIT(22)
#define K8_NBSL 0x48 #define K8_NBSL 0x48
...@@ -420,9 +420,6 @@ struct amd64_pvt { ...@@ -420,9 +420,6 @@ struct amd64_pvt {
/* x4 or x8 syndromes in use */ /* x4 or x8 syndromes in use */
u8 syn_type; u8 syn_type;
/* temp storage for when input is received from sysfs */
struct err_regs ctl_error_info;
/* place to store error injection parameters prior to issue */ /* place to store error injection parameters prior to issue */
struct error_injection injection; struct error_injection injection;
......
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